1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include "odm_precomp.h"
9
10 void odm_ConfigRFReg_8723B(
11 PDM_ODM_T pDM_Odm,
12 u32 Addr,
13 u32 Data,
14 ODM_RF_RADIO_PATH_E RF_PATH,
15 u32 RegAddr
16 )
17 {
18 if (Addr == 0xfe || Addr == 0xffe)
19 msleep(50);
20 else {
21 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
22 /* Add 1us delay between BB/RF register setting. */
23 udelay(1);
24
25 /* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. */
26 if (Addr == 0xb6) {
27 u32 getvalue = 0;
28 u8 count = 0;
29
30 getvalue = PHY_QueryRFReg(
31 pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
32 );
33
34 udelay(1);
35
36 while ((getvalue>>8) != (Data>>8)) {
37 count++;
38 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
39 udelay(1);
40 getvalue = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord);
41 ODM_RT_TRACE(
42 pDM_Odm,
43 ODM_COMP_INIT,
44 ODM_DBG_TRACE,
45 (
46 "===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n",
47 getvalue,
48 Data,
49 count
50 )
51 );
52 if (count > 5)
53 break;
54 }
55 }
56
57 if (Addr == 0xb2) {
58 u32 getvalue = 0;
59 u8 count = 0;
60
61 getvalue = PHY_QueryRFReg(
62 pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
63 );
64
65 udelay(1);
66
67 while (getvalue != Data) {
68 count++;
69 PHY_SetRFReg(
70 pDM_Odm->Adapter,
71 RF_PATH,
72 RegAddr,
73 bRFRegOffsetMask,
74 Data
75 );
76 udelay(1);
77 /* Do LCK againg */
78 PHY_SetRFReg(
79 pDM_Odm->Adapter,
80 RF_PATH,
81 0x18,
82 bRFRegOffsetMask,
83 0x0fc07
84 );
85 udelay(1);
86 getvalue = PHY_QueryRFReg(
87 pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
88 );
89 ODM_RT_TRACE(
90 pDM_Odm,
91 ODM_COMP_INIT,
92 ODM_DBG_TRACE,
93 (
94 "===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n",
95 getvalue,
96 Data,
97 count
98 )
99 );
100
101 if (count > 5)
102 break;
103 }
104 }
105 }
106 }
107
108
109 void odm_ConfigRF_RadioA_8723B(PDM_ODM_T pDM_Odm, u32 Addr, u32 Data)
110 {
111 u32 content = 0x1000; /* RF_Content: radioa_txt */
112 u32 maskforPhySet = (u32)(content&0xE000);
113
114 odm_ConfigRFReg_8723B(
115 pDM_Odm,
116 Addr,
117 Data,
118 ODM_RF_PATH_A,
119 Addr|maskforPhySet
120 );
121
122 ODM_RT_TRACE(
123 pDM_Odm,
124 ODM_COMP_INIT,
125 ODM_DBG_TRACE,
126 (
127 "===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n",
128 Addr,
129 Data
130 )
131 );
132 }
133
134 void odm_ConfigMAC_8723B(PDM_ODM_T pDM_Odm, u32 Addr, u8 Data)
135 {
136 rtw_write8(pDM_Odm->Adapter, Addr, Data);
137 ODM_RT_TRACE(
138 pDM_Odm,
139 ODM_COMP_INIT,
140 ODM_DBG_TRACE,
141 (
142 "===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n",
143 Addr,
144 Data
145 )
146 );
147 }
148
149 void odm_ConfigBB_AGC_8723B(
150 PDM_ODM_T pDM_Odm,
151 u32 Addr,
152 u32 Bitmask,
153 u32 Data
154 )
155 {
156 PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
157 /* Add 1us delay between BB/RF register setting. */
158 udelay(1);
159
160 ODM_RT_TRACE(
161 pDM_Odm,
162 ODM_COMP_INIT,
163 ODM_DBG_TRACE,
164 (
165 "===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n",
166 Addr,
167 Data
168 )
169 );
170 }
171
172 void odm_ConfigBB_PHY_REG_PG_8723B(
173 PDM_ODM_T pDM_Odm,
174 u32 Band,
175 u32 RfPath,
176 u32 TxNum,
177 u32 Addr,
178 u32 Bitmask,
179 u32 Data
180 )
181 {
182 if (Addr == 0xfe || Addr == 0xffe)
183 msleep(50);
184 else {
185 PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
186 }
187 ODM_RT_TRACE(
188 pDM_Odm,
189 ODM_COMP_INIT,
190 ODM_DBG_LOUD,
191 (
192 "===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n",
193 Addr,
194 Bitmask,
195 Data
196 )
197 );
198 }
199
200 void odm_ConfigBB_PHY_8723B(
201 PDM_ODM_T pDM_Odm,
202 u32 Addr,
203 u32 Bitmask,
204 u32 Data
205 )
206 {
207 if (Addr == 0xfe)
208 msleep(50);
209 else if (Addr == 0xfd)
210 mdelay(5);
211 else if (Addr == 0xfc)
212 mdelay(1);
213 else if (Addr == 0xfb)
214 udelay(50);
215 else if (Addr == 0xfa)
216 udelay(5);
217 else if (Addr == 0xf9)
218 udelay(1);
219 else {
220 PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
221 }
222
223 /* Add 1us delay between BB/RF register setting. */
224 udelay(1);
225 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
226 }
227
228 void odm_ConfigBB_TXPWR_LMT_8723B(
229 PDM_ODM_T pDM_Odm,
230 u8 *Regulation,
231 u8 *Band,
232 u8 *Bandwidth,
233 u8 *RateSection,
234 u8 *RfPath,
235 u8 *Channel,
236 u8 *PowerLimit
237 )
238 {
239 PHY_SetTxPowerLimit(
240 pDM_Odm->Adapter,
241 Regulation,
242 Band,
243 Bandwidth,
244 RateSection,
245 RfPath,
246 Channel,
247 PowerLimit
248 );
249 }