root/drivers/staging/rtl8723bs/hal/odm_EdcaTurboCheck.c

DEFINITIONS

1. ODM_EdcaTurboInit
2. odm_EdcaTurboCheck
3. odm_EdcaTurboCheckCE

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 
   8 #include "odm_precomp.h"
   9 
  10 static u32 edca_setting_DL_GMode[HT_IOT_PEER_MAX] = {
  11 /*UNKNOWN, REALTEK_90, ALTEK_92SE       BROADCOM, LINK  ATHEROS,
  12  *CISCO, MERU, MARVELL, 92U_AP, SELF_AP
  13  */
  14         0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322,
  15         0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b
  16 };
  17 
  18 static u32 edca_setting_UL[HT_IOT_PEER_MAX] = {
  19 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM, RALINK, ATHEROS,
  20  *CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx)
  21  */
  22         0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322,
  23         0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
  24 
  25 static u32 edca_setting_DL[HT_IOT_PEER_MAX] = {
  26 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM, RALINK, ATHEROS,
  27  *CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)
  28  */
  29         0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630,
  30         0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
  31 
  32 void ODM_EdcaTurboInit(void *pDM_VOID)
  33 {
  34         PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
  35         struct adapter *Adapter = pDM_Odm->Adapter;
  36 
  37         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
  38         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
  39         Adapter->recvpriv.bIsAnyNonBEPkts = false;
  40 
  41         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
  42                      ("Original VO PARAM: 0x%x\n",
  43                       rtw_read32(pDM_Odm->Adapter, ODM_EDCA_VO_PARAM)));
  44         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
  45                      ("Original VI PARAM: 0x%x\n",
  46                       rtw_read32(pDM_Odm->Adapter, ODM_EDCA_VI_PARAM)));
  47         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
  48                      ("Original BE PARAM: 0x%x\n",
  49                       rtw_read32(pDM_Odm->Adapter, ODM_EDCA_BE_PARAM)));
  50         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
  51                      ("Original BK PARAM: 0x%x\n",
  52                       rtw_read32(pDM_Odm->Adapter, ODM_EDCA_BK_PARAM)));
  53 }       /*  ODM_InitEdcaTurbo */
  54 
  55 void odm_EdcaTurboCheck(void *pDM_VOID)
  56 {
  57         /*  In HW integration first stage, we provide 4 different handles to
  58          *  operate at the same time. In stage2/3, we need to prove universal
  59          *  interface and merge all HW dynamic mechanism.
  60          */
  61         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;
  62 
  63         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
  64                      ("odm_EdcaTurboCheck ========================>\n"));
  65 
  66         if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
  67                 return;
  68 
  69         odm_EdcaTurboCheckCE(pDM_Odm);
  70         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
  71                      ("<========================odm_EdcaTurboCheck\n"));
  72 }       /*  odm_CheckEdcaTurbo */
  73 
  74 void odm_EdcaTurboCheckCE(void *pDM_VOID)
  75 {
  76         PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
  77         struct adapter *Adapter = pDM_Odm->Adapter;
  78         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
  79         struct recv_priv *precvpriv = &(Adapter->recvpriv);
  80         struct registry_priv *pregpriv = &Adapter->registrypriv;
  81         struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
  82         struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
  83         u32 EDCA_BE_UL = 0x5ea42b;
  84         u32 EDCA_BE_DL = 0x5ea42b;
  85         u32 iot_peer = 0;
  86         u8 wirelessmode = 0xFF;         /* invalid value */
  87         u32 trafficIndex;
  88         u32 edca_param;
  89         u64     cur_tx_bytes = 0;
  90         u64     cur_rx_bytes = 0;
  91         u8 bbtchange = false;
  92         u8 biasonrx = false;
  93         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
  94 
  95         if (!pDM_Odm->bLinked) {
  96                 precvpriv->bIsAnyNonBEPkts = false;
  97                 return;
  98         }
  99 
 100         if (pregpriv->wifi_spec == 1) {
 101                 precvpriv->bIsAnyNonBEPkts = false;
 102                 return;
 103         }
 104 
 105         if (pDM_Odm->pwirelessmode)
 106                 wirelessmode = *(pDM_Odm->pwirelessmode);
 107 
 108         iot_peer = pmlmeinfo->assoc_AP_vendor;
 109 
 110         if (iot_peer >=  HT_IOT_PEER_MAX) {
 111                 precvpriv->bIsAnyNonBEPkts = false;
 112                 return;
 113         }
 114 
 115         /*  Check if the status needs to be changed. */
 116         if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
 117                 cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
 118                 cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
 119 
 120                 /* traffic, TX or RX */
 121                 if (biasonrx) {
 122                         if (cur_tx_bytes > (cur_rx_bytes << 2)) {
 123                                 /*  Uplink TP is present. */
 124                                 trafficIndex = UP_LINK;
 125                         } else { /*  Balance TP is present. */
 126                                 trafficIndex = DOWN_LINK;
 127                         }
 128                 } else {
 129                         if (cur_rx_bytes > (cur_tx_bytes << 2)) {
 130                                 /*  Downlink TP is present. */
 131                                 trafficIndex = DOWN_LINK;
 132                         } else { /*  Balance TP is present. */
 133                                 trafficIndex = UP_LINK;
 134                         }
 135                 }
 136 
 137                 /* 92D txop can't be set to 0x3e for cisco1250 */
 138                 if ((iot_peer == HT_IOT_PEER_CISCO) &&
 139                     (wirelessmode == ODM_WM_N24G)) {
 140                         EDCA_BE_DL = edca_setting_DL[iot_peer];
 141                         EDCA_BE_UL = edca_setting_UL[iot_peer];
 142                 } else if ((iot_peer == HT_IOT_PEER_CISCO) &&
 143                            ((wirelessmode == ODM_WM_G) ||
 144                             (wirelessmode == (ODM_WM_B | ODM_WM_G)) ||
 145                             (wirelessmode == ODM_WM_A) ||
 146                             (wirelessmode == ODM_WM_B))) {
 147                         EDCA_BE_DL = edca_setting_DL_GMode[iot_peer];
 148                 } else if ((iot_peer == HT_IOT_PEER_AIRGO) &&
 149                            ((wirelessmode == ODM_WM_G) ||
 150                             (wirelessmode == ODM_WM_A))) {
 151                         EDCA_BE_DL = 0xa630;
 152                 } else if (iot_peer == HT_IOT_PEER_MARVELL) {
 153                         EDCA_BE_DL = edca_setting_DL[iot_peer];
 154                         EDCA_BE_UL = edca_setting_UL[iot_peer];
 155                 } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
 156                         /*  Set DL EDCA for Atheros peer to 0x3ea42b. */
 157                         EDCA_BE_DL = edca_setting_DL[iot_peer];
 158                 }
 159 
 160                 if (trafficIndex == DOWN_LINK)
 161                         edca_param = EDCA_BE_DL;
 162                 else
 163                         edca_param = EDCA_BE_UL;
 164 
 165                 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
 166 
 167                 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
 168 
 169                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
 170         } else {
 171                 /*  Turn Off EDCA turbo here. */
 172                 /*  Restore original EDCA according to the declaration of AP. */
 173                  if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
 174                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
 175                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
 176                 }
 177         }
 178 }