This source file includes following definitions.
- _FWDownloadEnable
- _BlockWrite
- _PageWrite
- _WriteFW
- _8051Reset8723
- polling_fwdl_chksum
- _FWFreeToGo
- rtl8723b_FirmwareSelfReset
- rtl8723b_FirmwareDownload
- rtl8723b_InitializeFirmwareVars
- SetFwRelatedForWoWLAN8723b
- rtl8723b_free_hal_data
- hal_EfuseSwitchToBank
- Hal_GetEfuseDefinition
- Hal_BT_EfusePowerSwitch
- Hal_EfusePowerSwitch
- hal_ReadEFuse_WiFi
- hal_ReadEFuse_BT
- Hal_ReadEFuse
- hal_EfuseGetCurrentSize_WiFi
- hal_EfuseGetCurrentSize_BT
- Hal_EfuseGetCurrentSize
- Hal_EfuseWordEnableDataWrite
- Hal_EfusePgPacketRead
- hal_EfusePgCheckAvailableAddr
- hal_EfuseConstructPGPkt
- hal_EfusePartialWriteCheck
- hal_EfusePgPacketWrite1ByteHeader
- hal_EfusePgPacketWrite2ByteHeader
- hal_EfusePgPacketWriteHeader
- hal_EfusePgPacketWriteData
- Hal_EfusePgPacketWrite
- Hal_EfusePgPacketWrite_BT
- ReadChipVersion8723B
- rtl8723b_read_chip_version
- rtl8723b_InitBeaconParameters
- _InitBurstPktLen_8723BS
- ResumeTxBeacon
- StopTxBeacon
- _BeaconFunctionEnable
- rtl8723b_SetBeaconRelatedRegisters
- rtl8723b_GetHalODMVar
- rtl8723b_SetHalODMVar
- hal_notch_filter_8723b
- UpdateHalRAMask8723B
- rtl8723b_set_hal_ops
- rtl8723b_InitAntenna_Selection
- rtl8723b_init_default_value
- GetEEPROMSize8723B
- rtl8723b_InitLLTTable
- Hal_GetChnlGroup8723B
- Hal_InitPGData
- Hal_EfuseParseIDCode
- Hal_ReadPowerValueFromPROM_8723B
- Hal_EfuseParseTxPowerInfo_8723B
- Hal_EfuseParseBTCoexistInfo_8723B
- Hal_EfuseParseEEPROMVer_8723B
- Hal_EfuseParsePackageType_8723B
- Hal_EfuseParseVoltage_8723B
- Hal_EfuseParseChnlPlan_8723B
- Hal_EfuseParseCustomerID_8723B
- Hal_EfuseParseAntennaDiversity_8723B
- Hal_EfuseParseXtal_8723B
- Hal_EfuseParseThermalMeter_8723B
- Hal_ReadRFGainOffset
- BWMapping_8723B
- SCMapping_8723B
- rtl8723b_cal_txdesc_chksum
- fill_txdesc_sectype
- fill_txdesc_vcs_8723b
- fill_txdesc_phy_8723b
- rtl8723b_fill_default_txdesc
- rtl8723b_update_txdesc
- rtl8723b_fill_fake_txdesc
- hw_var_set_opmode
- hw_var_set_macaddr
- hw_var_set_bssid
- hw_var_set_bcn_func
- hw_var_set_correct_tsf
- hw_var_set_mlme_disconnect
- hw_var_set_mlme_sitesurvey
- hw_var_set_mlme_join
- CCX_FwC2HTxRpt_8723b
- c2h_id_filter_ccx_8723b
- c2h_handler_8723b
- process_c2h_event
- C2HPacketHandler_8723B
- SetHwReg8723B
- GetHwReg8723B
- SetHalDefVar8723B
- GetHalDefVar8723B
- Hal_DetectWoWMode
- rtl8723b_start_thread
- rtl8723b_stop_thread
- rtl8723bs_init_checkbthang_workqueue
- rtl8723bs_free_checkbthang_workqueue
- rtl8723bs_cancle_checkbthang_workqueue
- rtl8723bs_hal_check_bt_hang
1
2
3
4
5
6
7 #define _HAL_INIT_C_
8
9 #include <linux/firmware.h>
10 #include <linux/slab.h>
11 #include <drv_types.h>
12 #include <rtw_debug.h>
13 #include <rtl8723b_hal.h>
14 #include "hal_com_h2c.h"
15
16 static void _FWDownloadEnable(struct adapter *padapter, bool enable)
17 {
18 u8 tmp, count = 0;
19
20 if (enable) {
21
22 tmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
23 rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|0x04);
24
25 tmp = rtw_read8(padapter, REG_MCUFWDL);
26 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
27
28 do {
29 tmp = rtw_read8(padapter, REG_MCUFWDL);
30 if (tmp & 0x01)
31 break;
32 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
33 msleep(1);
34 } while (count++ < 100);
35
36 if (count > 0)
37 DBG_871X("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count);
38
39
40 tmp = rtw_read8(padapter, REG_MCUFWDL+2);
41 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7);
42 } else {
43
44 tmp = rtw_read8(padapter, REG_MCUFWDL);
45 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe);
46 }
47 }
48
49 static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize)
50 {
51 int ret = _SUCCESS;
52
53 u32 blockSize_p1 = 4;
54 u32 blockSize_p2 = 8;
55 u32 blockSize_p3 = 1;
56 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
57 u32 remainSize_p1 = 0, remainSize_p2 = 0;
58 u8 *bufferPtr = buffer;
59 u32 i = 0, offset = 0;
60
61
62
63
64 blockCount_p1 = buffSize / blockSize_p1;
65 remainSize_p1 = buffSize % blockSize_p1;
66
67 if (blockCount_p1) {
68 RT_TRACE(
69 _module_hal_init_c_,
70 _drv_notice_,
71 (
72 "_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n",
73 buffSize,
74 blockSize_p1,
75 blockCount_p1,
76 remainSize_p1
77 )
78 );
79 }
80
81 for (i = 0; i < blockCount_p1; i++) {
82 ret = rtw_write32(padapter, (FW_8723B_START_ADDRESS + i * blockSize_p1), *((u32 *)(bufferPtr + i * blockSize_p1)));
83 if (ret == _FAIL) {
84 printk("====>%s %d i:%d\n", __func__, __LINE__, i);
85 goto exit;
86 }
87 }
88
89
90 if (remainSize_p1) {
91 offset = blockCount_p1 * blockSize_p1;
92
93 blockCount_p2 = remainSize_p1/blockSize_p2;
94 remainSize_p2 = remainSize_p1%blockSize_p2;
95
96 if (blockCount_p2) {
97 RT_TRACE(
98 _module_hal_init_c_,
99 _drv_notice_,
100 (
101 "_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n",
102 (buffSize-offset),
103 blockSize_p2,
104 blockCount_p2,
105 remainSize_p2
106 )
107 );
108 }
109
110 }
111
112
113 if (remainSize_p2) {
114 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
115
116 blockCount_p3 = remainSize_p2 / blockSize_p3;
117
118 RT_TRACE(_module_hal_init_c_, _drv_notice_,
119 ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n",
120 (buffSize-offset), blockSize_p3, blockCount_p3));
121
122 for (i = 0; i < blockCount_p3; i++) {
123 ret = rtw_write8(padapter, (FW_8723B_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
124
125 if (ret == _FAIL) {
126 printk("====>%s %d i:%d\n", __func__, __LINE__, i);
127 goto exit;
128 }
129 }
130 }
131 exit:
132 return ret;
133 }
134
135 static int _PageWrite(
136 struct adapter *padapter,
137 u32 page,
138 void *buffer,
139 u32 size
140 )
141 {
142 u8 value8;
143 u8 u8Page = (u8) (page & 0x07);
144
145 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page;
146 rtw_write8(padapter, REG_MCUFWDL+2, value8);
147
148 return _BlockWrite(padapter, buffer, size);
149 }
150
151 static int _WriteFW(struct adapter *padapter, void *buffer, u32 size)
152 {
153
154
155 int ret = _SUCCESS;
156 u32 pageNums, remainSize;
157 u32 page, offset;
158 u8 *bufferPtr = buffer;
159
160 pageNums = size / MAX_DLFW_PAGE_SIZE;
161
162 remainSize = size % MAX_DLFW_PAGE_SIZE;
163
164 for (page = 0; page < pageNums; page++) {
165 offset = page * MAX_DLFW_PAGE_SIZE;
166 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_DLFW_PAGE_SIZE);
167
168 if (ret == _FAIL) {
169 printk("====>%s %d\n", __func__, __LINE__);
170 goto exit;
171 }
172 }
173
174 if (remainSize) {
175 offset = pageNums * MAX_DLFW_PAGE_SIZE;
176 page = pageNums;
177 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);
178
179 if (ret == _FAIL) {
180 printk("====>%s %d\n", __func__, __LINE__);
181 goto exit;
182 }
183 }
184 RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n"));
185
186 exit:
187 return ret;
188 }
189
190 void _8051Reset8723(struct adapter *padapter)
191 {
192 u8 cpu_rst;
193 u8 io_rst;
194
195
196
197
198
199 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1);
200 io_rst &= ~BIT(0);
201 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst);
202
203 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
204 cpu_rst &= ~BIT(2);
205 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst);
206
207
208
209 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1);
210 io_rst |= BIT(0);
211 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst);
212
213 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
214 cpu_rst |= BIT(2);
215 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst);
216
217 DBG_8192C("%s: Finish\n", __func__);
218 }
219
220 u8 g_fwdl_chksum_fail;
221
222 static s32 polling_fwdl_chksum(
223 struct adapter *adapter, u32 min_cnt, u32 timeout_ms
224 )
225 {
226 s32 ret = _FAIL;
227 u32 value32;
228 unsigned long start = jiffies;
229 u32 cnt = 0;
230
231
232 do {
233 cnt++;
234 value32 = rtw_read32(adapter, REG_MCUFWDL);
235 if (value32 & FWDL_ChkSum_rpt || adapter->bSurpriseRemoved || adapter->bDriverStopped)
236 break;
237 yield();
238 } while (jiffies_to_msecs(jiffies-start) < timeout_ms || cnt < min_cnt);
239
240 if (!(value32 & FWDL_ChkSum_rpt)) {
241 goto exit;
242 }
243
244 if (g_fwdl_chksum_fail) {
245 DBG_871X("%s: fwdl test case: fwdl_chksum_fail\n", __func__);
246 g_fwdl_chksum_fail--;
247 goto exit;
248 }
249
250 ret = _SUCCESS;
251
252 exit:
253 DBG_871X(
254 "%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n",
255 __func__,
256 (ret == _SUCCESS) ? "OK" : "Fail",
257 cnt,
258 jiffies_to_msecs(jiffies-start),
259 value32
260 );
261
262 return ret;
263 }
264
265 u8 g_fwdl_wintint_rdy_fail;
266
267 static s32 _FWFreeToGo(struct adapter *adapter, u32 min_cnt, u32 timeout_ms)
268 {
269 s32 ret = _FAIL;
270 u32 value32;
271 unsigned long start = jiffies;
272 u32 cnt = 0;
273
274 value32 = rtw_read32(adapter, REG_MCUFWDL);
275 value32 |= MCUFWDL_RDY;
276 value32 &= ~WINTINI_RDY;
277 rtw_write32(adapter, REG_MCUFWDL, value32);
278
279 _8051Reset8723(adapter);
280
281
282 do {
283 cnt++;
284 value32 = rtw_read32(adapter, REG_MCUFWDL);
285 if (value32 & WINTINI_RDY || adapter->bSurpriseRemoved || adapter->bDriverStopped)
286 break;
287 yield();
288 } while (jiffies_to_msecs(jiffies - start) < timeout_ms || cnt < min_cnt);
289
290 if (!(value32 & WINTINI_RDY)) {
291 goto exit;
292 }
293
294 if (g_fwdl_wintint_rdy_fail) {
295 DBG_871X("%s: fwdl test case: wintint_rdy_fail\n", __func__);
296 g_fwdl_wintint_rdy_fail--;
297 goto exit;
298 }
299
300 ret = _SUCCESS;
301
302 exit:
303 DBG_871X(
304 "%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n",
305 __func__,
306 (ret == _SUCCESS) ? "OK" : "Fail",
307 cnt,
308 jiffies_to_msecs(jiffies-start),
309 value32
310 );
311
312 return ret;
313 }
314
315 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
316
317 void rtl8723b_FirmwareSelfReset(struct adapter *padapter)
318 {
319 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
320 u8 u1bTmp;
321 u8 Delay = 100;
322
323 if (
324 !(IS_FW_81xxC(padapter) && ((pHalData->FirmwareVersion < 0x21) || (pHalData->FirmwareVersion == 0x21 && pHalData->FirmwareSubVersion < 0x01)))
325 ) {
326
327 rtw_write8(padapter, REG_HMETFR+3, 0x20);
328
329 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
330 while (u1bTmp & BIT2) {
331 Delay--;
332 if (Delay == 0)
333 break;
334 udelay(50);
335 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
336 }
337 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("-%s: 8051 reset success (%d)\n", __func__, Delay));
338
339 if (Delay == 0) {
340 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("%s: Force 8051 reset!!!\n", __func__));
341
342 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
343 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
344 }
345 }
346 }
347
348
349
350
351
352
353 s32 rtl8723b_FirmwareDownload(struct adapter *padapter, bool bUsedWoWLANFw)
354 {
355 s32 rtStatus = _SUCCESS;
356 u8 write_fw = 0;
357 unsigned long fwdl_start_time;
358 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
359 struct rt_firmware *pFirmware;
360 struct rt_firmware *pBTFirmware;
361 struct rt_firmware_hdr *pFwHdr = NULL;
362 u8 *pFirmwareBuf;
363 u32 FirmwareLen;
364 const struct firmware *fw;
365 struct device *device = dvobj_to_dev(padapter->dvobj);
366 u8 *fwfilepath;
367 struct dvobj_priv *psdpriv = padapter->dvobj;
368 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
369 u8 tmp_ps;
370
371 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__));
372 #ifdef CONFIG_WOWLAN
373 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("+%s, bUsedWoWLANFw:%d\n", __func__, bUsedWoWLANFw));
374 #endif
375 pFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL);
376 if (!pFirmware)
377 return _FAIL;
378 pBTFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL);
379 if (!pBTFirmware) {
380 kfree(pFirmware);
381 return _FAIL;
382 }
383 tmp_ps = rtw_read8(padapter, 0xa3);
384 tmp_ps &= 0xf8;
385 tmp_ps |= 0x02;
386
387 rtw_write8(padapter, 0xa3, tmp_ps);
388
389 tmp_ps = rtw_read8(padapter, 0xa0);
390 tmp_ps &= 0x03;
391 if (tmp_ps != 0x01) {
392 DBG_871X(FUNC_ADPT_FMT" tmp_ps =%x\n", FUNC_ADPT_ARG(padapter), tmp_ps);
393 pdbgpriv->dbg_downloadfw_pwr_state_cnt++;
394 }
395
396 #ifdef CONFIG_WOWLAN
397 if (bUsedWoWLANFw)
398 fwfilepath = "rtlwifi/rtl8723bs_wowlan.bin";
399 else
400 #endif
401 fwfilepath = "rtlwifi/rtl8723bs_nic.bin";
402
403 pr_info("rtl8723bs: acquire FW from file:%s\n", fwfilepath);
404
405 rtStatus = request_firmware(&fw, fwfilepath, device);
406 if (rtStatus) {
407 pr_err("Request firmware failed with error 0x%x\n", rtStatus);
408 rtStatus = _FAIL;
409 goto exit;
410 }
411
412 if (!fw) {
413 pr_err("Firmware %s not available\n", fwfilepath);
414 rtStatus = _FAIL;
415 goto exit;
416 }
417
418 if (fw->size > FW_8723B_SIZE) {
419 rtStatus = _FAIL;
420 RT_TRACE(
421 _module_hal_init_c_,
422 _drv_err_,
423 ("Firmware size exceed 0x%X. Check it.\n", FW_8188E_SIZE)
424 );
425 goto exit;
426 }
427
428 pFirmware->fw_buffer_sz = kmemdup(fw->data, fw->size, GFP_KERNEL);
429 if (!pFirmware->fw_buffer_sz) {
430 rtStatus = _FAIL;
431 goto exit;
432 }
433
434 pFirmware->fw_length = fw->size;
435 release_firmware(fw);
436 if (pFirmware->fw_length > FW_8723B_SIZE) {
437 rtStatus = _FAIL;
438 DBG_871X_LEVEL(_drv_emerg_, "Firmware size:%u exceed %u\n", pFirmware->fw_length, FW_8723B_SIZE);
439 goto release_fw1;
440 }
441
442 pFirmwareBuf = pFirmware->fw_buffer_sz;
443 FirmwareLen = pFirmware->fw_length;
444
445
446 pFwHdr = (struct rt_firmware_hdr *)pFirmwareBuf;
447
448 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->version);
449 pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->subversion);
450 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->signature);
451
452 DBG_871X(
453 "%s: fw_ver =%x fw_subver =%04x sig = 0x%x, Month =%02x, Date =%02x, Hour =%02x, Minute =%02x\n",
454 __func__,
455 pHalData->FirmwareVersion,
456 pHalData->FirmwareSubVersion,
457 pHalData->FirmwareSignature,
458 pFwHdr->month,
459 pFwHdr->date,
460 pFwHdr->hour,
461 pFwHdr->minute
462 );
463
464 if (IS_FW_HEADER_EXIST_8723B(pFwHdr)) {
465 DBG_871X("%s(): Shift for fw header!\n", __func__);
466
467 pFirmwareBuf = pFirmwareBuf + 32;
468 FirmwareLen = FirmwareLen - 32;
469 }
470
471
472
473 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
474 rtw_write8(padapter, REG_MCUFWDL, 0x00);
475 rtl8723b_FirmwareSelfReset(padapter);
476 }
477
478 _FWDownloadEnable(padapter, true);
479 fwdl_start_time = jiffies;
480 while (
481 !padapter->bDriverStopped &&
482 !padapter->bSurpriseRemoved &&
483 (write_fw++ < 3 || jiffies_to_msecs(jiffies - fwdl_start_time) < 500)
484 ) {
485
486 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt);
487
488 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
489 if (rtStatus != _SUCCESS)
490 continue;
491
492 rtStatus = polling_fwdl_chksum(padapter, 5, 50);
493 if (rtStatus == _SUCCESS)
494 break;
495 }
496 _FWDownloadEnable(padapter, false);
497 if (_SUCCESS != rtStatus)
498 goto fwdl_stat;
499
500 rtStatus = _FWFreeToGo(padapter, 10, 200);
501 if (_SUCCESS != rtStatus)
502 goto fwdl_stat;
503
504 fwdl_stat:
505 DBG_871X(
506 "FWDL %s. write_fw:%u, %dms\n",
507 (rtStatus == _SUCCESS)?"success":"fail",
508 write_fw,
509 jiffies_to_msecs(jiffies - fwdl_start_time)
510 );
511
512 exit:
513 kfree(pFirmware->fw_buffer_sz);
514 kfree(pFirmware);
515 release_fw1:
516 kfree(pBTFirmware);
517 DBG_871X(" <=== rtl8723b_FirmwareDownload()\n");
518 return rtStatus;
519 }
520
521 void rtl8723b_InitializeFirmwareVars(struct adapter *padapter)
522 {
523 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
524
525
526 adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = false;
527
528
529 rtw_write8(padapter, REG_HMETFR, 0x0f);
530
531
532 pHalData->LastHMEBoxNum = 0;
533
534
535
536 }
537
538 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
539
540
541
542
543
544
545
546
547
548
549 void SetFwRelatedForWoWLAN8723b(
550 struct adapter *padapter, u8 bHostIsGoingtoSleep
551 )
552 {
553 int status = _FAIL;
554
555
556
557 status = rtl8723b_FirmwareDownload(padapter, bHostIsGoingtoSleep);
558 if (status != _SUCCESS) {
559 DBG_871X("SetFwRelatedForWoWLAN8723b(): Re-Download Firmware failed!!\n");
560 return;
561 } else {
562 DBG_871X("SetFwRelatedForWoWLAN8723b(): Re-Download Firmware Success !!\n");
563 }
564
565
566
567 rtl8723b_InitializeFirmwareVars(padapter);
568 }
569 #endif
570
571 static void rtl8723b_free_hal_data(struct adapter *padapter)
572 {
573 }
574
575
576
577
578 static u8 hal_EfuseSwitchToBank(
579 struct adapter *padapter, u8 bank, bool bPseudoTest
580 )
581 {
582 u8 bRet = false;
583 u32 value32 = 0;
584 #ifdef HAL_EFUSE_MEMORY
585 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
586 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
587 #endif
588
589
590 DBG_8192C("%s: Efuse switch bank to %d\n", __func__, bank);
591 if (bPseudoTest) {
592 #ifdef HAL_EFUSE_MEMORY
593 pEfuseHal->fakeEfuseBank = bank;
594 #else
595 fakeEfuseBank = bank;
596 #endif
597 bRet = true;
598 } else {
599 value32 = rtw_read32(padapter, EFUSE_TEST);
600 bRet = true;
601 switch (bank) {
602 case 0:
603 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
604 break;
605 case 1:
606 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
607 break;
608 case 2:
609 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
610 break;
611 case 3:
612 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
613 break;
614 default:
615 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
616 bRet = false;
617 break;
618 }
619 rtw_write32(padapter, EFUSE_TEST, value32);
620 }
621
622 return bRet;
623 }
624
625 static void Hal_GetEfuseDefinition(
626 struct adapter *padapter,
627 u8 efuseType,
628 u8 type,
629 void *pOut,
630 bool bPseudoTest
631 )
632 {
633 switch (type) {
634 case TYPE_EFUSE_MAX_SECTION:
635 {
636 u8 *pMax_section;
637 pMax_section = pOut;
638
639 if (efuseType == EFUSE_WIFI)
640 *pMax_section = EFUSE_MAX_SECTION_8723B;
641 else
642 *pMax_section = EFUSE_BT_MAX_SECTION;
643 }
644 break;
645
646 case TYPE_EFUSE_REAL_CONTENT_LEN:
647 {
648 u16 *pu2Tmp;
649 pu2Tmp = pOut;
650
651 if (efuseType == EFUSE_WIFI)
652 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B;
653 else
654 *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
655 }
656 break;
657
658 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
659 {
660 u16 *pu2Tmp;
661 pu2Tmp = pOut;
662
663 if (efuseType == EFUSE_WIFI)
664 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES);
665 else
666 *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK);
667 }
668 break;
669
670 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
671 {
672 u16 *pu2Tmp;
673 pu2Tmp = pOut;
674
675 if (efuseType == EFUSE_WIFI)
676 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES);
677 else
678 *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN-(EFUSE_PROTECT_BYTES_BANK*3));
679 }
680 break;
681
682 case TYPE_EFUSE_MAP_LEN:
683 {
684 u16 *pu2Tmp;
685 pu2Tmp = pOut;
686
687 if (efuseType == EFUSE_WIFI)
688 *pu2Tmp = EFUSE_MAX_MAP_LEN;
689 else
690 *pu2Tmp = EFUSE_BT_MAP_LEN;
691 }
692 break;
693
694 case TYPE_EFUSE_PROTECT_BYTES_BANK:
695 {
696 u8 *pu1Tmp;
697 pu1Tmp = pOut;
698
699 if (efuseType == EFUSE_WIFI)
700 *pu1Tmp = EFUSE_OOB_PROTECT_BYTES;
701 else
702 *pu1Tmp = EFUSE_PROTECT_BYTES_BANK;
703 }
704 break;
705
706 case TYPE_EFUSE_CONTENT_LEN_BANK:
707 {
708 u16 *pu2Tmp;
709 pu2Tmp = pOut;
710
711 if (efuseType == EFUSE_WIFI)
712 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B;
713 else
714 *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN;
715 }
716 break;
717
718 default:
719 {
720 u8 *pu1Tmp;
721 pu1Tmp = pOut;
722 *pu1Tmp = 0;
723 }
724 break;
725 }
726 }
727
728 #define VOLTAGE_V25 0x03
729 #define LDOE25_SHIFT 28
730
731
732
733
734
735 #define EFUSE_ACCESS_ON_8723 0x69
736 #define EFUSE_ACCESS_OFF_8723 0x00
737 #define REG_EFUSE_ACCESS_8723 0x00CF
738
739
740 static void Hal_BT_EfusePowerSwitch(
741 struct adapter *padapter, u8 bWrite, u8 PwrState
742 )
743 {
744 u8 tempval;
745 if (PwrState) {
746
747
748 tempval = rtw_read8(padapter, 0x6B);
749 tempval |= BIT(6);
750 rtw_write8(padapter, 0x6B, tempval);
751
752
753
754 msleep(1);
755
756
757 tempval = rtw_read8(padapter, 0x6B);
758 tempval &= ~BIT(7);
759 rtw_write8(padapter, 0x6B, tempval);
760 } else {
761
762
763 tempval = rtw_read8(padapter, 0x6B);
764 tempval |= BIT(7);
765 rtw_write8(padapter, 0x6B, tempval);
766
767
768
769
770
771
772 tempval = rtw_read8(padapter, 0x6B);
773 tempval &= ~BIT(6);
774 rtw_write8(padapter, 0x6B, tempval);
775 }
776
777 }
778 static void Hal_EfusePowerSwitch(
779 struct adapter *padapter, u8 bWrite, u8 PwrState
780 )
781 {
782 u8 tempval;
783 u16 tmpV16;
784
785
786 if (PwrState) {
787
788
789 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
790 if (tempval & BIT(0)) {
791 u8 count = 0;
792
793
794 tempval &= ~BIT(0);
795 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL, tempval);
796
797
798 do {
799 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
800 tempval &= 0x3;
801 if (tempval == 0x02)
802 break;
803
804 count++;
805 if (count >= 100)
806 break;
807
808 mdelay(10);
809 } while (1);
810
811 if (count >= 100) {
812 DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86 =%#X\n",
813 FUNC_ADPT_ARG(padapter), tempval);
814 } else {
815 DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86 =%#X\n",
816 FUNC_ADPT_ARG(padapter), tempval);
817 }
818 }
819
820 rtw_write8(padapter, REG_EFUSE_ACCESS_8723, EFUSE_ACCESS_ON_8723);
821
822
823 tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
824 if (!(tmpV16 & FEN_ELDR)) {
825 tmpV16 |= FEN_ELDR;
826 rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
827 }
828
829
830 tmpV16 = rtw_read16(padapter, REG_SYS_CLKR);
831 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
832 tmpV16 |= (LOADER_CLK_EN | ANA8M);
833 rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
834 }
835
836 if (bWrite) {
837
838 tempval = rtw_read8(padapter, EFUSE_TEST+3);
839 tempval &= 0x0F;
840 tempval |= (VOLTAGE_V25 << 4);
841 rtw_write8(padapter, EFUSE_TEST+3, (tempval | 0x80));
842
843
844 }
845 } else {
846 rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
847
848 if (bWrite) {
849
850 tempval = rtw_read8(padapter, EFUSE_TEST+3);
851 rtw_write8(padapter, EFUSE_TEST+3, (tempval & 0x7F));
852 }
853
854 }
855 }
856
857 static void hal_ReadEFuse_WiFi(
858 struct adapter *padapter,
859 u16 _offset,
860 u16 _size_byte,
861 u8 *pbuf,
862 bool bPseudoTest
863 )
864 {
865 #ifdef HAL_EFUSE_MEMORY
866 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
867 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
868 #endif
869 u8 *efuseTbl = NULL;
870 u16 eFuse_Addr = 0;
871 u8 offset, wden;
872 u8 efuseHeader, efuseExtHdr, efuseData;
873 u16 i, total, used;
874 u8 efuse_usage = 0;
875
876
877
878
879
880 if ((_offset+_size_byte) > EFUSE_MAX_MAP_LEN) {
881 DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte);
882 return;
883 }
884
885 efuseTbl = rtw_malloc(EFUSE_MAX_MAP_LEN);
886 if (!efuseTbl) {
887 DBG_8192C("%s: alloc efuseTbl fail!\n", __func__);
888 return;
889 }
890
891 memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN);
892
893
894 #ifdef DEBUG
895 if (0) {
896 for (i = 0; i < 256; i++)
897 efuse_OneByteRead(padapter, i, &efuseTbl[i], false);
898 DBG_871X("Efuse Content:\n");
899 for (i = 0; i < 256; i++) {
900 if (i % 16 == 0)
901 printk("\n");
902 printk("%02X ", efuseTbl[i]);
903 }
904 printk("\n");
905 }
906 #endif
907
908
909
910 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
911
912 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
913 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
914 if (efuseHeader == 0xFF) {
915 DBG_8192C("%s: data end at address =%#x\n", __func__, eFuse_Addr-1);
916 break;
917 }
918
919
920
921 if (EXT_HEADER(efuseHeader)) {
922 offset = GET_HDR_OFFSET_2_0(efuseHeader);
923
924
925 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
926
927 if (ALL_WORDS_DISABLED(efuseExtHdr))
928 continue;
929
930 offset |= ((efuseExtHdr & 0xF0) >> 1);
931 wden = (efuseExtHdr & 0x0F);
932 } else {
933 offset = ((efuseHeader >> 4) & 0x0f);
934 wden = (efuseHeader & 0x0f);
935 }
936
937
938 if (offset < EFUSE_MAX_SECTION_8723B) {
939 u16 addr;
940
941
942
943 addr = offset * PGPKT_DATA_SIZE;
944 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
945
946 if (!(wden & (0x01<<i))) {
947 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
948
949 efuseTbl[addr] = efuseData;
950
951 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
952
953 efuseTbl[addr+1] = efuseData;
954 }
955 addr += 2;
956 }
957 } else {
958 DBG_8192C(KERN_ERR "%s: offset(%d) is illegal!!\n", __func__, offset);
959 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2;
960 }
961 }
962
963
964 for (i = 0; i < _size_byte; i++)
965 pbuf[i] = efuseTbl[_offset+i];
966
967 #ifdef DEBUG
968 if (1) {
969 DBG_871X("Efuse Realmap:\n");
970 for (i = 0; i < _size_byte; i++) {
971 if (i % 16 == 0)
972 printk("\n");
973 printk("%02X ", pbuf[i]);
974 }
975 printk("\n");
976 }
977 #endif
978
979 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
980 used = eFuse_Addr - 1;
981 efuse_usage = (u8)((used*100)/total);
982 if (bPseudoTest) {
983 #ifdef HAL_EFUSE_MEMORY
984 pEfuseHal->fakeEfuseUsedBytes = used;
985 #else
986 fakeEfuseUsedBytes = used;
987 #endif
988 } else {
989 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used);
990 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage);
991 }
992
993 kfree(efuseTbl);
994 }
995
996 static void hal_ReadEFuse_BT(
997 struct adapter *padapter,
998 u16 _offset,
999 u16 _size_byte,
1000 u8 *pbuf,
1001 bool bPseudoTest
1002 )
1003 {
1004 #ifdef HAL_EFUSE_MEMORY
1005 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1006 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1007 #endif
1008 u8 *efuseTbl;
1009 u8 bank;
1010 u16 eFuse_Addr;
1011 u8 efuseHeader, efuseExtHdr, efuseData;
1012 u8 offset, wden;
1013 u16 i, total, used;
1014 u8 efuse_usage;
1015
1016
1017
1018
1019
1020 if ((_offset+_size_byte) > EFUSE_BT_MAP_LEN) {
1021 DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte);
1022 return;
1023 }
1024
1025 efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
1026 if (!efuseTbl) {
1027 DBG_8192C("%s: efuseTbl malloc fail!\n", __func__);
1028 return;
1029 }
1030
1031 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
1032
1033 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest);
1034
1035 for (bank = 1; bank < 3; bank++) {
1036 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) {
1037 DBG_8192C("%s: hal_EfuseSwitchToBank Fail!!\n", __func__);
1038 goto exit;
1039 }
1040
1041 eFuse_Addr = 0;
1042
1043 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
1044 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
1045 if (efuseHeader == 0xFF)
1046 break;
1047 DBG_8192C("%s: efuse[%#X]= 0x%02x (header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseHeader);
1048
1049
1050 if (EXT_HEADER(efuseHeader)) {
1051 offset = GET_HDR_OFFSET_2_0(efuseHeader);
1052 DBG_8192C("%s: extended header offset_2_0 = 0x%X\n", __func__, offset);
1053
1054 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
1055 DBG_8192C("%s: efuse[%#X]= 0x%02x (ext header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseExtHdr);
1056 if (ALL_WORDS_DISABLED(efuseExtHdr))
1057 continue;
1058
1059
1060 offset |= ((efuseExtHdr & 0xF0) >> 1);
1061 wden = (efuseExtHdr & 0x0F);
1062 } else {
1063 offset = ((efuseHeader >> 4) & 0x0f);
1064 wden = (efuseHeader & 0x0f);
1065 }
1066
1067 if (offset < EFUSE_BT_MAX_SECTION) {
1068 u16 addr;
1069
1070
1071 DBG_8192C("%s: Offset =%d Worden =%#X\n", __func__, offset, wden);
1072
1073 addr = offset * PGPKT_DATA_SIZE;
1074 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1075
1076 if (!(wden & (0x01<<i))) {
1077 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1078 DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData);
1079 efuseTbl[addr] = efuseData;
1080
1081 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1082 DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData);
1083 efuseTbl[addr+1] = efuseData;
1084 }
1085 addr += 2;
1086 }
1087 } else {
1088 DBG_8192C("%s: offset(%d) is illegal!!\n", __func__, offset);
1089 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2;
1090 }
1091 }
1092
1093 if ((eFuse_Addr-1) < total) {
1094 DBG_8192C("%s: bank(%d) data end at %#x\n", __func__, bank, eFuse_Addr-1);
1095 break;
1096 }
1097 }
1098
1099
1100 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1101
1102
1103 for (i = 0; i < _size_byte; i++)
1104 pbuf[i] = efuseTbl[_offset+i];
1105
1106
1107
1108
1109 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
1110 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN*(bank-1)) + eFuse_Addr - 1;
1111 DBG_8192C("%s: bank(%d) data end at %#x , used =%d\n", __func__, bank, eFuse_Addr-1, used);
1112 efuse_usage = (u8)((used*100)/total);
1113 if (bPseudoTest) {
1114 #ifdef HAL_EFUSE_MEMORY
1115 pEfuseHal->fakeBTEfuseUsedBytes = used;
1116 #else
1117 fakeBTEfuseUsedBytes = used;
1118 #endif
1119 } else {
1120 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used);
1121 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage);
1122 }
1123
1124 exit:
1125 kfree(efuseTbl);
1126 }
1127
1128 static void Hal_ReadEFuse(
1129 struct adapter *padapter,
1130 u8 efuseType,
1131 u16 _offset,
1132 u16 _size_byte,
1133 u8 *pbuf,
1134 bool bPseudoTest
1135 )
1136 {
1137 if (efuseType == EFUSE_WIFI)
1138 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest);
1139 else
1140 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest);
1141 }
1142
1143 static u16 hal_EfuseGetCurrentSize_WiFi(
1144 struct adapter *padapter, bool bPseudoTest
1145 )
1146 {
1147 #ifdef HAL_EFUSE_MEMORY
1148 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1149 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1150 #endif
1151 u16 efuse_addr = 0;
1152 u16 start_addr = 0;
1153 u8 hoffset = 0, hworden = 0;
1154 u8 efuse_data, word_cnts = 0;
1155 u32 count = 0;
1156
1157
1158 if (bPseudoTest) {
1159 #ifdef HAL_EFUSE_MEMORY
1160 efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes;
1161 #else
1162 efuse_addr = (u16)fakeEfuseUsedBytes;
1163 #endif
1164 } else
1165 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1166
1167 start_addr = efuse_addr;
1168 DBG_8192C("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr);
1169
1170
1171 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1172
1173 count = 0;
1174 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1175 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false) {
1176 DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr = 0x%X !!\n", __func__, efuse_addr);
1177 goto error;
1178 }
1179
1180 if (efuse_data == 0xFF)
1181 break;
1182
1183 if ((start_addr != 0) && (efuse_addr == start_addr)) {
1184 count++;
1185 DBG_8192C(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X = 0x%02X not 0xFF!!(%d times)\n",
1186 FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count);
1187
1188 efuse_data = 0xFF;
1189 if (count < 4) {
1190
1191
1192 if (count > 2) {
1193
1194 efuse_addr = 0;
1195 start_addr = 0;
1196 }
1197
1198 continue;
1199 }
1200
1201 goto error;
1202 }
1203
1204 if (EXT_HEADER(efuse_data)) {
1205 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
1206 efuse_addr++;
1207 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1208 if (ALL_WORDS_DISABLED(efuse_data))
1209 continue;
1210
1211 hoffset |= ((efuse_data & 0xF0) >> 1);
1212 hworden = efuse_data & 0x0F;
1213 } else {
1214 hoffset = (efuse_data>>4) & 0x0F;
1215 hworden = efuse_data & 0x0F;
1216 }
1217
1218 word_cnts = Efuse_CalculateWordCnts(hworden);
1219 efuse_addr += (word_cnts*2)+1;
1220 }
1221
1222 if (bPseudoTest) {
1223 #ifdef HAL_EFUSE_MEMORY
1224 pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
1225 #else
1226 fakeEfuseUsedBytes = efuse_addr;
1227 #endif
1228 } else
1229 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1230
1231 goto exit;
1232
1233 error:
1234
1235 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest);
1236
1237 exit:
1238 DBG_8192C("%s: CurrentSize =%d\n", __func__, efuse_addr);
1239
1240 return efuse_addr;
1241 }
1242
1243 static u16 hal_EfuseGetCurrentSize_BT(struct adapter *padapter, u8 bPseudoTest)
1244 {
1245 #ifdef HAL_EFUSE_MEMORY
1246 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1247 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1248 #endif
1249 u16 btusedbytes;
1250 u16 efuse_addr;
1251 u8 bank, startBank;
1252 u8 hoffset = 0, hworden = 0;
1253 u8 efuse_data, word_cnts = 0;
1254 u16 retU2 = 0;
1255
1256 if (bPseudoTest) {
1257 #ifdef HAL_EFUSE_MEMORY
1258 btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes;
1259 #else
1260 btusedbytes = fakeBTEfuseUsedBytes;
1261 #endif
1262 } else
1263 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes);
1264
1265 efuse_addr = (u16)((btusedbytes%EFUSE_BT_REAL_BANK_CONTENT_LEN));
1266 startBank = (u8)(1+(btusedbytes/EFUSE_BT_REAL_BANK_CONTENT_LEN));
1267
1268 DBG_8192C("%s: start from bank =%d addr = 0x%X\n", __func__, startBank, efuse_addr);
1269
1270 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest);
1271
1272 for (bank = startBank; bank < 3; bank++) {
1273 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) {
1274 DBG_8192C(KERN_ERR "%s: switch bank(%d) Fail!!\n", __func__, bank);
1275
1276 break;
1277 }
1278
1279
1280 if (bank != startBank)
1281 efuse_addr = 0;
1282 #if 1
1283
1284 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1285 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false) {
1286 DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr = 0x%X !!\n", __func__, efuse_addr);
1287
1288 break;
1289 }
1290 DBG_8192C("%s: efuse_OneByteRead ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank);
1291
1292 if (efuse_data == 0xFF)
1293 break;
1294
1295 if (EXT_HEADER(efuse_data)) {
1296 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
1297 efuse_addr++;
1298 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1299 DBG_8192C("%s: efuse_OneByteRead EXT_HEADER ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank);
1300
1301 if (ALL_WORDS_DISABLED(efuse_data)) {
1302 efuse_addr++;
1303 continue;
1304 }
1305
1306
1307 hoffset |= ((efuse_data & 0xF0) >> 1);
1308 hworden = efuse_data & 0x0F;
1309 } else {
1310 hoffset = (efuse_data>>4) & 0x0F;
1311 hworden = efuse_data & 0x0F;
1312 }
1313
1314 DBG_8192C(FUNC_ADPT_FMT": Offset =%d Worden =%#X\n",
1315 FUNC_ADPT_ARG(padapter), hoffset, hworden);
1316
1317 word_cnts = Efuse_CalculateWordCnts(hworden);
1318
1319 efuse_addr += (word_cnts*2)+1;
1320 }
1321 #else
1322 while (
1323 bContinual &&
1324 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) &&
1325 AVAILABLE_EFUSE_ADDR(efuse_addr)
1326 ) {
1327 if (efuse_data != 0xFF) {
1328 if ((efuse_data&0x1F) == 0x0F) {
1329 hoffset = efuse_data;
1330 efuse_addr++;
1331 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1332 if ((efuse_data & 0x0F) == 0x0F) {
1333 efuse_addr++;
1334 continue;
1335 } else {
1336 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1337 hworden = efuse_data & 0x0F;
1338 }
1339 } else {
1340 hoffset = (efuse_data>>4) & 0x0F;
1341 hworden = efuse_data & 0x0F;
1342 }
1343 word_cnts = Efuse_CalculateWordCnts(hworden);
1344
1345 efuse_addr = efuse_addr + (word_cnts*2)+1;
1346 } else
1347 bContinual = false;
1348 }
1349 #endif
1350
1351
1352
1353 if (efuse_addr < retU2)
1354 break;
1355 }
1356
1357 retU2 = ((bank-1)*EFUSE_BT_REAL_BANK_CONTENT_LEN)+efuse_addr;
1358 if (bPseudoTest) {
1359 pEfuseHal->fakeBTEfuseUsedBytes = retU2;
1360
1361 } else {
1362 pEfuseHal->BTEfuseUsedBytes = retU2;
1363
1364 }
1365
1366 DBG_8192C("%s: CurrentSize =%d\n", __func__, retU2);
1367 return retU2;
1368 }
1369
1370 static u16 Hal_EfuseGetCurrentSize(
1371 struct adapter *padapter, u8 efuseType, bool bPseudoTest
1372 )
1373 {
1374 u16 ret = 0;
1375
1376 if (efuseType == EFUSE_WIFI)
1377 ret = hal_EfuseGetCurrentSize_WiFi(padapter, bPseudoTest);
1378 else
1379 ret = hal_EfuseGetCurrentSize_BT(padapter, bPseudoTest);
1380
1381 return ret;
1382 }
1383
1384 static u8 Hal_EfuseWordEnableDataWrite(
1385 struct adapter *padapter,
1386 u16 efuse_addr,
1387 u8 word_en,
1388 u8 *data,
1389 bool bPseudoTest
1390 )
1391 {
1392 u16 tmpaddr = 0;
1393 u16 start_addr = efuse_addr;
1394 u8 badworden = 0x0F;
1395 u8 tmpdata[PGPKT_DATA_SIZE];
1396
1397
1398
1399 memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
1400
1401 if (!(word_en & BIT(0))) {
1402 tmpaddr = start_addr;
1403 efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest);
1404 efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest);
1405
1406 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest);
1407 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[1], bPseudoTest);
1408 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1])) {
1409 badworden &= (~BIT(0));
1410 }
1411 }
1412 if (!(word_en & BIT(1))) {
1413 tmpaddr = start_addr;
1414 efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest);
1415 efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest);
1416
1417 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest);
1418 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[3], bPseudoTest);
1419 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3])) {
1420 badworden &= (~BIT(1));
1421 }
1422 }
1423
1424 if (!(word_en & BIT(2))) {
1425 tmpaddr = start_addr;
1426 efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest);
1427 efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest);
1428
1429 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest);
1430 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[5], bPseudoTest);
1431 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5])) {
1432 badworden &= (~BIT(2));
1433 }
1434 }
1435
1436 if (!(word_en & BIT(3))) {
1437 tmpaddr = start_addr;
1438 efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest);
1439 efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest);
1440
1441 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest);
1442 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[7], bPseudoTest);
1443 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7])) {
1444 badworden &= (~BIT(3));
1445 }
1446 }
1447
1448 return badworden;
1449 }
1450
1451 static s32 Hal_EfusePgPacketRead(
1452 struct adapter *padapter,
1453 u8 offset,
1454 u8 *data,
1455 bool bPseudoTest
1456 )
1457 {
1458 u8 efuse_data, word_cnts = 0;
1459 u16 efuse_addr = 0;
1460 u8 hoffset = 0, hworden = 0;
1461 u8 i;
1462 u8 max_section = 0;
1463 s32 ret;
1464
1465
1466 if (!data)
1467 return false;
1468
1469 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest);
1470 if (offset > max_section) {
1471 DBG_8192C("%s: Packet offset(%d) is illegal(>%d)!\n", __func__, offset, max_section);
1472 return false;
1473 }
1474
1475 memset(data, 0xFF, PGPKT_DATA_SIZE);
1476 ret = true;
1477
1478
1479
1480
1481
1482
1483 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1484 if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == false) {
1485 ret = false;
1486 break;
1487 }
1488
1489 if (efuse_data == 0xFF)
1490 break;
1491
1492 if (EXT_HEADER(efuse_data)) {
1493 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
1494 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
1495 if (ALL_WORDS_DISABLED(efuse_data)) {
1496 DBG_8192C("%s: Error!! All words disabled!\n", __func__);
1497 continue;
1498 }
1499
1500 hoffset |= ((efuse_data & 0xF0) >> 1);
1501 hworden = efuse_data & 0x0F;
1502 } else {
1503 hoffset = (efuse_data>>4) & 0x0F;
1504 hworden = efuse_data & 0x0F;
1505 }
1506
1507 if (hoffset == offset) {
1508 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1509
1510 if (!(hworden & (0x01<<i))) {
1511 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
1512
1513 data[i*2] = efuse_data;
1514
1515 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
1516
1517 data[(i*2)+1] = efuse_data;
1518 }
1519 }
1520 } else {
1521 word_cnts = Efuse_CalculateWordCnts(hworden);
1522 efuse_addr += word_cnts*2;
1523 }
1524 }
1525
1526 return ret;
1527 }
1528
1529 static u8 hal_EfusePgCheckAvailableAddr(
1530 struct adapter *padapter, u8 efuseType, u8 bPseudoTest
1531 )
1532 {
1533 u16 max_available = 0;
1534 u16 current_size;
1535
1536
1537 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest);
1538
1539
1540 current_size = Efuse_GetCurrentSize(padapter, efuseType, bPseudoTest);
1541 if (current_size >= max_available) {
1542 DBG_8192C("%s: Error!! current_size(%d)>max_available(%d)\n", __func__, current_size, max_available);
1543 return false;
1544 }
1545 return true;
1546 }
1547
1548 static void hal_EfuseConstructPGPkt(
1549 u8 offset,
1550 u8 word_en,
1551 u8 *pData,
1552 PPGPKT_STRUCT pTargetPkt
1553 )
1554 {
1555 memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
1556 pTargetPkt->offset = offset;
1557 pTargetPkt->word_en = word_en;
1558 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
1559 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
1560 }
1561
1562 static u8 hal_EfusePartialWriteCheck(
1563 struct adapter *padapter,
1564 u8 efuseType,
1565 u16 *pAddr,
1566 PPGPKT_STRUCT pTargetPkt,
1567 u8 bPseudoTest
1568 )
1569 {
1570 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1571 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1572 u8 bRet = false;
1573 u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0;
1574 u8 efuse_data = 0;
1575
1576 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest);
1577 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest);
1578
1579 if (efuseType == EFUSE_WIFI) {
1580 if (bPseudoTest) {
1581 #ifdef HAL_EFUSE_MEMORY
1582 startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes;
1583 #else
1584 startAddr = (u16)fakeEfuseUsedBytes;
1585 #endif
1586 } else
1587 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
1588 } else {
1589 if (bPseudoTest) {
1590 #ifdef HAL_EFUSE_MEMORY
1591 startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes;
1592 #else
1593 startAddr = (u16)fakeBTEfuseUsedBytes;
1594 #endif
1595 } else
1596 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr);
1597 }
1598 startAddr %= efuse_max;
1599 DBG_8192C("%s: startAddr =%#X\n", __func__, startAddr);
1600
1601 while (1) {
1602 if (startAddr >= efuse_max_available_len) {
1603 bRet = false;
1604 DBG_8192C("%s: startAddr(%d) >= efuse_max_available_len(%d)\n", __func__, startAddr, efuse_max_available_len);
1605 break;
1606 }
1607
1608 if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
1609 #if 1
1610 bRet = false;
1611 DBG_8192C("%s: Something Wrong! last bytes(%#X = 0x%02X) is not 0xFF\n",
1612 __func__, startAddr, efuse_data);
1613 break;
1614 #else
1615 if (EXT_HEADER(efuse_data)) {
1616 cur_header = efuse_data;
1617 startAddr++;
1618 efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest);
1619 if (ALL_WORDS_DISABLED(efuse_data)) {
1620 DBG_8192C("%s: Error condition, all words disabled!", __func__);
1621 bRet = false;
1622 break;
1623 } else {
1624 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1625 curPkt.word_en = efuse_data & 0x0F;
1626 }
1627 } else {
1628 cur_header = efuse_data;
1629 curPkt.offset = (cur_header>>4) & 0x0F;
1630 curPkt.word_en = cur_header & 0x0F;
1631 }
1632
1633 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
1634
1635
1636 if (
1637 (curPkt.offset == pTargetPkt->offset) &&
1638 (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr+1, bPseudoTest) == false) &&
1639 wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == true
1640 ) {
1641 DBG_8192C("%s: Need to partial write data by the previous wrote header\n", __func__);
1642
1643 badworden = Efuse_WordEnableDataWrite(padapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest);
1644 if (badworden != 0x0F) {
1645 u32 PgWriteSuccess = 0;
1646
1647 if (efuseType == EFUSE_WIFI)
1648 PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
1649 else
1650 PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
1651
1652 if (!PgWriteSuccess) {
1653 bRet = false;
1654 break;
1655 }
1656 }
1657
1658 for (i = 0; i < 4; i++) {
1659 if ((matched_wden & (0x1<<i)) == 0) {
1660 pTargetPkt->word_en |= (0x1<<i);
1661 }
1662 }
1663 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
1664 }
1665
1666 startAddr = startAddr + (curPkt.word_cnts*2) + 1;
1667 #endif
1668 } else {
1669
1670 *pAddr = startAddr;
1671
1672 bRet = true;
1673 break;
1674 }
1675 }
1676
1677 return bRet;
1678 }
1679
1680 static u8 hal_EfusePgPacketWrite1ByteHeader(
1681 struct adapter *padapter,
1682 u8 efuseType,
1683 u16 *pAddr,
1684 PPGPKT_STRUCT pTargetPkt,
1685 u8 bPseudoTest
1686 )
1687 {
1688 u8 pg_header = 0, tmp_header = 0;
1689 u16 efuse_addr = *pAddr;
1690 u8 repeatcnt = 0;
1691
1692
1693
1694 pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
1695
1696 do {
1697 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
1698 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
1699 if (tmp_header != 0xFF)
1700 break;
1701 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
1702 DBG_8192C("%s: Repeat over limit for pg_header!!\n", __func__);
1703 return false;
1704 }
1705 } while (1);
1706
1707 if (tmp_header != pg_header) {
1708 DBG_8192C(KERN_ERR "%s: PG Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header);
1709 return false;
1710 }
1711
1712 *pAddr = efuse_addr;
1713
1714 return true;
1715 }
1716
1717 static u8 hal_EfusePgPacketWrite2ByteHeader(
1718 struct adapter *padapter,
1719 u8 efuseType,
1720 u16 *pAddr,
1721 PPGPKT_STRUCT pTargetPkt,
1722 u8 bPseudoTest
1723 )
1724 {
1725 u16 efuse_addr, efuse_max_available_len = 0;
1726 u8 pg_header = 0, tmp_header = 0;
1727 u8 repeatcnt = 0;
1728
1729
1730
1731 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest);
1732
1733 efuse_addr = *pAddr;
1734 if (efuse_addr >= efuse_max_available_len) {
1735 DBG_8192C("%s: addr(%d) over available (%d)!!\n", __func__,
1736 efuse_addr, efuse_max_available_len);
1737 return false;
1738 }
1739
1740 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
1741
1742
1743 do {
1744 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
1745 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
1746 if (tmp_header != 0xFF)
1747 break;
1748 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
1749 DBG_8192C("%s: Repeat over limit for pg_header!!\n", __func__);
1750 return false;
1751 }
1752 } while (1);
1753
1754 if (tmp_header != pg_header) {
1755 DBG_8192C(KERN_ERR "%s: PG Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header);
1756 return false;
1757 }
1758
1759
1760 efuse_addr++;
1761 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
1762
1763 do {
1764 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
1765 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
1766 if (tmp_header != 0xFF)
1767 break;
1768 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
1769 DBG_8192C("%s: Repeat over limit for ext_header!!\n", __func__);
1770 return false;
1771 }
1772 } while (1);
1773
1774 if (tmp_header != pg_header) {
1775 DBG_8192C(KERN_ERR "%s: PG EXT Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header);
1776 return false;
1777 }
1778
1779 *pAddr = efuse_addr;
1780
1781 return true;
1782 }
1783
1784 static u8 hal_EfusePgPacketWriteHeader(
1785 struct adapter *padapter,
1786 u8 efuseType,
1787 u16 *pAddr,
1788 PPGPKT_STRUCT pTargetPkt,
1789 u8 bPseudoTest
1790 )
1791 {
1792 u8 bRet = false;
1793
1794 if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
1795 bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
1796 else
1797 bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
1798
1799 return bRet;
1800 }
1801
1802 static u8 hal_EfusePgPacketWriteData(
1803 struct adapter *padapter,
1804 u8 efuseType,
1805 u16 *pAddr,
1806 PPGPKT_STRUCT pTargetPkt,
1807 u8 bPseudoTest
1808 )
1809 {
1810 u16 efuse_addr;
1811 u8 badworden;
1812
1813
1814 efuse_addr = *pAddr;
1815 badworden = Efuse_WordEnableDataWrite(padapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
1816 if (badworden != 0x0F) {
1817 DBG_8192C("%s: Fail!!\n", __func__);
1818 return false;
1819 }
1820
1821
1822 return true;
1823 }
1824
1825 static s32 Hal_EfusePgPacketWrite(
1826 struct adapter *padapter,
1827 u8 offset,
1828 u8 word_en,
1829 u8 *pData,
1830 bool bPseudoTest
1831 )
1832 {
1833 PGPKT_STRUCT targetPkt;
1834 u16 startAddr = 0;
1835 u8 efuseType = EFUSE_WIFI;
1836
1837 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest))
1838 return false;
1839
1840 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
1841
1842 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1843 return false;
1844
1845 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1846 return false;
1847
1848 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1849 return false;
1850
1851 return true;
1852 }
1853
1854 static bool Hal_EfusePgPacketWrite_BT(
1855 struct adapter *padapter,
1856 u8 offset,
1857 u8 word_en,
1858 u8 *pData,
1859 bool bPseudoTest
1860 )
1861 {
1862 PGPKT_STRUCT targetPkt;
1863 u16 startAddr = 0;
1864 u8 efuseType = EFUSE_BT;
1865
1866 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest))
1867 return false;
1868
1869 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
1870
1871 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1872 return false;
1873
1874 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1875 return false;
1876
1877 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1878 return false;
1879
1880 return true;
1881 }
1882
1883 static HAL_VERSION ReadChipVersion8723B(struct adapter *padapter)
1884 {
1885 u32 value32;
1886 HAL_VERSION ChipVersion;
1887 struct hal_com_data *pHalData;
1888
1889
1890 pHalData = GET_HAL_DATA(padapter);
1891
1892 value32 = rtw_read32(padapter, REG_SYS_CFG);
1893 ChipVersion.ICType = CHIP_8723B;
1894 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
1895 ChipVersion.RFType = RF_TYPE_1T1R;
1896 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
1897 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT;
1898
1899
1900 pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
1901
1902 value32 = rtw_read32(padapter, REG_GPIO_OUTSTS);
1903 ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20);
1904
1905
1906 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
1907 value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
1908 pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
1909 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
1910 pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
1911 pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
1912 #if 1
1913 dump_chip_info(ChipVersion);
1914 #endif
1915 pHalData->VersionID = ChipVersion;
1916 if (IS_1T2R(ChipVersion))
1917 pHalData->rf_type = RF_1T2R;
1918 else if (IS_2T2R(ChipVersion))
1919 pHalData->rf_type = RF_2T2R;
1920 else
1921 pHalData->rf_type = RF_1T1R;
1922
1923 MSG_8192C("RF_Type is %x!!\n", pHalData->rf_type);
1924
1925 return ChipVersion;
1926 }
1927
1928 static void rtl8723b_read_chip_version(struct adapter *padapter)
1929 {
1930 ReadChipVersion8723B(padapter);
1931 }
1932
1933 void rtl8723b_InitBeaconParameters(struct adapter *padapter)
1934 {
1935 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1936 u16 val16;
1937 u8 val8;
1938
1939
1940 val8 = DIS_TSF_UDT;
1941 val16 = val8 | (val8 << 8);
1942
1943
1944 val16 |= EN_BCN_FUNCTION;
1945
1946 rtw_write16(padapter, REG_BCN_CTRL, val16);
1947
1948
1949 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);
1950
1951
1952 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
1953 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8723B);
1954 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8723B);
1955
1956
1957
1958 rtw_write16(padapter, REG_BCNTCFG, 0x660F);
1959
1960 pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL);
1961 pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE);
1962 pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
1963 pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2);
1964 pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1);
1965 }
1966
1967 void _InitBurstPktLen_8723BS(struct adapter *Adapter)
1968 {
1969 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1970
1971 rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7)|BIT(7));
1972 rtw_write8(Adapter, REG_RX_PKT_LIMIT_8723B, 0x18);
1973 rtw_write8(Adapter, REG_MAX_AGGR_NUM_8723B, 0x1F);
1974 rtw_write8(Adapter, REG_PIFS_8723B, 0x00);
1975 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8723B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7)));
1976 if (pHalData->AMPDUBurstMode)
1977 rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8723B, 0x5F);
1978 rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8723B, 0x70);
1979
1980
1981 rtw_write32(Adapter, REG_ARFR0_8723B, 0x00000010);
1982 if (IS_NORMAL_CHIP(pHalData->VersionID))
1983 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0xfffff000);
1984 else
1985 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0x3e0ff000);
1986
1987
1988 rtw_write32(Adapter, REG_ARFR1_8723B, 0x00000010);
1989 rtw_write32(Adapter, REG_ARFR1_8723B+4, 0x003ff000);
1990 }
1991
1992 static void ResumeTxBeacon(struct adapter *padapter)
1993 {
1994 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1995
1996
1997
1998
1999
2000 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));
2001
2002 pHalData->RegFwHwTxQCtrl |= BIT(6);
2003 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
2004 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff);
2005 pHalData->RegReg542 |= BIT(0);
2006 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
2007 }
2008
2009 static void StopTxBeacon(struct adapter *padapter)
2010 {
2011 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2012
2013
2014
2015
2016
2017 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));
2018
2019 pHalData->RegFwHwTxQCtrl &= ~BIT(6);
2020 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
2021 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64);
2022 pHalData->RegReg542 &= ~BIT(0);
2023 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
2024
2025 CheckFwRsvdPageContent(padapter);
2026 }
2027
2028 static void _BeaconFunctionEnable(struct adapter *padapter, u8 Enable, u8 Linked)
2029 {
2030 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
2031 rtw_write8(padapter, REG_RD_CTRL+1, 0x6F);
2032 }
2033
2034 static void rtl8723b_SetBeaconRelatedRegisters(struct adapter *padapter)
2035 {
2036 u8 val8;
2037 u32 value32;
2038 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2039 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2040 u32 bcn_ctrl_reg;
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055 bcn_ctrl_reg = REG_BCN_CTRL;
2056
2057
2058
2059
2060 rtw_write16(padapter, REG_ATIMWND, 2);
2061
2062
2063
2064
2065 rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2066
2067 rtl8723b_InitBeaconParameters(padapter);
2068
2069 rtw_write8(padapter, REG_SLOT, 0x09);
2070
2071
2072
2073
2074 value32 = rtw_read32(padapter, REG_TCR);
2075 value32 &= ~TSFRST;
2076 rtw_write32(padapter, REG_TCR, value32);
2077
2078 value32 |= TSFRST;
2079 rtw_write32(padapter, REG_TCR, value32);
2080
2081
2082 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE) == true) {
2083 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
2084 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
2085 }
2086
2087 _BeaconFunctionEnable(padapter, true, true);
2088
2089 ResumeTxBeacon(padapter);
2090 val8 = rtw_read8(padapter, bcn_ctrl_reg);
2091 val8 |= DIS_BCNQ_SUB;
2092 rtw_write8(padapter, bcn_ctrl_reg, val8);
2093 }
2094
2095 static void rtl8723b_GetHalODMVar(
2096 struct adapter *Adapter,
2097 enum HAL_ODM_VARIABLE eVariable,
2098 void *pValue1,
2099 void *pValue2
2100 )
2101 {
2102 GetHalODMVar(Adapter, eVariable, pValue1, pValue2);
2103 }
2104
2105 static void rtl8723b_SetHalODMVar(
2106 struct adapter *Adapter,
2107 enum HAL_ODM_VARIABLE eVariable,
2108 void *pValue1,
2109 bool bSet
2110 )
2111 {
2112 SetHalODMVar(Adapter, eVariable, pValue1, bSet);
2113 }
2114
2115 static void hal_notch_filter_8723b(struct adapter *adapter, bool enable)
2116 {
2117 if (enable) {
2118 DBG_871X("Enable notch filter\n");
2119 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
2120 } else {
2121 DBG_871X("Disable notch filter\n");
2122 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
2123 }
2124 }
2125
2126 static void UpdateHalRAMask8723B(struct adapter *padapter, u32 mac_id, u8 rssi_level)
2127 {
2128 u32 mask, rate_bitmap;
2129 u8 shortGIrate = false;
2130 struct sta_info *psta;
2131 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2132 struct dm_priv *pdmpriv = &pHalData->dmpriv;
2133 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2134 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2135
2136 DBG_871X("%s(): mac_id =%d rssi_level =%d\n", __func__, mac_id, rssi_level);
2137
2138 if (mac_id >= NUM_STA)
2139 return;
2140
2141 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2142 if (!psta)
2143 return;
2144
2145 shortGIrate = query_ra_short_GI(psta);
2146
2147 mask = psta->ra_mask;
2148
2149 rate_bitmap = 0xffffffff;
2150 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level);
2151 DBG_871X("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2152 __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap);
2153
2154 mask &= rate_bitmap;
2155
2156 rate_bitmap = hal_btcoex_GetRaMask(padapter);
2157 mask &= ~rate_bitmap;
2158
2159 #ifdef CONFIG_CMCC_TEST
2160 if (pmlmeext->cur_wireless_mode & WIRELESS_11G) {
2161 if (mac_id == 0) {
2162 DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask);
2163 mask &= 0xffffff00;
2164 DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask);
2165 }
2166 }
2167 #endif
2168
2169 if (pHalData->fw_ractrl) {
2170 rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, psta->raid, psta->bw_mode, shortGIrate, mask);
2171 }
2172
2173
2174 pdmpriv->INIDATA_RATE[mac_id] = psta->init_rate;
2175 DBG_871X("%s(): mac_id =%d raid = 0x%x bw =%d mask = 0x%x init_rate = 0x%x\n", __func__, mac_id, psta->raid, psta->bw_mode, mask, psta->init_rate);
2176 }
2177
2178
2179 void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc)
2180 {
2181 pHalFunc->free_hal_data = &rtl8723b_free_hal_data;
2182
2183 pHalFunc->dm_init = &rtl8723b_init_dm_priv;
2184
2185 pHalFunc->read_chip_version = &rtl8723b_read_chip_version;
2186
2187 pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8723B;
2188
2189 pHalFunc->set_bwmode_handler = &PHY_SetBWMode8723B;
2190 pHalFunc->set_channel_handler = &PHY_SwChnl8723B;
2191 pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8723B;
2192
2193 pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8723B;
2194 pHalFunc->get_tx_power_level_handler = &PHY_GetTxPowerLevel8723B;
2195
2196 pHalFunc->hal_dm_watchdog = &rtl8723b_HalDmWatchDog;
2197 pHalFunc->hal_dm_watchdog_in_lps = &rtl8723b_HalDmWatchDog_in_LPS;
2198
2199
2200 pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8723b_SetBeaconRelatedRegisters;
2201
2202 pHalFunc->Add_RateATid = &rtl8723b_Add_RateATid;
2203
2204 pHalFunc->run_thread = &rtl8723b_start_thread;
2205 pHalFunc->cancel_thread = &rtl8723b_stop_thread;
2206
2207 pHalFunc->read_bbreg = &PHY_QueryBBReg_8723B;
2208 pHalFunc->write_bbreg = &PHY_SetBBReg_8723B;
2209 pHalFunc->read_rfreg = &PHY_QueryRFReg_8723B;
2210 pHalFunc->write_rfreg = &PHY_SetRFReg_8723B;
2211
2212
2213 pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch;
2214 pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch;
2215 pHalFunc->ReadEFuse = &Hal_ReadEFuse;
2216 pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition;
2217 pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize;
2218 pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead;
2219 pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite;
2220 pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite;
2221 pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT;
2222
2223 pHalFunc->GetHalODMVarHandler = &rtl8723b_GetHalODMVar;
2224 pHalFunc->SetHalODMVarHandler = &rtl8723b_SetHalODMVar;
2225
2226 pHalFunc->xmit_thread_handler = &hal_xmit_handler;
2227 pHalFunc->hal_notch_filter = &hal_notch_filter_8723b;
2228
2229 pHalFunc->c2h_handler = c2h_handler_8723b;
2230 pHalFunc->c2h_id_filter_ccx = c2h_id_filter_ccx_8723b;
2231
2232 pHalFunc->fill_h2c_cmd = &FillH2CCmd8723B;
2233 }
2234
2235 void rtl8723b_InitAntenna_Selection(struct adapter *padapter)
2236 {
2237 struct hal_com_data *pHalData;
2238 u8 val;
2239
2240
2241 pHalData = GET_HAL_DATA(padapter);
2242
2243 val = rtw_read8(padapter, REG_LEDCFG2);
2244
2245 val |= BIT(7);
2246 rtw_write8(padapter, REG_LEDCFG2, val);
2247 }
2248
2249 void rtl8723b_init_default_value(struct adapter *padapter)
2250 {
2251 struct hal_com_data *pHalData;
2252 struct dm_priv *pdmpriv;
2253 u8 i;
2254
2255
2256 pHalData = GET_HAL_DATA(padapter);
2257 pdmpriv = &pHalData->dmpriv;
2258
2259 padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N;
2260
2261
2262 pHalData->fw_ractrl = false;
2263 pHalData->bIQKInitialized = false;
2264 if (!adapter_to_pwrctl(padapter)->bkeepfwalive)
2265 pHalData->LastHMEBoxNum = 0;
2266
2267 pHalData->bIQKInitialized = false;
2268
2269
2270 pdmpriv->TM_Trigger = 0;
2271
2272
2273
2274
2275 pdmpriv->ThermalValue_HP_index = 0;
2276 for (i = 0; i < HP_THERMAL_NUM; i++)
2277 pdmpriv->ThermalValue_HP[i] = 0;
2278
2279
2280 pHalData->EfuseUsedBytes = 0;
2281 pHalData->EfuseUsedPercentage = 0;
2282 #ifdef HAL_EFUSE_MEMORY
2283 pHalData->EfuseHal.fakeEfuseBank = 0;
2284 pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
2285 memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
2286 memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
2287 memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
2288 pHalData->EfuseHal.BTEfuseUsedBytes = 0;
2289 pHalData->EfuseHal.BTEfuseUsedPercentage = 0;
2290 memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE);
2291 memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
2292 memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
2293 pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0;
2294 memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE);
2295 memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
2296 memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
2297 #endif
2298 }
2299
2300 u8 GetEEPROMSize8723B(struct adapter *padapter)
2301 {
2302 u8 size = 0;
2303 u32 cr;
2304
2305 cr = rtw_read16(padapter, REG_9346CR);
2306
2307 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
2308
2309 MSG_8192C("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
2310
2311 return size;
2312 }
2313
2314
2315
2316
2317
2318
2319 s32 rtl8723b_InitLLTTable(struct adapter *padapter)
2320 {
2321 unsigned long start, passing_time;
2322 u32 val32;
2323 s32 ret;
2324
2325
2326 ret = _FAIL;
2327
2328 val32 = rtw_read32(padapter, REG_AUTO_LLT);
2329 val32 |= BIT_AUTO_INIT_LLT;
2330 rtw_write32(padapter, REG_AUTO_LLT, val32);
2331
2332 start = jiffies;
2333
2334 do {
2335 val32 = rtw_read32(padapter, REG_AUTO_LLT);
2336 if (!(val32 & BIT_AUTO_INIT_LLT)) {
2337 ret = _SUCCESS;
2338 break;
2339 }
2340
2341 passing_time = jiffies_to_msecs(jiffies - start);
2342 if (passing_time > 1000) {
2343 DBG_8192C(
2344 "%s: FAIL!! REG_AUTO_LLT(0x%X) =%08x\n",
2345 __func__,
2346 REG_AUTO_LLT,
2347 val32
2348 );
2349 break;
2350 }
2351
2352 msleep(1);
2353 } while (1);
2354
2355 return ret;
2356 }
2357
2358 static bool Hal_GetChnlGroup8723B(u8 Channel, u8 *pGroup)
2359 {
2360 bool bIn24G = true;
2361
2362 if (Channel <= 14) {
2363 bIn24G = true;
2364
2365 if (1 <= Channel && Channel <= 2)
2366 *pGroup = 0;
2367 else if (3 <= Channel && Channel <= 5)
2368 *pGroup = 1;
2369 else if (6 <= Channel && Channel <= 8)
2370 *pGroup = 2;
2371 else if (9 <= Channel && Channel <= 11)
2372 *pGroup = 3;
2373 else if (12 <= Channel && Channel <= 14)
2374 *pGroup = 4;
2375 else {
2376 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8723B in 2.4 G, but Channel %d in Group not found\n", Channel));
2377 }
2378 } else {
2379 bIn24G = false;
2380
2381 if (36 <= Channel && Channel <= 42)
2382 *pGroup = 0;
2383 else if (44 <= Channel && Channel <= 48)
2384 *pGroup = 1;
2385 else if (50 <= Channel && Channel <= 58)
2386 *pGroup = 2;
2387 else if (60 <= Channel && Channel <= 64)
2388 *pGroup = 3;
2389 else if (100 <= Channel && Channel <= 106)
2390 *pGroup = 4;
2391 else if (108 <= Channel && Channel <= 114)
2392 *pGroup = 5;
2393 else if (116 <= Channel && Channel <= 122)
2394 *pGroup = 6;
2395 else if (124 <= Channel && Channel <= 130)
2396 *pGroup = 7;
2397 else if (132 <= Channel && Channel <= 138)
2398 *pGroup = 8;
2399 else if (140 <= Channel && Channel <= 144)
2400 *pGroup = 9;
2401 else if (149 <= Channel && Channel <= 155)
2402 *pGroup = 10;
2403 else if (157 <= Channel && Channel <= 161)
2404 *pGroup = 11;
2405 else if (165 <= Channel && Channel <= 171)
2406 *pGroup = 12;
2407 else if (173 <= Channel && Channel <= 177)
2408 *pGroup = 13;
2409 else {
2410 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8723B in 5G, but Channel %d in Group not found\n", Channel));
2411 }
2412
2413 }
2414 RT_TRACE(
2415 _module_hci_hal_init_c_,
2416 _drv_info_,
2417 (
2418 "<==Hal_GetChnlGroup8723B, (%s) Channel = %d, Group =%d,\n",
2419 bIn24G ? "2.4G" : "5G",
2420 Channel,
2421 *pGroup
2422 )
2423 );
2424 return bIn24G;
2425 }
2426
2427 void Hal_InitPGData(struct adapter *padapter, u8 *PROMContent)
2428 {
2429 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2430
2431 if (!pEEPROM->bautoload_fail_flag) {
2432 if (!pEEPROM->EepromOrEfuse) {
2433
2434 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
2435 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B);
2436 }
2437 } else {
2438 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
2439 if (!pEEPROM->EepromOrEfuse)
2440 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
2441 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B);
2442 }
2443 }
2444
2445 void Hal_EfuseParseIDCode(struct adapter *padapter, u8 *hwinfo)
2446 {
2447 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2448
2449 u16 EEPROMId;
2450
2451
2452
2453 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
2454 if (EEPROMId != RTL_EEPROM_ID) {
2455 DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
2456 pEEPROM->bautoload_fail_flag = true;
2457 } else
2458 pEEPROM->bautoload_fail_flag = false;
2459
2460 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("EEPROM ID = 0x%04x\n", EEPROMId));
2461 }
2462
2463 static void Hal_ReadPowerValueFromPROM_8723B(
2464 struct adapter *Adapter,
2465 struct TxPowerInfo24G *pwrInfo24G,
2466 u8 *PROMContent,
2467 bool AutoLoadFail
2468 )
2469 {
2470 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
2471 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_8723B, group, TxCount = 0;
2472
2473 memset(pwrInfo24G, 0, sizeof(struct TxPowerInfo24G));
2474
2475 if (0xFF == PROMContent[eeAddr+1])
2476 AutoLoadFail = true;
2477
2478 if (AutoLoadFail) {
2479 DBG_871X("%s(): Use Default value!\n", __func__);
2480 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
2481
2482 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
2483 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2484 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2485 }
2486
2487 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2488 if (TxCount == 0) {
2489 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
2490 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
2491 } else {
2492 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2493 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2494 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2495 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2496 }
2497 }
2498 }
2499
2500 return;
2501 }
2502
2503 pHalData->bTXPowerDataReadFromEEPORM = true;
2504
2505 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
2506
2507 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
2508 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
2509 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
2510 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2511 }
2512
2513 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
2514 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
2515 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
2516 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2517 }
2518
2519 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2520 if (TxCount == 0) {
2521 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
2522 if (PROMContent[eeAddr] == 0xFF)
2523 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
2524 else {
2525 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2526 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3)
2527 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
2528 }
2529
2530 if (PROMContent[eeAddr] == 0xFF)
2531 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
2532 else {
2533 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2534 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3)
2535 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
2536 }
2537 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
2538 eeAddr++;
2539 } else {
2540 if (PROMContent[eeAddr] == 0xFF)
2541 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2542 else {
2543 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2544 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3)
2545 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
2546 }
2547
2548 if (PROMContent[eeAddr] == 0xFF)
2549 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2550 else {
2551 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2552 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3)
2553 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
2554 }
2555 eeAddr++;
2556
2557 if (PROMContent[eeAddr] == 0xFF)
2558 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2559 else {
2560 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2561 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3)
2562 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
2563 }
2564
2565 if (PROMContent[eeAddr] == 0xFF)
2566 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2567 else {
2568 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2569 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3)
2570 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
2571 }
2572 eeAddr++;
2573 }
2574 }
2575 }
2576 }
2577
2578
2579 void Hal_EfuseParseTxPowerInfo_8723B(
2580 struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail
2581 )
2582 {
2583 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2584 struct TxPowerInfo24G pwrInfo24G;
2585 u8 rfPath, ch, TxCount = 1;
2586
2587 Hal_ReadPowerValueFromPROM_8723B(padapter, &pwrInfo24G, PROMContent, AutoLoadFail);
2588 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2589 for (ch = 0 ; ch < CHANNEL_MAX_NUMBER; ch++) {
2590 u8 group = 0;
2591
2592 Hal_GetChnlGroup8723B(ch+1, &group);
2593
2594 if (ch == 14-1) {
2595 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][5];
2596 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
2597 } else {
2598 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
2599 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
2600 }
2601 #ifdef DEBUG
2602 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("======= Path %d, ChannelIndex %d, Group %d =======\n", rfPath, ch, group));
2603 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_CCK_Base[rfPath][ch]));
2604 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_BW40_Base[rfPath][ch]));
2605 #endif
2606 }
2607
2608 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2609 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
2610 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
2611 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
2612 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
2613
2614 #ifdef DEBUG
2615 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("--------------------------------------- 2.4G ---------------------------------------\n"));
2616 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CCK_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]));
2617 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("OFDM_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]));
2618 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW20_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]));
2619 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW40_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]));
2620 #endif
2621 }
2622 }
2623
2624
2625 if (!AutoLoadFail) {
2626 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8723B]&0x7);
2627 if (PROMContent[EEPROM_RF_BOARD_OPTION_8723B] == 0xFF)
2628 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7);
2629 } else
2630 pHalData->EEPROMRegulatory = 0;
2631
2632 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory));
2633 }
2634
2635 void Hal_EfuseParseBTCoexistInfo_8723B(
2636 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2637 )
2638 {
2639 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2640 u8 tempval;
2641 u32 tmpu4;
2642
2643 if (!AutoLoadFail) {
2644 tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
2645 if (tmpu4 & BT_FUNC_EN)
2646 pHalData->EEPROMBluetoothCoexist = true;
2647 else
2648 pHalData->EEPROMBluetoothCoexist = false;
2649
2650 pHalData->EEPROMBluetoothType = BT_RTL8723B;
2651
2652 tempval = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2653 if (tempval != 0xFF) {
2654 pHalData->EEPROMBluetoothAntNum = tempval & BIT(0);
2655
2656
2657 pHalData->ant_path = (tempval & BIT(6))?ODM_RF_PATH_B:ODM_RF_PATH_A;
2658 } else {
2659 pHalData->EEPROMBluetoothAntNum = Ant_x1;
2660 if (pHalData->PackageType == PACKAGE_QFN68)
2661 pHalData->ant_path = ODM_RF_PATH_B;
2662 else
2663 pHalData->ant_path = ODM_RF_PATH_A;
2664 }
2665 } else {
2666 pHalData->EEPROMBluetoothCoexist = false;
2667 pHalData->EEPROMBluetoothType = BT_RTL8723B;
2668 pHalData->EEPROMBluetoothAntNum = Ant_x1;
2669 pHalData->ant_path = ODM_RF_PATH_A;
2670 }
2671
2672 if (padapter->registrypriv.ant_num > 0) {
2673 DBG_8192C(
2674 "%s: Apply driver defined antenna number(%d) to replace origin(%d)\n",
2675 __func__,
2676 padapter->registrypriv.ant_num,
2677 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1
2678 );
2679
2680 switch (padapter->registrypriv.ant_num) {
2681 case 1:
2682 pHalData->EEPROMBluetoothAntNum = Ant_x1;
2683 break;
2684 case 2:
2685 pHalData->EEPROMBluetoothAntNum = Ant_x2;
2686 break;
2687 default:
2688 DBG_8192C(
2689 "%s: Discard invalid driver defined antenna number(%d)!\n",
2690 __func__,
2691 padapter->registrypriv.ant_num
2692 );
2693 break;
2694 }
2695 }
2696
2697 hal_btcoex_SetBTCoexist(padapter, pHalData->EEPROMBluetoothCoexist);
2698 hal_btcoex_SetChipType(padapter, pHalData->EEPROMBluetoothType);
2699 hal_btcoex_SetPgAntNum(padapter, pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
2700 if (pHalData->EEPROMBluetoothAntNum == Ant_x1)
2701 hal_btcoex_SetSingleAntPath(padapter, pHalData->ant_path);
2702
2703 DBG_8192C(
2704 "%s: %s BT-coex, ant_num =%d\n",
2705 __func__,
2706 pHalData->EEPROMBluetoothCoexist == true ? "Enable" : "Disable",
2707 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1
2708 );
2709 }
2710
2711 void Hal_EfuseParseEEPROMVer_8723B(
2712 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2713 )
2714 {
2715 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2716
2717
2718 if (!AutoLoadFail)
2719 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723B];
2720 else
2721 pHalData->EEPROMVersion = 1;
2722 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
2723 pHalData->EEPROMVersion));
2724 }
2725
2726
2727
2728 void Hal_EfuseParsePackageType_8723B(
2729 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2730 )
2731 {
2732 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2733 u8 package;
2734 u8 efuseContent;
2735
2736 Efuse_PowerSwitch(padapter, false, true);
2737 efuse_OneByteRead(padapter, 0x1FB, &efuseContent, false);
2738 DBG_871X("%s phy efuse read 0x1FB =%x\n", __func__, efuseContent);
2739 Efuse_PowerSwitch(padapter, false, false);
2740
2741 package = efuseContent & 0x7;
2742 switch (package) {
2743 case 0x4:
2744 pHalData->PackageType = PACKAGE_TFBGA79;
2745 break;
2746 case 0x5:
2747 pHalData->PackageType = PACKAGE_TFBGA90;
2748 break;
2749 case 0x6:
2750 pHalData->PackageType = PACKAGE_QFN68;
2751 break;
2752 case 0x7:
2753 pHalData->PackageType = PACKAGE_TFBGA80;
2754 break;
2755
2756 default:
2757 pHalData->PackageType = PACKAGE_DEFAULT;
2758 break;
2759 }
2760
2761 DBG_871X("PackageType = 0x%X\n", pHalData->PackageType);
2762 }
2763
2764
2765 void Hal_EfuseParseVoltage_8723B(
2766 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2767 )
2768 {
2769 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2770
2771
2772 DBG_871X("%s hwinfo[EEPROM_Voltage_ADDR_8723B] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8723B]);
2773 pEEPROM->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8723B] & 0xf0) >> 4;
2774 DBG_871X("%s pEEPROM->adjuseVoltageVal =%x\n", __func__, pEEPROM->adjuseVoltageVal);
2775 }
2776
2777 void Hal_EfuseParseChnlPlan_8723B(
2778 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2779 )
2780 {
2781 padapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan(
2782 padapter,
2783 hwinfo ? hwinfo[EEPROM_ChannelPlan_8723B] : 0xFF,
2784 padapter->registrypriv.channel_plan,
2785 RT_CHANNEL_DOMAIN_WORLD_NULL,
2786 AutoLoadFail
2787 );
2788
2789 Hal_ChannelPlanToRegulation(padapter, padapter->mlmepriv.ChannelPlan);
2790
2791 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan));
2792 }
2793
2794 void Hal_EfuseParseCustomerID_8723B(
2795 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2796 )
2797 {
2798 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2799
2800
2801 if (!AutoLoadFail)
2802 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723B];
2803 else
2804 pHalData->EEPROMCustomerID = 0;
2805
2806 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID));
2807 }
2808
2809 void Hal_EfuseParseAntennaDiversity_8723B(
2810 struct adapter *padapter,
2811 u8 *hwinfo,
2812 bool AutoLoadFail
2813 )
2814 {
2815 }
2816
2817 void Hal_EfuseParseXtal_8723B(
2818 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2819 )
2820 {
2821 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2822
2823
2824 if (!AutoLoadFail) {
2825 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_8723B];
2826 if (pHalData->CrystalCap == 0xFF)
2827 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B;
2828 } else
2829 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B;
2830
2831 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM CrystalCap: 0x%2x\n", pHalData->CrystalCap));
2832 }
2833
2834
2835 void Hal_EfuseParseThermalMeter_8723B(
2836 struct adapter *padapter, u8 *PROMContent, u8 AutoLoadFail
2837 )
2838 {
2839 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2840
2841
2842
2843
2844
2845 if (!AutoLoadFail)
2846 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_8723B];
2847 else
2848 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B;
2849
2850 if ((pHalData->EEPROMThermalMeter == 0xff) || AutoLoadFail) {
2851 pHalData->bAPKThermalMeterIgnore = true;
2852 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B;
2853 }
2854
2855 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
2856 }
2857
2858
2859 void Hal_ReadRFGainOffset(
2860 struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail
2861 )
2862 {
2863
2864
2865
2866
2867 if (!AutoloadFail) {
2868 Adapter->eeprompriv.EEPROMRFGainOffset = PROMContent[EEPROM_RF_GAIN_OFFSET];
2869 DBG_871X("AutoloadFail =%x,\n", AutoloadFail);
2870 Adapter->eeprompriv.EEPROMRFGainVal = EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL);
2871 DBG_871X("Adapter->eeprompriv.EEPROMRFGainVal =%x\n", Adapter->eeprompriv.EEPROMRFGainVal);
2872 } else {
2873 Adapter->eeprompriv.EEPROMRFGainOffset = 0;
2874 Adapter->eeprompriv.EEPROMRFGainVal = 0xFF;
2875 DBG_871X("else AutoloadFail =%x,\n", AutoloadFail);
2876 }
2877 DBG_871X("EEPRORFGainOffset = 0x%02x\n", Adapter->eeprompriv.EEPROMRFGainOffset);
2878 }
2879
2880 u8 BWMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib)
2881 {
2882 u8 BWSettingOfDesc = 0;
2883 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
2884
2885
2886
2887 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
2888 if (pattrib->bwmode == CHANNEL_WIDTH_80)
2889 BWSettingOfDesc = 2;
2890 else if (pattrib->bwmode == CHANNEL_WIDTH_40)
2891 BWSettingOfDesc = 1;
2892 else
2893 BWSettingOfDesc = 0;
2894 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
2895 if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
2896 BWSettingOfDesc = 1;
2897 else
2898 BWSettingOfDesc = 0;
2899 } else
2900 BWSettingOfDesc = 0;
2901
2902
2903
2904
2905 return BWSettingOfDesc;
2906 }
2907
2908 u8 SCMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib)
2909 {
2910 u8 SCSettingOfDesc = 0;
2911 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
2912
2913
2914
2915 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
2916 if (pattrib->bwmode == CHANNEL_WIDTH_80) {
2917 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
2918 } else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
2919 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
2920 SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
2921 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
2922 SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
2923 else
2924 DBG_871X("SCMapping: Not Correct Primary40MHz Setting\n");
2925 } else {
2926 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
2927 SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
2928 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
2929 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2930 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
2931 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2932 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
2933 SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
2934 else
2935 DBG_871X("SCMapping: Not Correct Primary40MHz Setting\n");
2936 }
2937 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
2938
2939
2940 if (pattrib->bwmode == CHANNEL_WIDTH_40) {
2941 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
2942 } else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
2943 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) {
2944 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2945 } else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) {
2946 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2947 } else {
2948 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
2949 }
2950 }
2951 } else {
2952 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
2953 }
2954
2955 return SCSettingOfDesc;
2956 }
2957
2958 static void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc)
2959 {
2960 u16 *usPtr = (u16 *)ptxdesc;
2961 u32 count;
2962 u32 index;
2963 u16 checksum = 0;
2964
2965
2966
2967 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
2968
2969
2970
2971
2972 count = 16;
2973
2974 for (index = 0; index < count; index++) {
2975 checksum |= le16_to_cpu(*(__le16 *)(usPtr + index));
2976 }
2977
2978 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
2979 }
2980
2981 static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib)
2982 {
2983 u8 sectype = 0;
2984 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
2985 switch (pattrib->encrypt) {
2986
2987 case _WEP40_:
2988 case _WEP104_:
2989 case _TKIP_:
2990 case _TKIP_WTMIC_:
2991 sectype = 1;
2992 break;
2993
2994 case _AES_:
2995 sectype = 3;
2996 break;
2997
2998 case _NO_PRIVACY_:
2999 default:
3000 break;
3001 }
3002 }
3003 return sectype;
3004 }
3005
3006 static void fill_txdesc_vcs_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, PTXDESC_8723B ptxdesc)
3007 {
3008
3009
3010 if (pattrib->vcs_mode) {
3011 switch (pattrib->vcs_mode) {
3012 case RTS_CTS:
3013 ptxdesc->rtsen = 1;
3014
3015 ptxdesc->hw_rts_en = 1;
3016 break;
3017
3018 case CTS_TO_SELF:
3019 ptxdesc->cts2self = 1;
3020 break;
3021
3022 case NONE_VCS:
3023 default:
3024 break;
3025 }
3026
3027 ptxdesc->rtsrate = 8;
3028 ptxdesc->rts_ratefb_lmt = 0xF;
3029
3030 if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT)
3031 ptxdesc->rts_short = 1;
3032
3033
3034 if (pattrib->ht_en)
3035 ptxdesc->rts_sc = SCMapping_8723B(padapter, pattrib);
3036 }
3037 }
3038
3039 static void fill_txdesc_phy_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, PTXDESC_8723B ptxdesc)
3040 {
3041
3042
3043 if (pattrib->ht_en) {
3044 ptxdesc->data_bw = BWMapping_8723B(padapter, pattrib);
3045
3046 ptxdesc->data_sc = SCMapping_8723B(padapter, pattrib);
3047 }
3048 }
3049
3050 static void rtl8723b_fill_default_txdesc(
3051 struct xmit_frame *pxmitframe, u8 *pbuf
3052 )
3053 {
3054 struct adapter *padapter;
3055 struct hal_com_data *pHalData;
3056 struct dm_priv *pdmpriv;
3057 struct mlme_ext_priv *pmlmeext;
3058 struct mlme_ext_info *pmlmeinfo;
3059 struct pkt_attrib *pattrib;
3060 PTXDESC_8723B ptxdesc;
3061 s32 bmcst;
3062
3063 memset(pbuf, 0, TXDESC_SIZE);
3064
3065 padapter = pxmitframe->padapter;
3066 pHalData = GET_HAL_DATA(padapter);
3067 pdmpriv = &pHalData->dmpriv;
3068 pmlmeext = &padapter->mlmeextpriv;
3069 pmlmeinfo = &(pmlmeext->mlmext_info);
3070
3071 pattrib = &pxmitframe->attrib;
3072 bmcst = IS_MCAST(pattrib->ra);
3073
3074 ptxdesc = (PTXDESC_8723B)pbuf;
3075
3076 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
3077 u8 drv_userate = 0;
3078
3079 ptxdesc->macid = pattrib->mac_id;
3080 ptxdesc->rate_id = pattrib->raid;
3081 ptxdesc->qsel = pattrib->qsel;
3082 ptxdesc->seq = pattrib->seqnum;
3083
3084 ptxdesc->sectype = fill_txdesc_sectype(pattrib);
3085 fill_txdesc_vcs_8723b(padapter, pattrib, ptxdesc);
3086
3087 if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1)
3088 drv_userate = 1;
3089
3090 if (
3091 (pattrib->ether_type != 0x888e) &&
3092 (pattrib->ether_type != 0x0806) &&
3093 (pattrib->ether_type != 0x88B4) &&
3094 (pattrib->dhcp_pkt != 1) &&
3095 (drv_userate != 1)
3096 #ifdef CONFIG_AUTO_AP_MODE
3097 && (!pattrib->pctrl)
3098 #endif
3099 ) {
3100
3101
3102 if (pattrib->ampdu_en) {
3103 ptxdesc->agg_en = 1;
3104 ptxdesc->max_agg_num = 0x1f;
3105 ptxdesc->ampdu_density = pattrib->ampdu_spacing;
3106 } else
3107 ptxdesc->bk = 1;
3108
3109 fill_txdesc_phy_8723b(padapter, pattrib, ptxdesc);
3110
3111 ptxdesc->data_ratefb_lmt = 0x1F;
3112
3113 if (!pHalData->fw_ractrl) {
3114 ptxdesc->userate = 1;
3115
3116 if (pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & BIT(7))
3117 ptxdesc->data_short = 1;
3118
3119 ptxdesc->datarate = pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & 0x7F;
3120 }
3121
3122 if (padapter->fix_rate != 0xFF) {
3123 ptxdesc->userate = 1;
3124 if (padapter->fix_rate & BIT(7))
3125 ptxdesc->data_short = 1;
3126
3127 ptxdesc->datarate = (padapter->fix_rate & 0x7F);
3128 ptxdesc->disdatafb = 1;
3129 }
3130
3131 if (pattrib->ldpc)
3132 ptxdesc->data_ldpc = 1;
3133 if (pattrib->stbc)
3134 ptxdesc->data_stbc = 1;
3135
3136 #ifdef CONFIG_CMCC_TEST
3137 ptxdesc->data_short = 1;
3138 #endif
3139 } else {
3140
3141
3142
3143
3144 ptxdesc->bk = 1;
3145 ptxdesc->userate = 1;
3146 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
3147 ptxdesc->data_short = 1;
3148 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
3149 DBG_871X("YJ: %s(): ARP Data: userate =%d, datarate = 0x%x\n", __func__, ptxdesc->userate, ptxdesc->datarate);
3150 }
3151
3152 ptxdesc->usb_txagg_num = pxmitframe->agg_num;
3153 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
3154
3155
3156 ptxdesc->macid = pattrib->mac_id;
3157 ptxdesc->qsel = pattrib->qsel;
3158 ptxdesc->rate_id = pattrib->raid;
3159 ptxdesc->seq = pattrib->seqnum;
3160 ptxdesc->userate = 1;
3161
3162 ptxdesc->mbssid = pattrib->mbssid & 0xF;
3163
3164 ptxdesc->rty_lmt_en = 1;
3165 if (pattrib->retry_ctrl) {
3166 ptxdesc->data_rt_lmt = 6;
3167 } else {
3168 ptxdesc->data_rt_lmt = 12;
3169 }
3170
3171 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
3172
3173
3174 if (pxmitframe->ack_report) {
3175 #ifdef DBG_CCX
3176 DBG_8192C("%s set spe_rpt\n", __func__);
3177 #endif
3178 ptxdesc->spe_rpt = 1;
3179 ptxdesc->sw_define = (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no);
3180 }
3181 } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
3182 RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: TXAGG_FRAMETAG\n", __func__));
3183 } else {
3184 RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: frame_tag = 0x%x\n", __func__, pxmitframe->frame_tag));
3185
3186 ptxdesc->macid = pattrib->mac_id;
3187 ptxdesc->rate_id = pattrib->raid;
3188 ptxdesc->qsel = pattrib->qsel;
3189 ptxdesc->seq = pattrib->seqnum;
3190 ptxdesc->userate = 1;
3191 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
3192 }
3193
3194 ptxdesc->pktlen = pattrib->last_txcmdsz;
3195 ptxdesc->offset = TXDESC_SIZE + OFFSET_SZ;
3196
3197 if (bmcst)
3198 ptxdesc->bmc = 1;
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208 if (!pattrib->qos_en)
3209 ptxdesc->en_hwseq = 1;
3210 }
3211
3212
3213
3214
3215
3216
3217
3218
3219 void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
3220 {
3221 struct tx_desc *pdesc;
3222
3223 rtl8723b_fill_default_txdesc(pxmitframe, pbuf);
3224
3225 pdesc = (struct tx_desc *)pbuf;
3226 pdesc->txdw0 = pdesc->txdw0;
3227 pdesc->txdw1 = pdesc->txdw1;
3228 pdesc->txdw2 = pdesc->txdw2;
3229 pdesc->txdw3 = pdesc->txdw3;
3230 pdesc->txdw4 = pdesc->txdw4;
3231 pdesc->txdw5 = pdesc->txdw5;
3232 pdesc->txdw6 = pdesc->txdw6;
3233 pdesc->txdw7 = pdesc->txdw7;
3234 pdesc->txdw8 = pdesc->txdw8;
3235 pdesc->txdw9 = pdesc->txdw9;
3236
3237 rtl8723b_cal_txdesc_chksum(pdesc);
3238 }
3239
3240
3241
3242
3243
3244
3245
3246
3247 void rtl8723b_fill_fake_txdesc(
3248 struct adapter *padapter,
3249 u8 *pDesc,
3250 u32 BufferLen,
3251 u8 IsPsPoll,
3252 u8 IsBTQosNull,
3253 u8 bDataFrame
3254 )
3255 {
3256
3257 memset(pDesc, 0, TXDESC_SIZE);
3258
3259 SET_TX_DESC_FIRST_SEG_8723B(pDesc, 1);
3260 SET_TX_DESC_LAST_SEG_8723B(pDesc, 1);
3261
3262 SET_TX_DESC_OFFSET_8723B(pDesc, 0x28);
3263
3264 SET_TX_DESC_PKT_SIZE_8723B(pDesc, BufferLen);
3265 SET_TX_DESC_QUEUE_SEL_8723B(pDesc, QSLT_MGNT);
3266
3267
3268 if (IsPsPoll) {
3269 SET_TX_DESC_NAV_USE_HDR_8723B(pDesc, 1);
3270 } else {
3271 SET_TX_DESC_HWSEQ_EN_8723B(pDesc, 1);
3272 SET_TX_DESC_HWSEQ_SEL_8723B(pDesc, 0);
3273 }
3274
3275 if (IsBTQosNull) {
3276 SET_TX_DESC_BT_INT_8723B(pDesc, 1);
3277 }
3278
3279 SET_TX_DESC_USE_RATE_8723B(pDesc, 1);
3280 SET_TX_DESC_OWN_8723B((u8 *)pDesc, 1);
3281
3282 SET_TX_DESC_TX_RATE_8723B(pDesc, DESC8723B_RATE1M);
3283
3284
3285
3286
3287 if (bDataFrame) {
3288 u32 EncAlg;
3289
3290 EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
3291 switch (EncAlg) {
3292 case _NO_PRIVACY_:
3293 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0);
3294 break;
3295 case _WEP40_:
3296 case _WEP104_:
3297 case _TKIP_:
3298 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x1);
3299 break;
3300 case _SMS4_:
3301 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x2);
3302 break;
3303 case _AES_:
3304 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x3);
3305 break;
3306 default:
3307 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0);
3308 break;
3309 }
3310 }
3311
3312
3313
3314 rtl8723b_cal_txdesc_chksum((struct tx_desc *)pDesc);
3315 }
3316
3317 static void hw_var_set_opmode(struct adapter *padapter, u8 variable, u8 *val)
3318 {
3319 u8 val8;
3320 u8 mode = *((u8 *)val);
3321
3322 {
3323
3324 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3325 val8 |= DIS_TSF_UDT;
3326 rtw_write8(padapter, REG_BCN_CTRL, val8);
3327
3328
3329 Set_MSR(padapter, mode);
3330 DBG_871X("#### %s() -%d iface_type(0) mode = %d ####\n", __func__, __LINE__, mode);
3331
3332 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
3333 {
3334 StopTxBeacon(padapter);
3335 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
3336 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3337 rtw_write8(padapter, REG_DRVERLYINT, 0x05);
3338 UpdateInterruptMask8812AU(padapter, true, 0, IMR_BCNDMAINT0_8723B);
3339 #endif
3340
3341 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3342 UpdateInterruptMask8812AU(padapter, true, 0, (IMR_TXBCN0ERR_8723B|IMR_TXBCN0OK_8723B));
3343 #endif
3344
3345 #endif
3346 }
3347
3348
3349 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_ATIM);
3350
3351 } else if (mode == _HW_STATE_ADHOC_) {
3352 ResumeTxBeacon(padapter);
3353 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_BCNQ_SUB);
3354 } else if (mode == _HW_STATE_AP_) {
3355 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
3356 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3357 UpdateInterruptMask8723BU(padapter, true, IMR_BCNDMAINT0_8723B, 0);
3358 #endif
3359
3360 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3361 UpdateInterruptMask8723BU(padapter, true, (IMR_TXBCN0ERR_8723B|IMR_TXBCN0OK_8723B), 0);
3362 #endif
3363
3364 #endif
3365
3366 ResumeTxBeacon(padapter);
3367
3368 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|DIS_BCNQ_SUB);
3369
3370
3371 rtw_write32(padapter, REG_RCR, 0x7000208e);
3372
3373 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
3374
3375 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
3376
3377
3378 rtw_write8(padapter, REG_BCNDMATIM, 0x02);
3379
3380
3381 rtw_write8(padapter, REG_ATIMWND, 0x0a);
3382 rtw_write16(padapter, REG_BCNTCFG, 0x00);
3383 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
3384 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
3385
3386
3387 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
3388
3389
3390
3391 rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT|EN_BCN_FUNCTION|EN_TXBCN_RPT|DIS_BCNQ_SUB));
3392
3393
3394
3395 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
3396
3397
3398 rtw_write8(
3399 padapter,
3400 REG_CCK_CHECK_8723B,
3401 (rtw_read8(padapter, REG_CCK_CHECK_8723B)&~BIT_BCN_PORT_SEL)
3402 );
3403
3404
3405 val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
3406 val8 |= DIS_ATIM;
3407 rtw_write8(padapter, REG_BCN_CTRL_1, val8);
3408 }
3409 }
3410 }
3411
3412 static void hw_var_set_macaddr(struct adapter *padapter, u8 variable, u8 *val)
3413 {
3414 u8 idx = 0;
3415 u32 reg_macid;
3416
3417 reg_macid = REG_MACID;
3418
3419 for (idx = 0 ; idx < 6; idx++)
3420 rtw_write8(GET_PRIMARY_ADAPTER(padapter), (reg_macid+idx), val[idx]);
3421 }
3422
3423 static void hw_var_set_bssid(struct adapter *padapter, u8 variable, u8 *val)
3424 {
3425 u8 idx = 0;
3426 u32 reg_bssid;
3427
3428 reg_bssid = REG_BSSID;
3429
3430 for (idx = 0 ; idx < 6; idx++)
3431 rtw_write8(padapter, (reg_bssid+idx), val[idx]);
3432 }
3433
3434 static void hw_var_set_bcn_func(struct adapter *padapter, u8 variable, u8 *val)
3435 {
3436 u32 bcn_ctrl_reg;
3437
3438 bcn_ctrl_reg = REG_BCN_CTRL;
3439
3440 if (*(u8 *)val)
3441 rtw_write8(padapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
3442 else {
3443 u8 val8;
3444 val8 = rtw_read8(padapter, bcn_ctrl_reg);
3445 val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT);
3446
3447
3448 if (REG_BCN_CTRL == bcn_ctrl_reg)
3449 val8 |= EN_BCN_FUNCTION;
3450
3451 rtw_write8(padapter, bcn_ctrl_reg, val8);
3452 }
3453 }
3454
3455 static void hw_var_set_correct_tsf(struct adapter *padapter, u8 variable, u8 *val)
3456 {
3457 u8 val8;
3458 u64 tsf;
3459 struct mlme_ext_priv *pmlmeext;
3460 struct mlme_ext_info *pmlmeinfo;
3461
3462
3463 pmlmeext = &padapter->mlmeextpriv;
3464 pmlmeinfo = &pmlmeext->mlmext_info;
3465
3466 tsf = pmlmeext->TSFValue-do_div(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024))-1024;
3467
3468 if (
3469 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ||
3470 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
3471 )
3472 StopTxBeacon(padapter);
3473
3474 {
3475
3476 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3477 val8 &= ~EN_BCN_FUNCTION;
3478 rtw_write8(padapter, REG_BCN_CTRL, val8);
3479
3480 rtw_write32(padapter, REG_TSFTR, tsf);
3481 rtw_write32(padapter, REG_TSFTR+4, tsf>>32);
3482
3483
3484 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3485 val8 |= EN_BCN_FUNCTION;
3486 rtw_write8(padapter, REG_BCN_CTRL, val8);
3487 }
3488
3489 if (
3490 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ||
3491 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
3492 )
3493 ResumeTxBeacon(padapter);
3494 }
3495
3496 static void hw_var_set_mlme_disconnect(struct adapter *padapter, u8 variable, u8 *val)
3497 {
3498 u8 val8;
3499
3500
3501
3502
3503 rtw_write16(padapter, REG_RXFLTMAP2, 0);
3504
3505
3506 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
3507
3508
3509 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3510 val8 |= DIS_TSF_UDT;
3511 rtw_write8(padapter, REG_BCN_CTRL, val8);
3512 }
3513
3514 static void hw_var_set_mlme_sitesurvey(struct adapter *padapter, u8 variable, u8 *val)
3515 {
3516 u32 value_rcr, rcr_clear_bit, reg_bcn_ctl;
3517 u16 value_rxfltmap2;
3518 u8 val8;
3519 struct hal_com_data *pHalData;
3520 struct mlme_priv *pmlmepriv;
3521
3522
3523 pHalData = GET_HAL_DATA(padapter);
3524 pmlmepriv = &padapter->mlmepriv;
3525
3526 reg_bcn_ctl = REG_BCN_CTRL;
3527
3528 rcr_clear_bit = RCR_CBSSID_BCN;
3529
3530
3531 value_rxfltmap2 = 0;
3532
3533 if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == true))
3534 rcr_clear_bit = RCR_CBSSID_BCN;
3535
3536 value_rcr = rtw_read32(padapter, REG_RCR);
3537
3538 if (*((u8 *)val)) {
3539
3540 value_rcr &= ~(rcr_clear_bit);
3541 rtw_write32(padapter, REG_RCR, value_rcr);
3542
3543 rtw_write16(padapter, REG_RXFLTMAP2, value_rxfltmap2);
3544
3545 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
3546
3547 val8 = rtw_read8(padapter, reg_bcn_ctl);
3548 val8 |= DIS_TSF_UDT;
3549 rtw_write8(padapter, reg_bcn_ctl, val8);
3550 }
3551
3552
3553 pHalData->RegRRSR = rtw_read16(padapter, REG_RRSR);
3554 } else {
3555
3556 if (check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)))
3557
3558 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
3559
3560 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
3561
3562 val8 = rtw_read8(padapter, reg_bcn_ctl);
3563 val8 &= ~DIS_TSF_UDT;
3564 rtw_write8(padapter, reg_bcn_ctl, val8);
3565 }
3566
3567 value_rcr |= rcr_clear_bit;
3568 rtw_write32(padapter, REG_RCR, value_rcr);
3569
3570
3571 rtw_write16(padapter, REG_RRSR, pHalData->RegRRSR);
3572 }
3573 }
3574
3575 static void hw_var_set_mlme_join(struct adapter *padapter, u8 variable, u8 *val)
3576 {
3577 u8 val8;
3578 u16 val16;
3579 u32 val32;
3580 u8 RetryLimit;
3581 u8 type;
3582 struct mlme_priv *pmlmepriv;
3583 struct eeprom_priv *pEEPROM;
3584
3585
3586 RetryLimit = 0x30;
3587 type = *(u8 *)val;
3588 pmlmepriv = &padapter->mlmepriv;
3589 pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3590
3591 if (type == 0) {
3592
3593
3594 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
3595
3596 val32 = rtw_read32(padapter, REG_RCR);
3597 if (padapter->in_cta_test)
3598 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
3599 else
3600 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN;
3601 rtw_write32(padapter, REG_RCR, val32);
3602
3603 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
3604 RetryLimit = (pEEPROM->CustomerID == RT_CID_CCX) ? 7 : 48;
3605 else
3606 RetryLimit = 0x7;
3607 } else if (type == 1)
3608 rtw_write16(padapter, REG_RXFLTMAP2, 0x00);
3609 else if (type == 2) {
3610
3611 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3612 val8 &= ~DIS_TSF_UDT;
3613 rtw_write8(padapter, REG_BCN_CTRL, val8);
3614
3615 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
3616 RetryLimit = 0x7;
3617 }
3618
3619 val16 = (RetryLimit << RETRY_LIMIT_SHORT_SHIFT) | (RetryLimit << RETRY_LIMIT_LONG_SHIFT);
3620 rtw_write16(padapter, REG_RL, val16);
3621 }
3622
3623 void CCX_FwC2HTxRpt_8723b(struct adapter *padapter, u8 *pdata, u8 len)
3624 {
3625 u8 seq_no;
3626
3627 #define GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
3628 #define GET_8723B_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
3629
3630
3631
3632
3633 seq_no = *(pdata+6);
3634
3635 if (GET_8723B_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(pdata)) {
3636 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
3637 }
3638
3639
3640
3641
3642
3643
3644 else
3645 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
3646 }
3647
3648 s32 c2h_id_filter_ccx_8723b(u8 *buf)
3649 {
3650 struct c2h_evt_hdr_88xx *c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
3651 s32 ret = false;
3652 if (c2h_evt->id == C2H_CCX_TX_RPT)
3653 ret = true;
3654
3655 return ret;
3656 }
3657
3658
3659 s32 c2h_handler_8723b(struct adapter *padapter, u8 *buf)
3660 {
3661 struct c2h_evt_hdr_88xx *pC2hEvent = (struct c2h_evt_hdr_88xx *)buf;
3662 s32 ret = _SUCCESS;
3663 u8 index = 0;
3664
3665 if (!pC2hEvent) {
3666 DBG_8192C("%s(): pC2hEventis NULL\n", __func__);
3667 ret = _FAIL;
3668 goto exit;
3669 }
3670
3671 switch (pC2hEvent->id) {
3672 case C2H_AP_RPT_RSP:
3673 break;
3674 case C2H_DBG:
3675 {
3676 RT_TRACE(_module_hal_init_c_, _drv_info_, ("c2h_handler_8723b: %s\n", pC2hEvent->payload));
3677 }
3678 break;
3679
3680 case C2H_CCX_TX_RPT:
3681
3682 break;
3683
3684 case C2H_EXT_RA_RPT:
3685
3686 break;
3687
3688 case C2H_HW_INFO_EXCH:
3689 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], C2H_HW_INFO_EXCH\n"));
3690 for (index = 0; index < pC2hEvent->plen; index++) {
3691 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], tmpBuf[%d]= 0x%x\n", index, pC2hEvent->payload[index]));
3692 }
3693 break;
3694
3695 case C2H_8723B_BT_INFO:
3696 hal_btcoex_BtInfoNotify(padapter, pC2hEvent->plen, pC2hEvent->payload);
3697 break;
3698
3699 default:
3700 break;
3701 }
3702
3703
3704
3705
3706
3707 exit:
3708 return ret;
3709 }
3710
3711 static void process_c2h_event(struct adapter *padapter, PC2H_EVT_HDR pC2hEvent, u8 *c2hBuf)
3712 {
3713 u8 index = 0;
3714
3715 if (!c2hBuf) {
3716 DBG_8192C("%s c2hbuff is NULL\n", __func__);
3717 return;
3718 }
3719
3720 switch (pC2hEvent->CmdID) {
3721 case C2H_AP_RPT_RSP:
3722 break;
3723 case C2H_DBG:
3724 {
3725 RT_TRACE(_module_hal_init_c_, _drv_info_, ("C2HCommandHandler: %s\n", c2hBuf));
3726 }
3727 break;
3728
3729 case C2H_CCX_TX_RPT:
3730
3731 break;
3732
3733 case C2H_EXT_RA_RPT:
3734
3735 break;
3736
3737 case C2H_HW_INFO_EXCH:
3738 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], C2H_HW_INFO_EXCH\n"));
3739 for (index = 0; index < pC2hEvent->CmdLen; index++) {
3740 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], tmpBuf[%d]= 0x%x\n", index, c2hBuf[index]));
3741 }
3742 break;
3743
3744 case C2H_8723B_BT_INFO:
3745 hal_btcoex_BtInfoNotify(padapter, pC2hEvent->CmdLen, c2hBuf);
3746 break;
3747
3748 default:
3749 break;
3750 }
3751 }
3752
3753 void C2HPacketHandler_8723B(struct adapter *padapter, u8 *pbuffer, u16 length)
3754 {
3755 C2H_EVT_HDR C2hEvent;
3756 u8 *tmpBuf = NULL;
3757 #ifdef CONFIG_WOWLAN
3758 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
3759
3760 if (pwrpriv->wowlan_mode) {
3761 DBG_871X("%s(): return because wowolan_mode ==true! CMDID =%d\n", __func__, pbuffer[0]);
3762 return;
3763 }
3764 #endif
3765 C2hEvent.CmdID = pbuffer[0];
3766 C2hEvent.CmdSeq = pbuffer[1];
3767 C2hEvent.CmdLen = length-2;
3768 tmpBuf = pbuffer+2;
3769
3770
3771
3772 RT_PRINT_DATA(_module_hal_init_c_, _drv_notice_, "C2HPacketHandler_8723B(): Command Content:\n", tmpBuf, C2hEvent.CmdLen);
3773
3774 process_c2h_event(padapter, &C2hEvent, tmpBuf);
3775
3776 return;
3777 }
3778
3779 void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val)
3780 {
3781 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
3782 u8 val8;
3783 u32 val32;
3784
3785 switch (variable) {
3786 case HW_VAR_MEDIA_STATUS:
3787 val8 = rtw_read8(padapter, MSR) & 0x0c;
3788 val8 |= *val;
3789 rtw_write8(padapter, MSR, val8);
3790 break;
3791
3792 case HW_VAR_MEDIA_STATUS1:
3793 val8 = rtw_read8(padapter, MSR) & 0x03;
3794 val8 |= *val << 2;
3795 rtw_write8(padapter, MSR, val8);
3796 break;
3797
3798 case HW_VAR_SET_OPMODE:
3799 hw_var_set_opmode(padapter, variable, val);
3800 break;
3801
3802 case HW_VAR_MAC_ADDR:
3803 hw_var_set_macaddr(padapter, variable, val);
3804 break;
3805
3806 case HW_VAR_BSSID:
3807 hw_var_set_bssid(padapter, variable, val);
3808 break;
3809
3810 case HW_VAR_BASIC_RATE:
3811 {
3812 struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info;
3813 u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;
3814 u16 rrsr_2g_force_mask = (RRSR_11M|RRSR_5_5M|RRSR_1M);
3815 u16 rrsr_2g_allow_mask = (RRSR_24M|RRSR_12M|RRSR_6M|RRSR_CCK_RATES);
3816
3817 HalSetBrateCfg(padapter, val, &BrateCfg);
3818 input_b = BrateCfg;
3819
3820
3821 BrateCfg |= rrsr_2g_force_mask;
3822 BrateCfg &= rrsr_2g_allow_mask;
3823 masked = BrateCfg;
3824
3825 #ifdef CONFIG_CMCC_TEST
3826 BrateCfg |= (RRSR_11M|RRSR_5_5M|RRSR_1M);
3827 BrateCfg |= (RRSR_24M|RRSR_18M|RRSR_12M);
3828 #endif
3829
3830
3831 if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
3832
3833 if ((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0)
3834 BrateCfg |= RRSR_6M;
3835 }
3836 ioted = BrateCfg;
3837
3838 pHalData->BasicRateSet = BrateCfg;
3839
3840 DBG_8192C("HW_VAR_BASIC_RATE: %#x -> %#x -> %#x\n", input_b, masked, ioted);
3841
3842
3843 rtw_write16(padapter, REG_RRSR, BrateCfg);
3844 rtw_write8(padapter, REG_RRSR+2, rtw_read8(padapter, REG_RRSR+2)&0xf0);
3845 }
3846 break;
3847
3848 case HW_VAR_TXPAUSE:
3849 rtw_write8(padapter, REG_TXPAUSE, *val);
3850 break;
3851
3852 case HW_VAR_BCN_FUNC:
3853 hw_var_set_bcn_func(padapter, variable, val);
3854 break;
3855
3856 case HW_VAR_CORRECT_TSF:
3857 hw_var_set_correct_tsf(padapter, variable, val);
3858 break;
3859
3860 case HW_VAR_CHECK_BSSID:
3861 {
3862 u32 val32;
3863 val32 = rtw_read32(padapter, REG_RCR);
3864 if (*val)
3865 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN;
3866 else
3867 val32 &= ~(RCR_CBSSID_DATA|RCR_CBSSID_BCN);
3868 rtw_write32(padapter, REG_RCR, val32);
3869 }
3870 break;
3871
3872 case HW_VAR_MLME_DISCONNECT:
3873 hw_var_set_mlme_disconnect(padapter, variable, val);
3874 break;
3875
3876 case HW_VAR_MLME_SITESURVEY:
3877 hw_var_set_mlme_sitesurvey(padapter, variable, val);
3878
3879 hal_btcoex_ScanNotify(padapter, *val?true:false);
3880 break;
3881
3882 case HW_VAR_MLME_JOIN:
3883 hw_var_set_mlme_join(padapter, variable, val);
3884
3885 switch (*val) {
3886 case 0:
3887
3888 hal_btcoex_ConnectNotify(padapter, true);
3889 break;
3890 case 1:
3891
3892 hal_btcoex_ConnectNotify(padapter, false);
3893 break;
3894 case 2:
3895
3896
3897 break;
3898 }
3899 break;
3900
3901 case HW_VAR_ON_RCR_AM:
3902 val32 = rtw_read32(padapter, REG_RCR);
3903 val32 |= RCR_AM;
3904 rtw_write32(padapter, REG_RCR, val32);
3905 DBG_8192C("%s, %d, RCR = %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR));
3906 break;
3907
3908 case HW_VAR_OFF_RCR_AM:
3909 val32 = rtw_read32(padapter, REG_RCR);
3910 val32 &= ~RCR_AM;
3911 rtw_write32(padapter, REG_RCR, val32);
3912 DBG_8192C("%s, %d, RCR = %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR));
3913 break;
3914
3915 case HW_VAR_BEACON_INTERVAL:
3916 rtw_write16(padapter, REG_BCN_INTERVAL, *((u16 *)val));
3917 break;
3918
3919 case HW_VAR_SLOT_TIME:
3920 rtw_write8(padapter, REG_SLOT, *val);
3921 break;
3922
3923 case HW_VAR_RESP_SIFS:
3924
3925
3926 rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]);
3927 rtw_write8(padapter, REG_RESP_SIFS_CCK+1, val[1]);
3928
3929 rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]);
3930 rtw_write8(padapter, REG_RESP_SIFS_OFDM+1, val[3]);
3931 break;
3932
3933 case HW_VAR_ACK_PREAMBLE:
3934 {
3935 u8 regTmp;
3936 u8 bShortPreamble = *val;
3937
3938
3939
3940 regTmp = 0;
3941 if (bShortPreamble)
3942 regTmp |= 0x80;
3943 rtw_write8(padapter, REG_RRSR+2, regTmp);
3944 }
3945 break;
3946
3947 case HW_VAR_CAM_EMPTY_ENTRY:
3948 {
3949 u8 ucIndex = *val;
3950 u8 i;
3951 u32 ulCommand = 0;
3952 u32 ulContent = 0;
3953 u32 ulEncAlgo = CAM_AES;
3954
3955 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
3956
3957 if (i == 0) {
3958 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
3959
3960 } else
3961 ulContent = 0;
3962
3963
3964 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
3965 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
3966
3967 rtw_write32(padapter, WCAMI, ulContent);
3968
3969 rtw_write32(padapter, RWCAM, ulCommand);
3970
3971 }
3972 }
3973 break;
3974
3975 case HW_VAR_CAM_INVALID_ALL:
3976 rtw_write32(padapter, RWCAM, BIT(31)|BIT(30));
3977 break;
3978
3979 case HW_VAR_CAM_WRITE:
3980 {
3981 u32 cmd;
3982 u32 *cam_val = (u32 *)val;
3983
3984 rtw_write32(padapter, WCAMI, cam_val[0]);
3985
3986 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
3987 rtw_write32(padapter, RWCAM, cmd);
3988 }
3989 break;
3990
3991 case HW_VAR_AC_PARAM_VO:
3992 rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val));
3993 break;
3994
3995 case HW_VAR_AC_PARAM_VI:
3996 rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val));
3997 break;
3998
3999 case HW_VAR_AC_PARAM_BE:
4000 pHalData->AcParam_BE = ((u32 *)(val))[0];
4001 rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val));
4002 break;
4003
4004 case HW_VAR_AC_PARAM_BK:
4005 rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val));
4006 break;
4007
4008 case HW_VAR_ACM_CTRL:
4009 {
4010 u8 ctrl = *((u8 *)val);
4011 u8 hwctrl = 0;
4012
4013 if (ctrl != 0) {
4014 hwctrl |= AcmHw_HwEn;
4015
4016 if (ctrl & BIT(1))
4017 hwctrl |= AcmHw_BeqEn;
4018
4019 if (ctrl & BIT(2))
4020 hwctrl |= AcmHw_ViqEn;
4021
4022 if (ctrl & BIT(3))
4023 hwctrl |= AcmHw_VoqEn;
4024 }
4025
4026 DBG_8192C("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
4027 rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
4028 }
4029 break;
4030
4031 case HW_VAR_AMPDU_FACTOR:
4032 {
4033 u32 AMPDULen = (*((u8 *)val));
4034
4035 if (AMPDULen < HT_AGG_SIZE_32K)
4036 AMPDULen = (0x2000 << (*((u8 *)val)))-1;
4037 else
4038 AMPDULen = 0x7fff;
4039
4040 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723B, AMPDULen);
4041 }
4042 break;
4043
4044 case HW_VAR_H2C_FW_PWRMODE:
4045 {
4046 u8 psmode = *val;
4047
4048
4049
4050 if (psmode != PS_MODE_ACTIVE) {
4051 ODM_RF_Saving(&pHalData->odmpriv, true);
4052 }
4053
4054
4055
4056
4057
4058
4059 rtl8723b_set_FwPwrMode_cmd(padapter, psmode);
4060 }
4061 break;
4062 case HW_VAR_H2C_PS_TUNE_PARAM:
4063 rtl8723b_set_FwPsTuneParam_cmd(padapter);
4064 break;
4065
4066 case HW_VAR_H2C_FW_JOINBSSRPT:
4067 rtl8723b_set_FwJoinBssRpt_cmd(padapter, *val);
4068 break;
4069
4070 case HW_VAR_INITIAL_GAIN:
4071 {
4072 DIG_T *pDigTable = &pHalData->odmpriv.DM_DigTable;
4073 u32 rx_gain = *(u32 *)val;
4074
4075 if (rx_gain == 0xff) {
4076 ODM_Write_DIG(&pHalData->odmpriv, pDigTable->BackupIGValue);
4077 } else {
4078 pDigTable->BackupIGValue = pDigTable->CurIGValue;
4079 ODM_Write_DIG(&pHalData->odmpriv, rx_gain);
4080 }
4081 }
4082 break;
4083
4084 case HW_VAR_EFUSE_USAGE:
4085 pHalData->EfuseUsedPercentage = *val;
4086 break;
4087
4088 case HW_VAR_EFUSE_BYTES:
4089 pHalData->EfuseUsedBytes = *((u16 *)val);
4090 break;
4091
4092 case HW_VAR_EFUSE_BT_USAGE:
4093 #ifdef HAL_EFUSE_MEMORY
4094 pHalData->EfuseHal.BTEfuseUsedPercentage = *val;
4095 #endif
4096 break;
4097
4098 case HW_VAR_EFUSE_BT_BYTES:
4099 #ifdef HAL_EFUSE_MEMORY
4100 pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val);
4101 #else
4102 BTEfuseUsedBytes = *((u16 *)val);
4103 #endif
4104 break;
4105
4106 case HW_VAR_FIFO_CLEARN_UP:
4107 {
4108 #define RW_RELEASE_EN BIT(18)
4109 #define RXDMA_IDLE BIT(17)
4110
4111 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
4112 u8 trycnt = 100;
4113
4114
4115 rtw_write8(padapter, REG_TXPAUSE, 0xff);
4116
4117
4118 padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
4119
4120 if (!pwrpriv->bkeepfwalive) {
4121
4122 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
4123 val32 |= RW_RELEASE_EN;
4124 rtw_write32(padapter, REG_RXPKT_NUM, val32);
4125 do {
4126 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
4127 val32 &= RXDMA_IDLE;
4128 if (val32)
4129 break;
4130
4131 DBG_871X("%s: [HW_VAR_FIFO_CLEARN_UP] val =%x times:%d\n", __func__, val32, trycnt);
4132 } while (--trycnt);
4133
4134 if (trycnt == 0) {
4135 DBG_8192C("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n");
4136 }
4137
4138
4139 rtw_write16(padapter, REG_RQPN_NPQ, 0);
4140 rtw_write32(padapter, REG_RQPN, 0x80000000);
4141 mdelay(2);
4142 }
4143 }
4144 break;
4145
4146 case HW_VAR_APFM_ON_MAC:
4147 pHalData->bMacPwrCtrlOn = *val;
4148 DBG_8192C("%s: bMacPwrCtrlOn =%d\n", __func__, pHalData->bMacPwrCtrlOn);
4149 break;
4150
4151 case HW_VAR_NAV_UPPER:
4152 {
4153 u32 usNavUpper = *((u32 *)val);
4154
4155 if (usNavUpper > HAL_NAV_UPPER_UNIT_8723B * 0xFF) {
4156 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", usNavUpper, HAL_NAV_UPPER_UNIT_8723B));
4157 break;
4158 }
4159
4160
4161
4162 usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT_8723B - 1) / HAL_NAV_UPPER_UNIT_8723B;
4163 rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
4164 }
4165 break;
4166
4167 case HW_VAR_H2C_MEDIA_STATUS_RPT:
4168 {
4169 u16 mstatus_rpt = (*(u16 *)val);
4170 u8 mstatus, macId;
4171
4172 mstatus = (u8) (mstatus_rpt & 0xFF);
4173 macId = (u8)(mstatus_rpt >> 8);
4174 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, mstatus, macId);
4175 }
4176 break;
4177 case HW_VAR_BCN_VALID:
4178 {
4179
4180 val8 = rtw_read8(padapter, REG_TDECTRL+2);
4181 val8 |= BIT(0);
4182 rtw_write8(padapter, REG_TDECTRL+2, val8);
4183 }
4184 break;
4185
4186 case HW_VAR_DL_BCN_SEL:
4187 {
4188
4189 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2);
4190 val8 &= ~BIT(4);
4191 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8);
4192 }
4193 break;
4194
4195 case HW_VAR_DO_IQK:
4196 pHalData->bNeedIQK = true;
4197 break;
4198
4199 case HW_VAR_DL_RSVD_PAGE:
4200 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true)
4201 rtl8723b_download_BTCoex_AP_mode_rsvd_page(padapter);
4202 else
4203 rtl8723b_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
4204 break;
4205
4206 case HW_VAR_MACID_SLEEP:
4207
4208 val32 = *(u32 *)val;
4209 if (val32 > 31) {
4210 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] Invalid macid(%d)\n",
4211 FUNC_ADPT_ARG(padapter), val32);
4212 break;
4213 }
4214 val8 = (u8)val32;
4215
4216 val32 = rtw_read32(padapter, REG_MACID_SLEEP);
4217 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid =%d, org MACID_SLEEP = 0x%08X\n",
4218 FUNC_ADPT_ARG(padapter), val8, val32);
4219 if (val32 & BIT(val8))
4220 break;
4221 val32 |= BIT(val8);
4222 rtw_write32(padapter, REG_MACID_SLEEP, val32);
4223 break;
4224
4225 case HW_VAR_MACID_WAKEUP:
4226
4227 val32 = *(u32 *)val;
4228 if (val32 > 31) {
4229 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] Invalid macid(%d)\n",
4230 FUNC_ADPT_ARG(padapter), val32);
4231 break;
4232 }
4233 val8 = (u8)val32;
4234
4235 val32 = rtw_read32(padapter, REG_MACID_SLEEP);
4236 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid =%d, org MACID_SLEEP = 0x%08X\n",
4237 FUNC_ADPT_ARG(padapter), val8, val32);
4238 if (!(val32 & BIT(val8)))
4239 break;
4240 val32 &= ~BIT(val8);
4241 rtw_write32(padapter, REG_MACID_SLEEP, val32);
4242 break;
4243
4244 default:
4245 SetHwReg(padapter, variable, val);
4246 break;
4247 }
4248 }
4249
4250 void GetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val)
4251 {
4252 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
4253 u8 val8;
4254 u16 val16;
4255
4256 switch (variable) {
4257 case HW_VAR_TXPAUSE:
4258 *val = rtw_read8(padapter, REG_TXPAUSE);
4259 break;
4260
4261 case HW_VAR_BCN_VALID:
4262 {
4263
4264 val8 = rtw_read8(padapter, REG_TDECTRL+2);
4265 *val = (BIT(0) & val8) ? true : false;
4266 }
4267 break;
4268
4269 case HW_VAR_FWLPS_RF_ON:
4270 {
4271
4272 u32 valRCR;
4273
4274 if (
4275 padapter->bSurpriseRemoved ||
4276 (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)
4277 ) {
4278
4279
4280 *val = true;
4281 } else {
4282 valRCR = rtw_read32(padapter, REG_RCR);
4283 valRCR &= 0x00070000;
4284 if (valRCR)
4285 *val = false;
4286 else
4287 *val = true;
4288 }
4289 }
4290 break;
4291
4292 case HW_VAR_EFUSE_USAGE:
4293 *val = pHalData->EfuseUsedPercentage;
4294 break;
4295
4296 case HW_VAR_EFUSE_BYTES:
4297 *((u16 *)val) = pHalData->EfuseUsedBytes;
4298 break;
4299
4300 case HW_VAR_EFUSE_BT_USAGE:
4301 #ifdef HAL_EFUSE_MEMORY
4302 *val = pHalData->EfuseHal.BTEfuseUsedPercentage;
4303 #endif
4304 break;
4305
4306 case HW_VAR_EFUSE_BT_BYTES:
4307 #ifdef HAL_EFUSE_MEMORY
4308 *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes;
4309 #else
4310 *((u16 *)val) = BTEfuseUsedBytes;
4311 #endif
4312 break;
4313
4314 case HW_VAR_APFM_ON_MAC:
4315 *val = pHalData->bMacPwrCtrlOn;
4316 break;
4317 case HW_VAR_CHK_HI_QUEUE_EMPTY:
4318 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
4319 *val = (val16 & BIT(10)) ? true:false;
4320 break;
4321 #ifdef CONFIG_WOWLAN
4322 case HW_VAR_RPWM_TOG:
4323 *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1) & BIT7;
4324 break;
4325 case HW_VAR_WAKEUP_REASON:
4326 *val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
4327 if (*val == 0xEA)
4328 *val = 0;
4329 break;
4330 case HW_VAR_SYS_CLKR:
4331 *val = rtw_read8(padapter, REG_SYS_CLKR);
4332 break;
4333 #endif
4334 default:
4335 GetHwReg(padapter, variable, val);
4336 break;
4337 }
4338 }
4339
4340
4341
4342
4343
4344 u8 SetHalDefVar8723B(struct adapter *padapter, enum HAL_DEF_VARIABLE variable, void *pval)
4345 {
4346 u8 bResult;
4347
4348 bResult = _SUCCESS;
4349
4350 switch (variable) {
4351 default:
4352 bResult = SetHalDefVar(padapter, variable, pval);
4353 break;
4354 }
4355
4356 return bResult;
4357 }
4358
4359
4360
4361
4362
4363 u8 GetHalDefVar8723B(struct adapter *padapter, enum HAL_DEF_VARIABLE variable, void *pval)
4364 {
4365 u8 bResult;
4366
4367 bResult = _SUCCESS;
4368
4369 switch (variable) {
4370 case HAL_DEF_MAX_RECVBUF_SZ:
4371 *((u32 *)pval) = MAX_RECVBUF_SZ;
4372 break;
4373
4374 case HAL_DEF_RX_PACKET_OFFSET:
4375 *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ*8;
4376 break;
4377
4378 case HW_VAR_MAX_RX_AMPDU_FACTOR:
4379
4380
4381
4382 *(u32 *)pval = MAX_AMPDU_FACTOR_16K;
4383 break;
4384 case HAL_DEF_TX_LDPC:
4385 case HAL_DEF_RX_LDPC:
4386 *((u8 *)pval) = false;
4387 break;
4388 case HAL_DEF_TX_STBC:
4389 *((u8 *)pval) = 0;
4390 break;
4391 case HAL_DEF_RX_STBC:
4392 *((u8 *)pval) = 1;
4393 break;
4394 case HAL_DEF_EXPLICIT_BEAMFORMER:
4395 case HAL_DEF_EXPLICIT_BEAMFORMEE:
4396 *((u8 *)pval) = false;
4397 break;
4398
4399 case HW_DEF_RA_INFO_DUMP:
4400 {
4401 u8 mac_id = *(u8 *)pval;
4402 u32 cmd;
4403 u32 ra_info1, ra_info2;
4404 u32 rate_mask1, rate_mask2;
4405 u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate;
4406
4407 DBG_8192C("============ RA status check Mac_id:%d ===================\n", mac_id);
4408
4409 cmd = 0x40000100 | mac_id;
4410 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd);
4411 msleep(10);
4412 ra_info1 = rtw_read32(padapter, 0x2F0);
4413 curr_tx_rate = ra_info1&0x7F;
4414 curr_tx_sgi = (ra_info1>>7)&0x01;
4415 DBG_8192C("[ ra_info1:0x%08x ] =>cur_tx_rate = %s, cur_sgi:%d, PWRSTS = 0x%02x \n",
4416 ra_info1,
4417 HDATA_RATE(curr_tx_rate),
4418 curr_tx_sgi,
4419 (ra_info1>>8) & 0x07);
4420
4421 cmd = 0x40000400 | mac_id;
4422 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd);
4423 msleep(10);
4424 ra_info1 = rtw_read32(padapter, 0x2F0);
4425 ra_info2 = rtw_read32(padapter, 0x2F4);
4426 rate_mask1 = rtw_read32(padapter, 0x2F8);
4427 rate_mask2 = rtw_read32(padapter, 0x2FC);
4428 hight_rate = ra_info2&0xFF;
4429 lowest_rate = (ra_info2>>8) & 0xFF;
4430
4431 DBG_8192C("[ ra_info1:0x%08x ] =>RSSI =%d, BW_setting = 0x%02x, DISRA = 0x%02x, VHT_EN = 0x%02x\n",
4432 ra_info1,
4433 ra_info1&0xFF,
4434 (ra_info1>>8) & 0xFF,
4435 (ra_info1>>16) & 0xFF,
4436 (ra_info1>>24) & 0xFF);
4437
4438 DBG_8192C("[ ra_info2:0x%08x ] =>hight_rate =%s, lowest_rate =%s, SGI = 0x%02x, RateID =%d\n",
4439 ra_info2,
4440 HDATA_RATE(hight_rate),
4441 HDATA_RATE(lowest_rate),
4442 (ra_info2>>16) & 0xFF,
4443 (ra_info2>>24) & 0xFF);
4444
4445 DBG_8192C("rate_mask2 = 0x%08x, rate_mask1 = 0x%08x\n", rate_mask2, rate_mask1);
4446
4447 }
4448 break;
4449
4450 case HAL_DEF_TX_PAGE_BOUNDARY:
4451 if (!padapter->registrypriv.wifi_spec) {
4452 *(u8 *)pval = TX_PAGE_BOUNDARY_8723B;
4453 } else {
4454 *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
4455 }
4456 break;
4457
4458 case HAL_DEF_MACID_SLEEP:
4459 *(u8 *)pval = true;
4460 break;
4461
4462 default:
4463 bResult = GetHalDefVar(padapter, variable, pval);
4464 break;
4465 }
4466
4467 return bResult;
4468 }
4469
4470 #ifdef CONFIG_WOWLAN
4471 void Hal_DetectWoWMode(struct adapter *padapter)
4472 {
4473 adapter_to_pwrctl(padapter)->bSupportRemoteWakeup = true;
4474 DBG_871X("%s\n", __func__);
4475 }
4476 #endif
4477
4478 void rtl8723b_start_thread(struct adapter *padapter)
4479 {
4480 #ifndef CONFIG_SDIO_TX_TASKLET
4481 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
4482
4483 xmitpriv->SdioXmitThread = kthread_run(rtl8723bs_xmit_thread, padapter, "RTWHALXT");
4484 if (IS_ERR(xmitpriv->SdioXmitThread)) {
4485 RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8723bs_xmit_thread FAIL!!\n", __func__));
4486 }
4487 #endif
4488 }
4489
4490 void rtl8723b_stop_thread(struct adapter *padapter)
4491 {
4492 #ifndef CONFIG_SDIO_TX_TASKLET
4493 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
4494
4495
4496 if (xmitpriv->SdioXmitThread) {
4497 complete(&xmitpriv->SdioXmitStart);
4498 wait_for_completion(&xmitpriv->SdioXmitTerminate);
4499 xmitpriv->SdioXmitThread = NULL;
4500 }
4501 #endif
4502 }
4503
4504 #if defined(CONFIG_CHECK_BT_HANG)
4505 extern void check_bt_status_work(void *data);
4506 void rtl8723bs_init_checkbthang_workqueue(struct adapter *adapter)
4507 {
4508 adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0);
4509 INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work);
4510 }
4511
4512 void rtl8723bs_free_checkbthang_workqueue(struct adapter *adapter)
4513 {
4514 if (adapter->priv_checkbt_wq) {
4515 cancel_delayed_work_sync(&adapter->checkbt_work);
4516 flush_workqueue(adapter->priv_checkbt_wq);
4517 destroy_workqueue(adapter->priv_checkbt_wq);
4518 adapter->priv_checkbt_wq = NULL;
4519 }
4520 }
4521
4522 void rtl8723bs_cancle_checkbthang_workqueue(struct adapter *adapter)
4523 {
4524 if (adapter->priv_checkbt_wq)
4525 cancel_delayed_work_sync(&adapter->checkbt_work);
4526 }
4527
4528 void rtl8723bs_hal_check_bt_hang(struct adapter *adapter)
4529 {
4530 if (adapter->priv_checkbt_wq)
4531 queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0);
4532 }
4533 #endif