1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8
9 #ifndef __HALDMOUTSRC_H__
10 #define __HALDMOUTSRC_H__
11
12 /* Definition */
13 /* Define all team support ability. */
14
15 /* Define for all teams. Please Define the constant in your precomp header. */
16
17 /* define DM_ODM_SUPPORT_AP 0 */
18 /* define DM_ODM_SUPPORT_ADSL 0 */
19 /* define DM_ODM_SUPPORT_CE 0 */
20 /* define DM_ODM_SUPPORT_MP 1 */
21
22 /* Define ODM SW team support flag. */
23
24 /* Antenna Switch Relative Definition. */
25
26 /* Add new function SwAntDivCheck8192C(). */
27 /* This is the main function of Antenna diversity function before link. */
28 /* Mainly, it just retains last scan result and scan again. */
29 /* After that, it compares the scan result to see which one gets better
30 * RSSI. It selects antenna with better receiving power and returns better
31 * scan result.
32 */
33
34 #define TP_MODE 0
35 #define RSSI_MODE 1
36 #define TRAFFIC_LOW 0
37 #define TRAFFIC_HIGH 1
38
39 /* 3 Tx Power Tracking */
40 /* 3============================================================ */
41 #define DPK_DELTA_MAPPING_NUM 13
42 #define index_mapping_HP_NUM 15
43
44
45 /* */
46 /* 3 PSD Handler */
47 /* 3============================================================ */
48
49 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
50 #define MODE_40M 0 /* 0:20M, 1:40M */
51 #define PSD_TH2 3
52 #define PSD_CHM 20 /* Minimum channel number for BT AFH */
53 #define SIR_STEP_SIZE 3
54 #define Smooth_Size_1 5
55 #define Smooth_TH_1 3
56 #define Smooth_Size_2 10
57 #define Smooth_TH_2 4
58 #define Smooth_Size_3 20
59 #define Smooth_TH_3 4
60 #define Smooth_Step_Size 5
61 #define Adaptive_SIR 1
62 #define PSD_RESCAN 4
63 #define PSD_SCAN_INTERVAL 700 /* ms */
64
65 /* 8723A High Power IGI Setting */
66 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
67 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
68 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
69
70 /* LPS define */
71 #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
72 #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
73 #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
74 #define RSSI_OFFSET_DIG 0x05;
75
76 struct rtw_dig {
77 u8 Dig_Enable_Flag;
78 u8 Dig_Ext_Port_Stage;
79
80 int RssiLowThresh;
81 int RssiHighThresh;
82
83 u32 FALowThresh;
84 u32 FAHighThresh;
85
86 u8 CurSTAConnectState;
87 u8 PreSTAConnectState;
88 u8 CurMultiSTAConnectState;
89
90 u8 PreIGValue;
91 u8 CurIGValue;
92 u8 BackupIGValue;
93
94 s8 BackoffVal;
95 s8 BackoffVal_range_max;
96 s8 BackoffVal_range_min;
97 u8 rx_gain_range_max;
98 u8 rx_gain_range_min;
99 u8 Rssi_val_min;
100
101 u8 PreCCK_CCAThres;
102 u8 CurCCK_CCAThres;
103 u8 PreCCKPDState;
104 u8 CurCCKPDState;
105
106 u8 LargeFAHit;
107 u8 ForbiddenIGI;
108 u32 Recover_cnt;
109
110 u8 DIG_Dynamic_MIN_0;
111 u8 DIG_Dynamic_MIN_1;
112 bool bMediaConnect_0;
113 bool bMediaConnect_1;
114
115 u32 AntDiv_RSSI_max;
116 u32 RSSI_max;
117 };
118
119 struct rtl_ps {
120 u8 PreCCAState;
121 u8 CurCCAState;
122
123 u8 PreRFState;
124 u8 CurRFState;
125
126 int Rssi_val_min;
127
128 u8 initialize;
129 u32 Reg874, RegC70, Reg85C, RegA74;
130
131 };
132
133 struct false_alarm_stats {
134 u32 Cnt_Parity_Fail;
135 u32 Cnt_Rate_Illegal;
136 u32 Cnt_Crc8_fail;
137 u32 Cnt_Mcs_fail;
138 u32 Cnt_Ofdm_fail;
139 u32 Cnt_Cck_fail;
140 u32 Cnt_all;
141 u32 Cnt_Fast_Fsync;
142 u32 Cnt_SB_Search_fail;
143 u32 Cnt_OFDM_CCA;
144 u32 Cnt_CCK_CCA;
145 u32 Cnt_CCA_all;
146 u32 Cnt_BW_USC; /* Gary */
147 u32 Cnt_BW_LSC; /* Gary */
148 };
149
150 struct rx_hpc {
151 u8 RXHP_flag;
152 u8 PSD_func_trigger;
153 u8 PSD_bitmap_RXHP[80];
154 u8 Pre_IGI;
155 u8 Cur_IGI;
156 u8 Pre_pw_th;
157 u8 Cur_pw_th;
158 bool First_time_enter;
159 bool RXHP_enable;
160 u8 TP_Mode;
161 struct timer_list PSDTimer;
162 };
163
164 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
165 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
166
167 /* This indicates two different steps. */
168 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
169 * the signal on the air.
170 */
171 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
172 * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
173 * switch antenna.
174 */
175
176 #define SWAW_STEP_PEAK 0
177 #define SWAW_STEP_DETERMINE 1
178
179 #define TP_MODE 0
180 #define RSSI_MODE 1
181 #define TRAFFIC_LOW 0
182 #define TRAFFIC_HIGH 1
183
184 struct sw_ant_switch {
185 u8 try_flag;
186 s32 PreRSSI;
187 u8 CurAntenna;
188 u8 PreAntenna;
189 u8 RSSI_Trying;
190 u8 TestMode;
191 u8 bTriggerAntennaSwitch;
192 u8 SelectAntennaMap;
193 u8 RSSI_target;
194
195 /* Before link Antenna Switch check */
196 u8 SWAS_NoLink_State;
197 u32 SWAS_NoLink_BK_Reg860;
198 bool ANTA_ON; /* To indicate Ant A is or not */
199 bool ANTB_ON; /* To indicate Ant B is on or not */
200
201 s32 RSSI_sum_A;
202 s32 RSSI_sum_B;
203 s32 RSSI_cnt_A;
204 s32 RSSI_cnt_B;
205 u64 lastTxOkCnt;
206 u64 lastRxOkCnt;
207 u64 TXByteCnt_A;
208 u64 TXByteCnt_B;
209 u64 RXByteCnt_A;
210 u64 RXByteCnt_B;
211 u8 TrafficLoad;
212 struct timer_list SwAntennaSwitchTimer;
213 /* Hybrid Antenna Diversity */
214 u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
215 u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
216 u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
217 u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
218 u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
219 u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
220 u8 TxAnt[ASSOCIATE_ENTRY_NUM];
221 u8 TargetSTA;
222 u8 antsel;
223 u8 RxIdleAnt;
224 };
225
226 struct edca_turbo {
227 bool bCurrentTurboEDCA;
228 bool bIsCurRDLState;
229 u32 prv_traffic_idx; /* edca turbo */
230 };
231
232 struct odm_rate_adapt {
233 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
234 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
235 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
236 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
237 u32 LastRATR; /* RATR Register Content */
238 };
239
240 #define IQK_MAC_REG_NUM 4
241 #define IQK_ADDA_REG_NUM 16
242 #define IQK_BB_REG_NUM_MAX 10
243 #define IQK_BB_REG_NUM 9
244 #define HP_THERMAL_NUM 8
245
246 #define AVG_THERMAL_NUM 8
247 #define IQK_Matrix_REG_NUM 8
248 #define IQK_Matrix_Settings_NUM 1+24+21
249
250 #define DM_Type_ByFWi 0
251 #define DM_Type_ByDriver 1
252
253 /* Declare for common info */
254
255 struct odm_phy_status_info {
256 u8 RxPWDBAll;
257 u8 SignalQuality; /* in 0-100 index. */
258 u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
259 u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */
260 s8 RxPower; /* in dBm Translate from PWdB */
261 s8 RecvSignalPower;/* Real power in dBm for this packet, no
262 * beautification and aggregation. Keep this raw
263 * info to be used for the other procedures.
264 */
265 u8 BTRxRSSIPercentage;
266 u8 SignalStrength; /* in 0-100 index. */
267 u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
268 u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
269 };
270
271 struct odm_phy_dbg_info {
272 /* ODM Write,debug info */
273 s8 RxSNRdB[MAX_PATH_NUM_92CS];
274 u64 NumQryPhyStatus;
275 u64 NumQryPhyStatusCCK;
276 u64 NumQryPhyStatusOFDM;
277 /* Others */
278 s32 RxEVM[MAX_PATH_NUM_92CS];
279 };
280
281 struct odm_per_pkt_info {
282 s8 Rate;
283 u8 StationID;
284 bool bPacketMatchBSSID;
285 bool bPacketToSelf;
286 bool bPacketBeacon;
287 };
288
289 struct odm_mac_status_info {
290 u8 test;
291 };
292
293 enum odm_ability {
294 /* BB Team */
295 ODM_DIG = 0x00000001,
296 ODM_HIGH_POWER = 0x00000002,
297 ODM_CCK_CCA_TH = 0x00000004,
298 ODM_FA_STATISTICS = 0x00000008,
299 ODM_RAMASK = 0x00000010,
300 ODM_RSSI_MONITOR = 0x00000020,
301 ODM_SW_ANTDIV = 0x00000040,
302 ODM_HW_ANTDIV = 0x00000080,
303 ODM_BB_PWRSV = 0x00000100,
304 ODM_2TPATHDIV = 0x00000200,
305 ODM_1TPATHDIV = 0x00000400,
306 ODM_PSD2AFH = 0x00000800
307 };
308
309 /* 2011/10/20 MH Define Common info enum for all team. */
310
311 enum odm_common_info_def {
312 /* Fixed value: */
313
314 /* HOOK BEFORE REG INIT----------- */
315 ODM_CMNINFO_PLATFORM = 0,
316 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
317 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */
318 ODM_CMNINFO_MP_TEST_CHIP,
319 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */
320 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */
321 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
322 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */
323 ODM_CMNINFO_EXT_LNA, /* true */
324 ODM_CMNINFO_EXT_PA,
325 ODM_CMNINFO_EXT_TRSW,
326 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
327 ODM_CMNINFO_BINHCT_TEST,
328 ODM_CMNINFO_BWIFI_TEST,
329 ODM_CMNINFO_SMART_CONCURRENT,
330 /* HOOK BEFORE REG INIT----------- */
331
332 /* Dynamic value: */
333 /* POINTER REFERENCE----------- */
334 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */
335 ODM_CMNINFO_TX_UNI,
336 ODM_CMNINFO_RX_UNI,
337 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */
338 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */
339 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */
340 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */
341 ODM_CMNINFO_BW, /* ODM_BW_E */
342 ODM_CMNINFO_CHNL,
343
344 ODM_CMNINFO_DMSP_GET_VALUE,
345 ODM_CMNINFO_BUDDY_ADAPTOR,
346 ODM_CMNINFO_DMSP_IS_MASTER,
347 ODM_CMNINFO_SCAN,
348 ODM_CMNINFO_POWER_SAVING,
349 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */
350 ODM_CMNINFO_DRV_STOP,
351 ODM_CMNINFO_PNP_IN,
352 ODM_CMNINFO_INIT_ON,
353 ODM_CMNINFO_ANT_TEST,
354 ODM_CMNINFO_NET_CLOSED,
355 ODM_CMNINFO_MP_MODE,
356 /* POINTER REFERENCE----------- */
357
358 /* CALL BY VALUE------------- */
359 ODM_CMNINFO_WIFI_DIRECT,
360 ODM_CMNINFO_WIFI_DISPLAY,
361 ODM_CMNINFO_LINK,
362 ODM_CMNINFO_RSSI_MIN,
363 ODM_CMNINFO_DBG_COMP, /* u64 */
364 ODM_CMNINFO_DBG_LEVEL, /* u32 */
365 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
366 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
367 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
368 ODM_CMNINFO_BT_DISABLED,
369 ODM_CMNINFO_BT_OPERATION,
370 ODM_CMNINFO_BT_DIG,
371 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */
372 ODM_CMNINFO_BT_DISABLE_EDCA,
373 /* CALL BY VALUE-------------*/
374
375 /* Dynamic ptr array hook itms. */
376 ODM_CMNINFO_STA_STATUS,
377 ODM_CMNINFO_PHY_STATUS,
378 ODM_CMNINFO_MAC_STATUS,
379 ODM_CMNINFO_MAX,
380 };
381
382 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */
383
384 enum odm_ability_def {
385 /* BB ODM section BIT 0-15 */
386 ODM_BB_DIG = BIT(0),
387 ODM_BB_RA_MASK = BIT(1),
388 ODM_BB_DYNAMIC_TXPWR = BIT(2),
389 ODM_BB_FA_CNT = BIT(3),
390 ODM_BB_RSSI_MONITOR = BIT(4),
391 ODM_BB_CCK_PD = BIT(5),
392 ODM_BB_ANT_DIV = BIT(6),
393 ODM_BB_PWR_SAVE = BIT(7),
394 ODM_BB_PWR_TRA = BIT(8),
395 ODM_BB_RATE_ADAPTIVE = BIT(9),
396 ODM_BB_PATH_DIV = BIT(10),
397 ODM_BB_PSD = BIT(11),
398 ODM_BB_RXHP = BIT(12),
399
400 /* MAC DM section BIT 16-23 */
401 ODM_MAC_EDCA_TURBO = BIT(16),
402 ODM_MAC_EARLY_MODE = BIT(17),
403
404 /* RF ODM section BIT 24-31 */
405 ODM_RF_TX_PWR_TRACK = BIT(24),
406 ODM_RF_RX_GAIN_TRACK = BIT(25),
407 ODM_RF_CALIBRATION = BIT(26),
408 };
409
410 #define ODM_RTL8188E BIT(4)
411
412 /* ODM_CMNINFO_CUT_VER */
413 enum odm_cut_version {
414 ODM_CUT_A = 1,
415 ODM_CUT_B = 2,
416 ODM_CUT_C = 3,
417 ODM_CUT_D = 4,
418 ODM_CUT_E = 5,
419 ODM_CUT_F = 6,
420 ODM_CUT_TEST = 7,
421 };
422
423 /* ODM_CMNINFO_RF_TYPE */
424 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
425 enum odm_rf_path {
426 ODM_RF_TX_A = BIT(0),
427 ODM_RF_TX_B = BIT(1),
428 ODM_RF_TX_C = BIT(2),
429 ODM_RF_TX_D = BIT(3),
430 ODM_RF_RX_A = BIT(4),
431 ODM_RF_RX_B = BIT(5),
432 ODM_RF_RX_C = BIT(6),
433 ODM_RF_RX_D = BIT(7),
434 };
435
436 enum odm_rf_type {
437 ODM_1T1R = 0,
438 ODM_1T2R = 1,
439 ODM_2T2R = 2,
440 ODM_2T3R = 3,
441 ODM_2T4R = 4,
442 ODM_3T3R = 5,
443 ODM_3T4R = 6,
444 ODM_4T4R = 7,
445 };
446
447 /* ODM Dynamic common info value definition */
448
449 enum odm_mac_phy_mode {
450 ODM_SMSP = 0,
451 ODM_DMSP = 1,
452 ODM_DMDP = 2,
453 };
454
455 enum odm_bt_coexist {
456 ODM_BT_BUSY = 1,
457 ODM_BT_ON = 2,
458 ODM_BT_OFF = 3,
459 ODM_BT_NONE = 4,
460 };
461
462 /* ODM_CMNINFO_OP_MODE */
463 enum odm_operation_mode {
464 ODM_NO_LINK = BIT(0),
465 ODM_LINK = BIT(1),
466 ODM_SCAN = BIT(2),
467 ODM_POWERSAVE = BIT(3),
468 ODM_AP_MODE = BIT(4),
469 ODM_CLIENT_MODE = BIT(5),
470 ODM_AD_HOC = BIT(6),
471 ODM_WIFI_DIRECT = BIT(7),
472 ODM_WIFI_DISPLAY = BIT(8),
473 };
474
475 /* ODM_CMNINFO_WM_MODE */
476 enum odm_wireless_mode {
477 ODM_WM_UNKNOWN = 0x0,
478 ODM_WM_B = BIT(0),
479 ODM_WM_G = BIT(1),
480 ODM_WM_A = BIT(2),
481 ODM_WM_N24G = BIT(3),
482 ODM_WM_N5G = BIT(4),
483 ODM_WM_AUTO = BIT(5),
484 ODM_WM_AC = BIT(6),
485 };
486
487 /* ODM_CMNINFO_BAND */
488 enum odm_band_type {
489 ODM_BAND_2_4G = BIT(0),
490 ODM_BAND_5G = BIT(1),
491 };
492
493 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
494 enum odm_sec_chnl_offset {
495 ODM_DONT_CARE = 0,
496 ODM_BELOW = 1,
497 ODM_ABOVE = 2
498 };
499
500 /* ODM_CMNINFO_SEC_MODE */
501 enum odm_security {
502 ODM_SEC_OPEN = 0,
503 ODM_SEC_WEP40 = 1,
504 ODM_SEC_TKIP = 2,
505 ODM_SEC_RESERVE = 3,
506 ODM_SEC_AESCCMP = 4,
507 ODM_SEC_WEP104 = 5,
508 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
509 ODM_SEC_SMS4 = 7,
510 };
511
512 /* ODM_CMNINFO_BW */
513 enum odm_bw {
514 ODM_BW20M = 0,
515 ODM_BW40M = 1,
516 ODM_BW80M = 2,
517 ODM_BW160M = 3,
518 ODM_BW10M = 4,
519 };
520
521 /* ODM_CMNINFO_BOARD_TYPE */
522 enum odm_board_type {
523 ODM_BOARD_NORMAL = 0,
524 ODM_BOARD_HIGHPWR = 1,
525 ODM_BOARD_MINICARD = 2,
526 ODM_BOARD_SLIM = 3,
527 ODM_BOARD_COMBO = 4,
528 };
529
530 /* ODM_CMNINFO_ONE_PATH_CCA */
531 enum odm_cca_path {
532 ODM_CCA_2R = 0,
533 ODM_CCA_1R_A = 1,
534 ODM_CCA_1R_B = 2,
535 };
536
537 struct odm_ra_info {
538 u8 RateID;
539 u32 RateMask;
540 u32 RAUseRate;
541 u8 RateSGI;
542 u8 RssiStaRA;
543 u8 PreRssiStaRA;
544 u8 SGIEnable;
545 u8 DecisionRate;
546 u8 PreRate;
547 u8 HighestRate;
548 u8 LowestRate;
549 u32 NscUp;
550 u32 NscDown;
551 u16 RTY[5];
552 u32 TOTAL;
553 u16 DROP;
554 u8 Active;
555 u16 RptTime;
556 u8 RAWaitingCounter;
557 u8 RAPendingCounter;
558 u8 PTActive; /* on or off */
559 u8 PTTryState; /* 0 trying state, 1 for decision state */
560 u8 PTStage; /* 0~6 */
561 u8 PTStopCount; /* Stop PT counter */
562 u8 PTPreRate; /* if rate change do PT */
563 u8 PTPreRssi; /* if RSSI change 5% do PT */
564 u8 PTModeSS; /* decide whitch rate should do PT */
565 u8 RAstage; /* StageRA, decide how many times RA will be done
566 * between PT
567 */
568 u8 PTSmoothFactor;
569 };
570
571 struct ijk_matrix_regs_set {
572 bool bIQKDone;
573 s32 Value[1][IQK_Matrix_REG_NUM];
574 };
575
576 struct odm_rf_cal {
577 /* for tx power tracking */
578 u32 RegA24; /* for TempCCK */
579 s32 RegE94;
580 s32 RegE9C;
581 s32 RegEB4;
582 s32 RegEBC;
583
584 u8 TXPowercount;
585 bool bTXPowerTracking;
586 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
587 * as default
588 */
589 u8 TM_Trigger;
590 u8 InternalPA5G[2]; /* pathA / pathB */
591
592 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0,
593 * and 1 for RFIC1
594 */
595 u8 ThermalValue;
596 u8 ThermalValue_LCK;
597 u8 ThermalValue_IQK;
598 u8 ThermalValue_DPK;
599 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
600 u8 ThermalValue_AVG_index;
601 u8 ThermalValue_RxGain;
602 u8 ThermalValue_Crystal;
603 u8 ThermalValue_DPKstore;
604 u8 ThermalValue_DPKtrack;
605 bool TxPowerTrackingInProgress;
606 bool bDPKenable;
607
608 bool bReloadtxpowerindex;
609 u8 bRfPiEnable;
610 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
611
612 u8 bCCKinCH14;
613 u8 CCK_index;
614 u8 OFDM_index[2];
615 bool bDoneTxpower;
616
617 u8 ThermalValue_HP[HP_THERMAL_NUM];
618 u8 ThermalValue_HP_index;
619 struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
620
621 u8 Delta_IQK;
622 u8 Delta_LCK;
623
624 /* for IQK */
625 u32 RegC04;
626 u32 Reg874;
627 u32 RegC08;
628 u32 RegB68;
629 u32 RegB6C;
630 u32 Reg870;
631 u32 Reg860;
632 u32 Reg864;
633
634 bool bIQKInitialized;
635 bool bLCKInProgress;
636 bool bAntennaDetected;
637 u32 ADDA_backup[IQK_ADDA_REG_NUM];
638 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
639 u32 IQK_BB_backup_recover[9];
640 u32 IQK_BB_backup[IQK_BB_REG_NUM];
641
642 /* for APK */
643 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
644 u8 bAPKdone;
645 u8 bAPKThermalMeterIgnore;
646 u8 bDPdone;
647 u8 bDPPathAOK;
648 u8 bDPPathBOK;
649 };
650
651 /* ODM Dynamic common info value definition */
652
653 struct fast_ant_train {
654 u8 Bssid[6];
655 u8 antsel_rx_keep_0;
656 u8 antsel_rx_keep_1;
657 u8 antsel_rx_keep_2;
658 u32 antSumRSSI[7];
659 u32 antRSSIcnt[7];
660 u32 antAveRSSI[7];
661 u8 FAT_State;
662 u32 TrainIdx;
663 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
664 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
665 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
666 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
667 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
668 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
669 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
670 u8 RxIdleAnt;
671 bool bBecomeLinked;
672 };
673
674 enum fat_state {
675 FAT_NORMAL_STATE = 0,
676 FAT_TRAINING_STATE = 1,
677 };
678
679 enum ant_div_type {
680 NO_ANTDIV = 0xFF,
681 CG_TRX_HW_ANTDIV = 0x01,
682 CGCS_RX_HW_ANTDIV = 0x02,
683 FIXED_HW_ANTDIV = 0x03,
684 CG_TRX_SMART_ANTDIV = 0x04,
685 CGCS_RX_SW_ANTDIV = 0x05,
686 };
687
688 /* Copy from SD4 defined structure. We use to support PHY DM integration. */
689 struct odm_dm_struct {
690 /* Add for different team use temporarily */
691 struct adapter *Adapter; /* For CE/NIC team */
692 struct rtl8192cd_priv *priv; /* For AP/ADSL team */
693 /* WHen you use above pointers, they must be initialized. */
694 bool odm_ready;
695
696 struct rtl8192cd_priv *fake_priv;
697 u64 DebugComponents;
698 u32 DebugLevel;
699
700 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
701 bool bCckHighPower;
702 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
703 u8 ControlChannel;
704 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
705
706 /* 1 COMMON INFORMATION */
707 /* Init Value */
708 /* HOOK BEFORE REG INIT----------- */
709 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
710 u8 SupportPlatform;
711 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */
712 u32 SupportAbility;
713 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
714 u8 SupportInterface;
715 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
716 * other type = 1/2/3/...
717 */
718 u32 SupportICType;
719 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
720 u8 CutVersion;
721 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
722 u8 BoardType;
723 /* with external LNA NO/Yes = 0/1 */
724 u8 ExtLNA;
725 /* with external PA NO/Yes = 0/1 */
726 u8 ExtPA;
727 /* with external TRSW NO/Yes = 0/1 */
728 u8 ExtTRSW;
729 u8 PatchID; /* Customer ID */
730 bool bInHctTest;
731 bool bWIFITest;
732
733 bool bDualMacSmartConcurrent;
734 u32 BK_SupportAbility;
735 u8 AntDivType;
736 /* HOOK BEFORE REG INIT----------- */
737
738 /* Dynamic Value */
739 /* POINTER REFERENCE----------- */
740
741 u8 u8_temp;
742 bool bool_temp;
743 struct adapter *adapter_temp;
744
745 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
746 u8 *pMacPhyMode;
747 /* TX Unicast byte count */
748 u64 *pNumTxBytesUnicast;
749 /* RX Unicast byte count */
750 u64 *pNumRxBytesUnicast;
751 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
752 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */
753 /* Frequence band 2.4G/5G = 0/1 */
754 u8 *pBandType;
755 /* Secondary channel offset don't_care/below/above = 0/1/2 */
756 u8 *pSecChOffset;
757 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
758 u8 *pSecurity;
759 /* BW info 20M/40M/80M = 0/1/2 */
760 u8 *pBandWidth;
761 /* Central channel location Ch1/Ch2/.... */
762 u8 *pChannel; /* central channel number */
763 /* Common info for 92D DMSP */
764
765 bool *pbGetValueFromOtherMac;
766 struct adapter **pBuddyAdapter;
767 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
768 /* Common info for Status */
769 bool *pbScanInProcess;
770 bool *pbPowerSaving;
771 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
772 u8 *pOnePathCCA;
773 /* pMgntInfo->AntennaTest */
774 u8 *pAntennaTest;
775 bool *pbNet_closed;
776 /* POINTER REFERENCE----------- */
777 /* */
778 /* CALL BY VALUE------------- */
779 bool bWIFI_Direct;
780 bool bWIFI_Display;
781 bool bLinked;
782 u8 RSSI_Min;
783 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
784 bool bIsMPChip;
785 bool bOneEntryOnly;
786 /* Common info for BTDM */
787 bool bBtDisabled; /* BT is disabled */
788 bool bBtHsOperation; /* BT HS mode is under progress */
789 u8 btHsDigVal; /* use BT rssi to decide the DIG value */
790 bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the
791 * EDCA Turbo
792 */
793 bool bBtBusy; /* BT is busy. */
794 /* CALL BY VALUE------------- */
795
796 /* 2 Define STA info. */
797 /* _ODM_STA_INFO */
798 /* For MP, we need to reduce one array pointer for default port.??*/
799 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
800
801 u16 CurrminRptTime;
802 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
803 * array index. STA MacID=0,
804 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1}
805 */
806 /* */
807 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
808 /* We need to colelct all support abilit to a proper area. */
809 /* */
810 bool RaSupport88E;
811
812 /* Define ........... */
813
814 /* Latest packet phy info (ODM write) */
815 struct odm_phy_dbg_info PhyDbgInfo;
816
817 /* Latest packet phy info (ODM write) */
818 struct odm_mac_status_info *pMacInfo;
819
820 /* Different Team independt structure?? */
821
822 /* ODM Structure */
823 struct fast_ant_train DM_FatTable;
824 struct rtw_dig DM_DigTable;
825 struct rtl_ps DM_PSTable;
826 struct rx_hpc DM_RXHP_Table;
827 struct false_alarm_stats FalseAlmCnt;
828 struct false_alarm_stats FlaseAlmCntBuddyAdapter;
829 struct sw_ant_switch DM_SWAT_Table;
830 bool RSSI_test;
831
832 struct edca_turbo DM_EDCA_Table;
833 u32 WMMEDCA_BE;
834 /* Copy from SD4 structure */
835 /* */
836 /* ================================================== */
837 /* */
838
839 bool *pbDriverStopped;
840 bool *pbDriverIsGoingToPnpSetPowerSleep;
841 bool *pinit_adpt_in_progress;
842
843 /* PSD */
844 bool bUserAssignLevel;
845 struct timer_list PSDTimer;
846 u8 RSSI_BT; /* come from BT */
847 bool bPSDinProcess;
848 bool bDMInitialGainEnable;
849
850 /* for rate adaptive, in fact, 88c/92c fw will handle this */
851 u8 bUseRAMask;
852
853 struct odm_rate_adapt RateAdaptive;
854
855 struct odm_rf_cal RFCalibrateInfo;
856
857 /* TX power tracking */
858 u8 BbSwingIdxOfdm;
859 u8 BbSwingIdxOfdmCurrent;
860 u8 BbSwingIdxOfdmBase;
861 bool BbSwingFlagOfdm;
862 u8 BbSwingIdxCck;
863 u8 BbSwingIdxCckCurrent;
864 u8 BbSwingIdxCckBase;
865 bool BbSwingFlagCck;
866 u8 *mp_mode;
867 /* ODM system resource. */
868
869 /* ODM relative time. */
870 struct timer_list PathDivSwitchTimer;
871 /* 2011.09.27 add for Path Diversity */
872 struct timer_list CCKPathDiversityTimer;
873 struct timer_list FastAntTrainingTimer;
874 }; /* DM_Dynamic_Mechanism_Structure */
875
876 #define ODM_RF_PATH_MAX 3
877
878 enum ODM_RF_CONTENT {
879 odm_radioa_txt = 0x1000,
880 odm_radiob_txt = 0x1001,
881 odm_radioc_txt = 0x1002,
882 odm_radiod_txt = 0x1003
883 };
884
885 /* Status code */
886 enum rt_status {
887 RT_STATUS_SUCCESS,
888 RT_STATUS_FAILURE,
889 RT_STATUS_PENDING,
890 RT_STATUS_RESOURCE,
891 RT_STATUS_INVALID_CONTEXT,
892 RT_STATUS_INVALID_PARAMETER,
893 RT_STATUS_NOT_SUPPORT,
894 RT_STATUS_OS_API_FAILED,
895 };
896
897 /* 3=========================================================== */
898 /* 3 DIG */
899 /* 3=========================================================== */
900
901 enum dm_dig_op {
902 RT_TYPE_THRESH_HIGH = 0,
903 RT_TYPE_THRESH_LOW = 1,
904 RT_TYPE_BACKOFF = 2,
905 RT_TYPE_RX_GAIN_MIN = 3,
906 RT_TYPE_RX_GAIN_MAX = 4,
907 RT_TYPE_ENABLE = 5,
908 RT_TYPE_DISABLE = 6,
909 DIG_OP_TYPE_MAX
910 };
911
912 #define DM_DIG_THRESH_HIGH 40
913 #define DM_DIG_THRESH_LOW 35
914
915 #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */
916
917
918 #define DM_false_ALARM_THRESH_LOW 400
919 #define DM_false_ALARM_THRESH_HIGH 1000
920
921 #define DM_DIG_MAX_NIC 0x4e
922 #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */
923
924 #define DM_DIG_MAX_AP 0x32
925 #define DM_DIG_MIN_AP 0x20
926
927 #define DM_DIG_MAX_NIC_HP 0x46
928 #define DM_DIG_MIN_NIC_HP 0x2e
929
930 #define DM_DIG_MAX_AP_HP 0x42
931 #define DM_DIG_MIN_AP_HP 0x30
932
933 /* vivi 92c&92d has different definition, 20110504 */
934 /* this is for 92c */
935 #define DM_DIG_FA_TH0 0x200/* 0x20 */
936 #define DM_DIG_FA_TH1 0x300/* 0x100 */
937 #define DM_DIG_FA_TH2 0x400/* 0x200 */
938 /* this is for 92d */
939 #define DM_DIG_FA_TH0_92D 0x100
940 #define DM_DIG_FA_TH1_92D 0x400
941 #define DM_DIG_FA_TH2_92D 0x600
942
943 #define DM_DIG_BACKOFF_MAX 12
944 #define DM_DIG_BACKOFF_MIN -4
945 #define DM_DIG_BACKOFF_DEFAULT 10
946
947 /* 3=========================================================== */
948 /* 3 AGC RX High Power Mode */
949 /* 3=========================================================== */
950 #define LNA_Low_Gain_1 0x64
951 #define LNA_Low_Gain_2 0x5A
952 #define LNA_Low_Gain_3 0x58
953
954 #define FA_RXHP_TH1 5000
955 #define FA_RXHP_TH2 1500
956 #define FA_RXHP_TH3 800
957 #define FA_RXHP_TH4 600
958 #define FA_RXHP_TH5 500
959
960 /* 3=========================================================== */
961 /* 3 EDCA */
962 /* 3=========================================================== */
963
964 /* 3=========================================================== */
965 /* 3 Dynamic Tx Power */
966 /* 3=========================================================== */
967 /* Dynamic Tx Power Control Threshold */
968 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
969 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
970 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
971
972 #define TxHighPwrLevel_Normal 0
973 #define TxHighPwrLevel_Level1 1
974 #define TxHighPwrLevel_Level2 2
975 #define TxHighPwrLevel_BT1 3
976 #define TxHighPwrLevel_BT2 4
977 #define TxHighPwrLevel_15 5
978 #define TxHighPwrLevel_35 6
979 #define TxHighPwrLevel_50 7
980 #define TxHighPwrLevel_70 8
981 #define TxHighPwrLevel_100 9
982
983 /* 3=========================================================== */
984 /* 3 Rate Adaptive */
985 /* 3=========================================================== */
986 #define DM_RATR_STA_INIT 0
987 #define DM_RATR_STA_HIGH 1
988 #define DM_RATR_STA_MIDDLE 2
989 #define DM_RATR_STA_LOW 3
990
991 /* 3=========================================================== */
992 /* 3 BB Power Save */
993 /* 3=========================================================== */
994
995
996 enum dm_1r_cca {
997 CCA_1R = 0,
998 CCA_2R = 1,
999 CCA_MAX = 2,
1000 };
1001
1002 enum dm_rf {
1003 RF_Save = 0,
1004 RF_Normal = 1,
1005 RF_MAX = 2,
1006 };
1007
1008 /* 3=========================================================== */
1009 /* 3 Antenna Diversity */
1010 /* 3=========================================================== */
1011 enum dm_swas {
1012 Antenna_A = 1,
1013 Antenna_B = 2,
1014 Antenna_MAX = 3,
1015 };
1016
1017 /* Maximal number of antenna detection mechanism needs to perform. */
1018 #define MAX_ANTENNA_DETECTION_CNT 10
1019
1020 /* Extern Global Variables. */
1021 #define OFDM_TABLE_SIZE_92C 37
1022 #define OFDM_TABLE_SIZE_92D 43
1023 #define CCK_TABLE_SIZE 33
1024
1025 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1026 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1027 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1028
1029 /* check Sta pointer valid or not */
1030 #define IS_STA_VALID(pSta) (pSta)
1031 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1032 /* This indicates two different the steps. */
1033 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1034 * signal on the air.
1035 */
1036 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1037 * SWAW_STEP_PEAK
1038 */
1039 /* with original RSSI to determine if it is necessary to switch antenna. */
1040 #define SWAW_STEP_PEAK 0
1041 #define SWAW_STEP_DETERMINE 1
1042
1043 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1044 #define dm_RF_Saving ODM_RF_Saving
1045
1046 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1047 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1048 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1049 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1050 bool bForceUpdate, u8 *pRATRState);
1051 u32 ConvertTo_dB(u32 Value);
1052 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1053 u32 ra_mask, u8 rssi_level);
1054 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1055 enum odm_common_info_def CmnInfo, u32 Value);
1056 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1057 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1058 enum odm_common_info_def CmnInfo, void *pValue);
1059 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1060 enum odm_common_info_def CmnInfo,
1061 u16 Index, void *pValue);
1062 void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1063 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1064 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);
1065
1066 #endif