1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7 #ifndef __INC_HAL8188EPHYCFG_H__
8 #define __INC_HAL8188EPHYCFG_H__
9
10
11 /*--------------------------Define Parameters-------------------------------*/
12 #define LOOP_LIMIT 5
13 #define MAX_STALL_TIME 50 /* us */
14 #define AntennaDiversityValue 0x80
15 #define MAX_TXPWR_IDX_NMODE_92S 63
16 #define Reset_Cnt_Limit 3
17
18 #define IQK_MAC_REG_NUM 4
19 #define IQK_ADDA_REG_NUM 16
20 #define IQK_BB_REG_NUM 9
21 #define HP_THERMAL_NUM 8
22
23 #define MAX_AGGR_NUM 0x07
24
25
26 /*--------------------------Define Parameters-------------------------------*/
27
28
29 /*------------------------------Define structure----------------------------*/
30 enum sw_chnl_cmd_id {
31 CmdID_End,
32 CmdID_SetTxPowerLevel,
33 CmdID_BBRegWrite10,
34 CmdID_WritePortUlong,
35 CmdID_WritePortUshort,
36 CmdID_WritePortUchar,
37 CmdID_RF_WriteReg,
38 };
39
40 /* 1. Switch channel related */
41 struct sw_chnl_cmd {
42 enum sw_chnl_cmd_id CmdID;
43 u32 Para1;
44 u32 Para2;
45 u32 msDelay;
46 };
47
48 enum hw90_block {
49 HW90_BLOCK_MAC = 0,
50 HW90_BLOCK_PHY0 = 1,
51 HW90_BLOCK_PHY1 = 2,
52 HW90_BLOCK_RF = 3,
53 HW90_BLOCK_MAXIMUM = 4, /* Never use this */
54 };
55
56 enum rf_radio_path {
57 RF_PATH_A = 0, /* Radio Path A */
58 RF_PATH_B = 1, /* Radio Path B */
59 };
60
61 #define MAX_PG_GROUP 13
62
63 #define RF_PATH_MAX 2
64 #define MAX_RF_PATH RF_PATH_MAX
65 #define MAX_TX_COUNT 4 /* path numbers */
66
67 #define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */
68 #define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,
69 *ch9~11, ch12~13, CH 14
70 * total three groups
71 */
72 #define CHANNEL_GROUP_MAX_88E 6
73
74 enum wireless_mode {
75 WIRELESS_MODE_UNKNOWN = 0x00,
76 WIRELESS_MODE_A = BIT(2),
77 WIRELESS_MODE_B = BIT(0),
78 WIRELESS_MODE_G = BIT(1),
79 WIRELESS_MODE_AUTO = BIT(5),
80 WIRELESS_MODE_N_24G = BIT(3),
81 WIRELESS_MODE_N_5G = BIT(4),
82 WIRELESS_MODE_AC = BIT(6)
83 };
84
85 enum phy_rate_tx_offset_area {
86 RA_OFFSET_LEGACY_OFDM1,
87 RA_OFFSET_LEGACY_OFDM2,
88 RA_OFFSET_HT_OFDM1,
89 RA_OFFSET_HT_OFDM2,
90 RA_OFFSET_HT_OFDM3,
91 RA_OFFSET_HT_OFDM4,
92 RA_OFFSET_HT_CCK,
93 };
94
95 struct bb_reg_def {
96 u32 rfintfs; /* set software control: */
97 /* 0x870~0x877[8 bytes] */
98 u32 rfintfi; /* readback data: */
99 /* 0x8e0~0x8e7[8 bytes] */
100 u32 rfintfo; /* output data: */
101 /* 0x860~0x86f [16 bytes] */
102 u32 rfintfe; /* output enable: */
103 /* 0x860~0x86f [16 bytes] */
104 u32 rf3wireOffset; /* LSSI data: */
105 /* 0x840~0x84f [16 bytes] */
106 u32 rfLSSI_Select; /* BB Band Select: */
107 /* 0x878~0x87f [8 bytes] */
108 u32 rfTxGainStage; /* Tx gain stage: */
109 /* 0x80c~0x80f [4 bytes] */
110 u32 rfHSSIPara1; /* wire parameter control1 : */
111 /* 0x820~0x823,0x828~0x82b,
112 * 0x830~0x833, 0x838~0x83b [16 bytes]
113 */
114 u32 rfHSSIPara2; /* wire parameter control2 : */
115 /* 0x824~0x827,0x82c~0x82f, 0x834~0x837,
116 * 0x83c~0x83f [16 bytes]
117 */
118 u32 rfSwitchControl; /* Tx Rx antenna control : */
119 /* 0x858~0x85f [16 bytes] */
120 u32 rfAGCControl1; /* AGC parameter control1 : */
121 /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
122 * 0xc68~0xc6b [16 bytes]
123 */
124 u32 rfAGCControl2; /* AGC parameter control2 : */
125 /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
126 * 0xc6c~0xc6f [16 bytes]
127 */
128 u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
129 /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
130 * 0xc2c~0xc2f [16 bytes]
131 */
132 u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter,
133 * Rx DC notch filter :
134 */
135 /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
136 * 0xc28~0xc2b [16 bytes]
137 */
138 u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
139 /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
140 * 0xc98~0xc9b [16 bytes]
141 */
142 u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
143 /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
144 * 0xc9c~0xc9f [16 bytes]
145 */
146 u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
147 /* 0x8a0~0x8af [16 bytes] */
148 u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for
149 * Path A and B
150 */
151 };
152
153 /*------------------------------Define structure----------------------------*/
154
155
156 /*------------------------Export global variable----------------------------*/
157 /*------------------------Export global variable----------------------------*/
158
159
160 /*------------------------Export Marco Definition---------------------------*/
161 /*------------------------Export Marco Definition---------------------------*/
162
163
164 /*--------------------------Exported Function prototype---------------------*/
165 /* */
166 /* BB and RF register read/write */
167 /* */
168
169 /* Read initi reg value for tx power setting. */
170 void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);
171
172 /* BB TX Power R/W */
173 void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel);
174
175 void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
176
177 /* Call after initialization */
178 void ChkFwCmdIoDone(struct adapter *adapter);
179
180 /* BB/MAC/RF other monitor API */
181 void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main);
182
183 void PHY_SwitchEphyParameter(struct adapter *adapter);
184
185 void PHY_EnableHostClkReq(struct adapter *adapter);
186
187 bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);
188
189 /*--------------------------Exported Function prototype---------------------*/
190
191 #define PHY_SetMacReg PHY_SetBBReg
192
193 #define SIC_HW_SUPPORT 0
194
195 #define SIC_MAX_POLL_CNT 5
196
197 #define SIC_CMD_READY 0
198 #define SIC_CMD_WRITE 1
199 #define SIC_CMD_READ 2
200
201 #define SIC_CMD_REG 0x1EB /* 1byte */
202 #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
203 #define SIC_DATA_REG 0x1EC /* 1bc~1bf */
204
205 #endif /* __INC_HAL8192CPHYCFG_H */