drivers/staging/rtl8188eu/include/rtw

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #ifndef __RTW_PWRCTRL_H_
   8 #define __RTW_PWRCTRL_H_
   9 
  10 #include <osdep_service.h>
  11 #include <drv_types.h>
  12 
  13 #define FW_PWR0         0
  14 #define FW_PWR1         1
  15 #define FW_PWR2         2
  16 #define FW_PWR3         3
  17 #define HW_PWR0         7
  18 #define HW_PWR1         6
  19 #define HW_PWR2         2
  20 #define HW_PWR3         0
  21 #define HW_PWR4         8
  22 
  23 #define FW_PWRMSK       0x7
  24 
  25 #define XMIT_ALIVE      BIT(0)
  26 #define RECV_ALIVE      BIT(1)
  27 #define CMD_ALIVE       BIT(2)
  28 #define EVT_ALIVE       BIT(3)
  29 
  30 enum power_mgnt {
  31         PS_MODE_ACTIVE = 0,
  32         PS_MODE_MIN,
  33         PS_MODE_MAX,
  34         PS_MODE_DTIM,
  35         PS_MODE_VOIP,
  36         PS_MODE_UAPSD_WMM,
  37         PS_MODE_UAPSD,
  38         PS_MODE_IBSS,
  39         PS_MODE_WWLAN,
  40         PM_Radio_Off,
  41         PM_Card_Disable,
  42         PS_MODE_NUM
  43 };
  44 
  45 /*
  46  *      BIT[2:0] = HW state
  47  *      BIT[3] = Protocol PS state,   0: register active state,
  48  *                                    1: register sleep state
  49  *      BIT[4] = sub-state
  50  */
  51 
  52 #define PS_DPS                  BIT(0)
  53 #define PS_LCLK                 (PS_DPS)
  54 #define PS_RF_OFF               BIT(1)
  55 #define PS_ALL_ON               BIT(2)
  56 #define PS_ST_ACTIVE            BIT(3)
  57 
  58 #define PS_ISR_ENABLE           BIT(4)
  59 #define PS_IMR_ENABLE           BIT(5)
  60 #define PS_ACK                  BIT(6)
  61 #define PS_TOGGLE               BIT(7)
  62 
  63 #define PS_STATE_MASK           (0x0F)
  64 #define PS_STATE_HW_MASK        (0x07)
  65 #define PS_SEQ_MASK             (0xc0)
  66 
  67 #define PS_STATE(x)             (PS_STATE_MASK & (x))
  68 #define PS_STATE_HW(x)          (PS_STATE_HW_MASK & (x))
  69 #define PS_SEQ(x)               (PS_SEQ_MASK & (x))
  70 
  71 #define PS_STATE_S0             (PS_DPS)
  72 #define PS_STATE_S1             (PS_LCLK)
  73 #define PS_STATE_S2             (PS_RF_OFF)
  74 #define PS_STATE_S3             (PS_ALL_ON)
  75 #define PS_STATE_S4             ((PS_ST_ACTIVE) | (PS_ALL_ON))
  76 
  77 #define PS_IS_RF_ON(x)  ((x) & (PS_ALL_ON))
  78 #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
  79 #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
  80 
  81 struct reportpwrstate_parm {
  82         unsigned char mode;
  83         unsigned char state; /* the CPWM value */
  84         unsigned short rsvd;
  85 };
  86 
  87 #define LPS_DELAY_TIME  1*HZ /*  1 sec */
  88 
  89 #define EXE_PWR_NONE    0x01
  90 #define EXE_PWR_IPS             0x02
  91 #define EXE_PWR_LPS             0x04
  92 
  93 /*  RF state. */
  94 enum rt_rf_power_state {
  95         rf_on,          /*  RF is on after RFSleep or RFOff */
  96         rf_sleep,       /*  802.11 Power Save mode */
  97         rf_off,         /*  HW/SW Radio OFF or Inactive Power Save */
  98         /* Add the new RF state above this line===== */
  99         rf_max
 100 };
 101 
 102 /*  RF Off Level for IPS or HW/SW radio off */
 103 #define RT_RF_OFF_LEVL_ASPM             BIT(0)  /* PCI ASPM */
 104 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /* PCI clock request */
 105 #define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /* PCI D3 mode */
 106 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)  /* NIC halt, re-init hw param*/
 107 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /* FW free, re-download the FW*/
 108 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /* FW in 32k */
 109 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)  /* Always enable ASPM and Clock
 110                                                  * Req in initialization.
 111                                                  */
 112 #define RT_RF_LPS_DISALBE_2R            BIT(30) /* When LPS is on, disable 2R
 113                                                  * if no packet is RX or TX.
 114                                                  */
 115 #define RT_RF_LPS_LEVEL_ASPM            BIT(31) /* LPS with ASPM */
 116 
 117 #define RT_IN_PS_LEVEL(ppsc, _PS_FLAG)                          \
 118         ((ppsc->cur_ps_level & _PS_FLAG) ? true : false)
 119 #define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG)                       \
 120         (ppsc->cur_ps_level &= (~(_PS_FLAG)))
 121 #define RT_SET_PS_LEVEL(ppsc, _PS_FLAG)                         \
 122         (ppsc->cur_ps_level |= _PS_FLAG)
 123 
 124 enum _PS_BBRegBackup_ {
 125         PSBBREG_RF0 = 0,
 126         PSBBREG_RF1,
 127         PSBBREG_RF2,
 128         PSBBREG_AFE0,
 129         PSBBREG_TOTALCNT
 130 };
 131 
 132 enum { /*  for ips_mode */
 133         IPS_NONE = 0,
 134         IPS_NORMAL,
 135         IPS_LEVEL_2,
 136 };
 137 
 138 struct pwrctrl_priv {
 139         struct mutex mutex_lock;
 140         volatile u8 rpwm; /*  requested power state for fw */
 141         volatile u8 cpwm; /*  fw current power state. updated when
 142                            * 1. read from HCPWM 2. driver lowers power level
 143                            */
 144         volatile u8 tog; /*  toggling */
 145         volatile u8 cpwm_tog; /*  toggling */
 146 
 147         u8      pwr_mode;
 148         u8      smart_ps;
 149         u8      bcn_ant_mode;
 150 
 151         u32     alives;
 152         struct work_struct cpwm_event;
 153         u8      bpower_saving;
 154 
 155         u8      b_hw_radio_off;
 156         u8      reg_rfoff;
 157         u8      reg_pdnmode; /* powerdown mode */
 158         u32     rfoff_reason;
 159 
 160         /* RF OFF Level */
 161         u32     cur_ps_level;
 162         u32     reg_rfps_level;
 163         uint    ips_enter_cnts;
 164         uint    ips_leave_cnts;
 165 
 166         u8      ips_mode;
 167         u8      ips_mode_req;   /*  used to accept the mode setting request,
 168                                  *  will update to ipsmode later
 169                                  */
 170         uint bips_processing;
 171         unsigned long ips_deny_time; /* will deny IPS when system time less than this */
 172         u8 ps_processing; /* temp used to mark whether in rtw_ps_processor */
 173 
 174         u8      bLeisurePs;
 175         u8      LpsIdleCount;
 176         u8      power_mgnt;
 177         u8      bFwCurrentInPSMode;
 178         u32     DelayLPSLastTimeStamp;
 179         u8      btcoex_rfon;
 180         s32             pnp_current_pwr_state;
 181         u8              pnp_bstop_trx;
 182 
 183         u8              bInternalAutoSuspend;
 184         u8              bInSuspend;
 185         u8              bSupportRemoteWakeup;
 186         struct timer_list pwr_state_check_timer;
 187         int             pwr_state_check_interval;
 188         u8              pwr_state_check_cnts;
 189 
 190         int             ps_flag;
 191 
 192         enum rt_rf_power_state  rf_pwrstate;/* cur power state */
 193         enum rt_rf_power_state  change_rfpwrstate;
 194 
 195         u8              wepkeymask;
 196         u8              bHWPowerdown;/* if support hw power down */
 197         u8              bHWPwrPindetect;
 198         u8              bkeepfwalive;
 199         u8              brfoffbyhw;
 200         unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
 201 };
 202 
 203 #define rtw_get_ips_mode_req(pwrctrlpriv) \
 204         (pwrctrlpriv)->ips_mode_req
 205 
 206 #define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \
 207         ((pwrctrlpriv)->ips_mode_req = (ips_mode))
 208 
 209 #define RTW_PWR_STATE_CHK_INTERVAL 2000
 210 
 211 #define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
 212         mod_timer(&pwrctrlpriv->pwr_state_check_timer,  \
 213                   jiffies + msecs_to_jiffies(ms))
 214 
 215 #define rtw_set_pwr_state_check_timer(pwrctrl)                  \
 216         _rtw_set_pwr_state_check_timer((pwrctrl),               \
 217                                        (pwrctrl)->pwr_state_check_interval)
 218 
 219 void rtw_init_pwrctrl_priv(struct adapter *adapter);
 220 
 221 void rtw_set_ps_mode(struct adapter *adapter, u8 ps_mode, u8 smart_ps,
 222                      u8 bcn_ant_mode);
 223 void rtw_set_rpwm(struct adapter *adapter, u8 val8);
 224 void LeaveAllPowerSaveMode(struct adapter *adapter);
 225 void ips_enter(struct adapter *padapter);
 226 int ips_leave(struct adapter *padapter);
 227 
 228 void rtw_ps_processor(struct adapter *padapter);
 229 
 230 enum rt_rf_power_state RfOnOffDetect(struct adapter *iadapter);
 231 
 232 s32 LPS_RF_ON_check(struct adapter *adapter, u32 delay_ms);
 233 void LPS_Enter(struct adapter *adapter);
 234 void LPS_Leave(struct adapter *adapter);
 235 
 236 int _rtw_pwr_wakeup(struct adapter *adapter, u32 ips_defer_ms,
 237                     const char *caller);
 238 #define rtw_pwr_wakeup(adapter)                                         \
 239          _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __func__)
 240 #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms)                       \
 241          _rtw_pwr_wakeup(adapter, ips_deffer_ms, __func__)
 242 int rtw_pm_set_ips(struct adapter *adapter, u8 mode);
 243 int rtw_pm_set_lps(struct adapter *adapter, u8 mode);
 244 
 245 #endif  /* __RTL871X_PWRCTRL_H_ */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/staging/rtl8188eu/include/rtw_pwrctrl.h

INCLUDED FROM
