root/drivers/staging/rtl8188eu/include/rtl8188e_spec.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  *******************************************************************************/
   7 #ifndef __RTL8188E_SPEC_H__
   8 #define __RTL8188E_SPEC_H__
   9 
  10 /*        8192C Register offset definition */
  11 
  12 #define         HAL_PS_TIMER_INT_DELAY  50      /*   50 microseconds */
  13 #define         HAL_92C_NAV_UPPER_UNIT  128     /*  micro-second */
  14 
  15 #define MAC_ADDR_LEN                    6
  16 /*  8188E PKT_BUFF_ACCESS_CTRL value */
  17 #define TXPKT_BUF_SELECT                0x69
  18 #define RXPKT_BUF_SELECT                0xA5
  19 #define DISABLE_TRXPKT_BUF_ACCESS       0x0
  20 
  21 
  22 /*      0x0000h ~ 0x00FFh       System Configuration */
  23 #define REG_SYS_ISO_CTRL                0x0000
  24 #define REG_SYS_FUNC_EN                 0x0002
  25 #define REG_APS_FSMCO                   0x0004
  26 #define REG_SYS_CLKR                    0x0008
  27 #define REG_9346CR                      0x000A
  28 #define REG_EE_VPD                      0x000C
  29 #define REG_AFE_MISC                    0x0010
  30 #define REG_SPS0_CTRL                   0x0011
  31 #define REG_SPS_OCP_CFG                 0x0018
  32 #define REG_RSV_CTRL                    0x001C
  33 #define REG_RF_CTRL                     0x001F
  34 #define REG_LDOA15_CTRL                 0x0020
  35 #define REG_LDOV12D_CTRL                0x0021
  36 #define REG_LDOHCI12_CTRL               0x0022
  37 #define REG_LPLDO_CTRL                  0x0023
  38 #define REG_AFE_XTAL_CTRL               0x0024
  39 #define REG_AFE_PLL_CTRL                0x0028
  40 #define REG_APE_PLL_CTRL_EXT            0x002c
  41 #define REG_EFUSE_CTRL                  0x0030
  42 #define REG_EFUSE_TEST                  0x0034
  43 #define REG_GPIO_MUXCFG                 0x0040
  44 #define REG_GPIO_IO_SEL                 0x0042
  45 #define REG_MAC_PINMUX_CFG              0x0043
  46 #define REG_GPIO_PIN_CTRL               0x0044
  47 #define REG_GPIO_INTM                   0x0048
  48 #define REG_LEDCFG0                     0x004C
  49 #define REG_LEDCFG1                     0x004D
  50 #define REG_LEDCFG2                     0x004E
  51 #define REG_LEDCFG3                     0x004F
  52 #define REG_FSIMR                       0x0050
  53 #define REG_FSISR                       0x0054
  54 #define REG_HSIMR                       0x0058
  55 #define REG_HSISR                       0x005c
  56 #define REG_GPIO_PIN_CTRL_2             0x0060 /*  RTL8723 WIFI/BT/GPS
  57                                                 * Multi-Function GPIO Pin Control.
  58                                                 */
  59 #define REG_GPIO_IO_SEL_2               0x0062 /*  RTL8723 WIFI/BT/GPS
  60                                                 * Multi-Function GPIO Select.
  61                                                 */
  62 #define REG_BB_PAD_CTRL                 0x0064
  63 #define REG_MULTI_FUNC_CTRL             0x0068 /*  RTL8723 WIFI/BT/GPS
  64                                                 * Multi-Function control source.
  65                                                 */
  66 #define REG_GPIO_OUTPUT                 0x006c
  67 #define REG_AFE_XTAL_CTRL_EXT           0x0078 /* RTL8188E */
  68 #define REG_XCK_OUT_CTRL                0x007c /* RTL8188E */
  69 #define REG_MCUFWDL                     0x0080
  70 #define REG_WOL_EVENT                   0x0081 /* RTL8188E */
  71 #define REG_MCUTSTCFG                   0x0084
  72 #define REG_HMEBOX_E0                   0x0088
  73 #define REG_HMEBOX_E1                   0x008A
  74 #define REG_HMEBOX_E2                   0x008C
  75 #define REG_HMEBOX_E3                   0x008E
  76 #define REG_HMEBOX_EXT_0                0x01F0
  77 #define REG_HMEBOX_EXT_1                0x01F4
  78 #define REG_HMEBOX_EXT_2                0x01F8
  79 #define REG_HMEBOX_EXT_3                0x01FC
  80 #define REG_HIMR_88E                    0x00B0
  81 #define REG_HISR_88E                    0x00B4
  82 #define REG_HIMRE_88E                   0x00B8
  83 #define REG_HISRE_88E                   0x00BC
  84 #define REG_EFUSE_ACCESS                0x00CF  /*  Efuse access protection
  85                                                  * for RTL8723
  86                                                  */
  87 #define REG_BIST_SCAN                   0x00D0
  88 #define REG_BIST_RPT                    0x00D4
  89 #define REG_BIST_ROM_RPT                0x00D8
  90 #define REG_USB_SIE_INTF                0x00E0
  91 #define REG_PCIE_MIO_INTF               0x00E4
  92 #define REG_PCIE_MIO_INTD               0x00E8
  93 #define REG_HPON_FSM                    0x00EC
  94 #define REG_SYS_CFG                     0x00F0
  95 #define REG_GPIO_OUTSTS                 0x00F4  /*  For RTL8723 only. */
  96 #define REG_TYPE_ID                     0x00FC
  97 
  98 #define REG_MAC_PHY_CTRL_NORMAL         0x00f8
  99 
 100 /*      0x0100h ~ 0x01FFh       MACTOP General Configuration */
 101 #define REG_CR                          0x0100
 102 #define REG_PBP                         0x0104
 103 #define REG_PKT_BUFF_ACCESS_CTRL        0x0106
 104 #define REG_TRXDMA_CTRL                 0x010C
 105 #define REG_TRXFF_BNDY                  0x0114
 106 #define REG_TRXFF_STATUS                0x0118
 107 #define REG_RXFF_PTR                    0x011C
 108 /* define REG_HIMR                      0x0120 */
 109 /* define REG_HISR                      0x0124 */
 110 #define REG_HIMRE                       0x0128
 111 #define REG_HISRE                       0x012C
 112 #define REG_CPWM                        0x012F
 113 #define REG_FWIMR                       0x0130
 114 #define REG_FTIMR                       0x0138
 115 #define REG_FWISR                       0x0134
 116 #define REG_PKTBUF_DBG_CTRL             0x0140
 117 #define REG_PKTBUF_DBG_ADDR             (REG_PKTBUF_DBG_CTRL)
 118 #define REG_RXPKTBUF_DBG                (REG_PKTBUF_DBG_CTRL + 2)
 119 #define REG_TXPKTBUF_DBG                (REG_PKTBUF_DBG_CTRL + 3)
 120 #define REG_RXPKTBUF_CTRL               (REG_PKTBUF_DBG_CTRL + 2)
 121 #define REG_PKTBUF_DBG_DATA_L           0x0144
 122 #define REG_PKTBUF_DBG_DATA_H           0x0148
 123 
 124 #define REG_TC0_CTRL                    0x0150
 125 #define REG_TC1_CTRL                    0x0154
 126 #define REG_TC2_CTRL                    0x0158
 127 #define REG_TC3_CTRL                    0x015C
 128 #define REG_TC4_CTRL                    0x0160
 129 #define REG_TCUNIT_BASE                 0x0164
 130 #define REG_MBIST_START                 0x0174
 131 #define REG_MBIST_DONE                  0x0178
 132 #define REG_MBIST_FAIL                  0x017C
 133 #define REG_32K_CTRL                    0x0194 /* RTL8188E */
 134 #define REG_C2HEVT_MSG_NORMAL           0x01A0
 135 #define REG_C2HEVT_CLEAR                0x01AF
 136 #define REG_MCUTST_1                    0x01c0
 137 #define REG_FMETHR                      0x01C8
 138 #define REG_HMETFR                      0x01CC
 139 #define REG_HMEBOX_0                    0x01D0
 140 #define REG_HMEBOX_1                    0x01D4
 141 #define REG_HMEBOX_2                    0x01D8
 142 #define REG_HMEBOX_3                    0x01DC
 143 
 144 #define REG_LLT_INIT                    0x01E0
 145 
 146 /*      0x0200h ~ 0x027Fh       TXDMA Configuration */
 147 #define REG_RQPN                        0x0200
 148 #define REG_FIFOPAGE                    0x0204
 149 #define REG_TDECTRL                     0x0208
 150 #define REG_TXDMA_OFFSET_CHK            0x020C
 151 #define REG_TXDMA_STATUS                0x0210
 152 #define REG_RQPN_NPQ                    0x0214
 153 
 154 /*      0x0280h ~ 0x02FFh       RXDMA Configuration */
 155 #define         REG_RXDMA_AGG_PG_TH     0x0280
 156 #define REG_RXPKT_NUM                   0x0284
 157 #define         REG_RXDMA_STATUS        0x0288
 158 
 159 /*      0x0300h ~ 0x03FFh       PCIe */
 160 #define REG_PCIE_CTRL_REG               0x0300
 161 #define REG_INT_MIG                     0x0304  /*  Interrupt Migration */
 162 #define REG_BCNQ_DESA                   0x0308  /*  TX Beacon Descr Address */
 163 #define REG_HQ_DESA                     0x0310  /*  TX High Queue Descr Addr */
 164 #define REG_MGQ_DESA                    0x0318  /*  TX Manage Queue Descr Addr*/
 165 #define REG_VOQ_DESA                    0x0320  /*  TX VO Queue Descr Addr */
 166 #define REG_VIQ_DESA                    0x0328  /*  TX VI Queue Descr Addr */
 167 #define REG_BEQ_DESA                    0x0330  /*  TX BE Queue Descr Addr */
 168 #define REG_BKQ_DESA                    0x0338  /*  TX BK Queue Descr Addr */
 169 #define REG_RX_DESA                     0x0340  /*  RX Queue Descr Addr */
 170 #define REG_MDIO                        0x0354  /*  MDIO for Access PCIE PHY */
 171 #define REG_DBG_SEL                     0x0360  /*  Debug Selection Register */
 172 #define REG_PCIE_HRPWM                  0x0361  /* PCIe RPWM */
 173 #define REG_PCIE_HCPWM                  0x0363  /* PCIe CPWM */
 174 #define REG_WATCH_DOG                   0x0368
 175 
 176 /*  RTL8723 series ------------------------------ */
 177 #define REG_PCIE_HISR                   0x03A0
 178 
 179 /*  spec version 11 */
 180 /*      0x0400h ~ 0x047Fh       Protocol Configuration */
 181 #define REG_VOQ_INFORMATION             0x0400
 182 #define REG_VIQ_INFORMATION             0x0404
 183 #define REG_BEQ_INFORMATION             0x0408
 184 #define REG_BKQ_INFORMATION             0x040C
 185 #define REG_MGQ_INFORMATION             0x0410
 186 #define REG_HGQ_INFORMATION             0x0414
 187 #define REG_BCNQ_INFORMATION            0x0418
 188 #define REG_TXPKT_EMPTY                 0x041A
 189 
 190 #define REG_CPU_MGQ_INFORMATION         0x041C
 191 #define REG_FWHW_TXQ_CTRL               0x0420
 192 #define REG_HWSEQ_CTRL                  0x0423
 193 #define REG_TXPKTBUF_BCNQ_BDNY          0x0424
 194 #define REG_TXPKTBUF_MGQ_BDNY           0x0425
 195 #define REG_LIFETIME_EN                 0x0426
 196 #define REG_MULTI_BCNQ_OFFSET           0x0427
 197 #define REG_SPEC_SIFS                   0x0428
 198 #define REG_RL                          0x042A
 199 #define REG_DARFRC                      0x0430
 200 #define REG_RARFRC                      0x0438
 201 #define REG_RRSR                        0x0440
 202 #define REG_ARFR0                       0x0444
 203 #define REG_ARFR1                       0x0448
 204 #define REG_ARFR2                       0x044C
 205 #define REG_ARFR3                       0x0450
 206 #define REG_AGGLEN_LMT                  0x0458
 207 #define REG_AMPDU_MIN_SPACE             0x045C
 208 #define REG_TXPKTBUF_WMAC_LBK_BF_HD     0x045D
 209 #define REG_FAST_EDCA_CTRL              0x0460
 210 #define REG_RD_RESP_PKT_TH              0x0463
 211 #define REG_INIRTS_RATE_SEL             0x0480
 212 /* define REG_INIDATA_RATE_SEL          0x0484 */
 213 #define REG_POWER_STATUS                0x04A4
 214 #define REG_POWER_STAGE1                0x04B4
 215 #define REG_POWER_STAGE2                0x04B8
 216 #define REG_PKT_VO_VI_LIFE_TIME         0x04C0
 217 #define REG_PKT_BE_BK_LIFE_TIME         0x04C2
 218 #define REG_STBC_SETTING                0x04C4
 219 #define REG_PROT_MODE_CTRL              0x04C8
 220 #define REG_MAX_AGGR_NUM                0x04CA
 221 #define REG_RTS_MAX_AGGR_NUM            0x04CB
 222 #define REG_BAR_MODE_CTRL               0x04CC
 223 #define REG_RA_TRY_RATE_AGG_LMT         0x04CF
 224 #define REG_EARLY_MODE_CONTROL          0x4D0
 225 #define REG_NQOS_SEQ                    0x04DC
 226 #define REG_QOS_SEQ                     0x04DE
 227 #define REG_NEED_CPU_HANDLE             0x04E0
 228 #define REG_PKT_LOSE_RPT                0x04E1
 229 #define REG_PTCL_ERR_STATUS             0x04E2
 230 #define REG_TX_RPT_CTRL                 0x04EC
 231 #define REG_TX_RPT_TIME                 0x04F0  /*  2 byte */
 232 #define REG_DUMMY                       0x04FC
 233 
 234 /*      0x0500h ~ 0x05FFh       EDCA Configuration */
 235 #define REG_EDCA_VO_PARAM               0x0500
 236 #define REG_EDCA_VI_PARAM               0x0504
 237 #define REG_EDCA_BE_PARAM               0x0508
 238 #define REG_EDCA_BK_PARAM               0x050C
 239 #define REG_BCNTCFG                     0x0510
 240 #define REG_PIFS                        0x0512
 241 #define REG_RDG_PIFS                    0x0513
 242 #define REG_SIFS_CTX                    0x0514
 243 #define REG_SIFS_TRX                    0x0516
 244 #define REG_TSFTR_SYN_OFFSET            0x0518
 245 #define REG_AGGR_BREAK_TIME             0x051A
 246 #define REG_SLOT                        0x051B
 247 #define REG_TX_PTCL_CTRL                0x0520
 248 #define REG_TXPAUSE                     0x0522
 249 #define REG_DIS_TXREQ_CLR               0x0523
 250 #define REG_RD_CTRL                     0x0524
 251 /*  Format for offset 540h-542h:
 252  *      [3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting
 253  *               beacon content before TBTT.
 254  *
 255  *      [7:4]:   Reserved.
 256  *      [19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding
 257  *               to send the beacon packet.
 258  *
 259  *      [23:20]: Reserved
 260  *  Description:
 261  *                    |
 262  *      |<--Setup--|--Hold------------>|
 263  *      --------------|----------------------
 264  *                 |
 265  *                TBTT
 266  *  Note: We cannot update beacon content to HW or send any AC packets during
 267  *        the time between Setup and Hold.
 268  */
 269 #define REG_TBTT_PROHIBIT               0x0540
 270 #define REG_RD_NAV_NXT                  0x0544
 271 #define REG_NAV_PROT_LEN                0x0546
 272 #define REG_BCN_CTRL                    0x0550
 273 #define REG_BCN_CTRL_1                  0x0551
 274 #define REG_MBID_NUM                    0x0552
 275 #define REG_DUAL_TSF_RST                0x0553
 276 #define REG_BCN_INTERVAL                0x0554
 277 #define REG_DRVERLYINT                  0x0558
 278 #define REG_BCNDMATIM                   0x0559
 279 #define REG_ATIMWND                     0x055A
 280 #define REG_BCN_MAX_ERR                 0x055D
 281 #define REG_RXTSF_OFFSET_CCK            0x055E
 282 #define REG_RXTSF_OFFSET_OFDM           0x055F
 283 #define REG_TSFTR                       0x0560
 284 #define REG_TSFTR1                      0x0568
 285 #define REG_ATIMWND_1                   0x0570
 286 #define REG_PSTIMER                     0x0580
 287 #define REG_TIMER0                      0x0584
 288 #define REG_TIMER1                      0x0588
 289 #define REG_ACMHWCTRL                   0x05C0
 290 
 291 /* define REG_FW_TSF_SYNC_CNT           0x04A0 */
 292 #define REG_FW_RESET_TSF_CNT_1          0x05FC
 293 #define REG_FW_RESET_TSF_CNT_0          0x05FD
 294 #define REG_FW_BCN_DIS_CNT              0x05FE
 295 
 296 /*      0x0600h ~ 0x07FFh       WMAC Configuration */
 297 #define REG_APSD_CTRL                   0x0600
 298 #define REG_BWOPMODE                    0x0603
 299 #define REG_TCR                         0x0604
 300 #define REG_RCR                         0x0608
 301 #define REG_RX_PKT_LIMIT                0x060C
 302 #define REG_RX_DLK_TIME                 0x060D
 303 #define REG_RX_DRVINFO_SZ               0x060F
 304 
 305 #define REG_MACID                       0x0610
 306 #define REG_BSSID                       0x0618
 307 #define REG_MAR                         0x0620
 308 #define REG_MBIDCAMCFG                  0x0628
 309 
 310 #define REG_USTIME_EDCA                 0x0638
 311 #define REG_MAC_SPEC_SIFS               0x063A
 312 
 313 /*  20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
 314 /*  [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
 315 #define REG_R2T_SIFS                    0x063C
 316 /*  [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
 317 #define REG_T2T_SIFS                    0x063E
 318 #define REG_ACKTO                       0x0640
 319 #define REG_CTS2TO                      0x0641
 320 #define REG_EIFS                        0x0642
 321 
 322 /* RXERR_RPT */
 323 #define RXERR_TYPE_OFDM_PPDU            0
 324 #define RXERR_TYPE_OFDM_false_ALARM     1
 325 #define RXERR_TYPE_OFDM_MPDU_OK         2
 326 #define RXERR_TYPE_OFDM_MPDU_FAIL       3
 327 #define RXERR_TYPE_CCK_PPDU             4
 328 #define RXERR_TYPE_CCK_false_ALARM      5
 329 #define RXERR_TYPE_CCK_MPDU_OK          6
 330 #define RXERR_TYPE_CCK_MPDU_FAIL        7
 331 #define RXERR_TYPE_HT_PPDU              8
 332 #define RXERR_TYPE_HT_false_ALARM       9
 333 #define RXERR_TYPE_HT_MPDU_TOTAL        10
 334 #define RXERR_TYPE_HT_MPDU_OK           11
 335 #define RXERR_TYPE_HT_MPDU_FAIL         12
 336 #define RXERR_TYPE_RX_FULL_DROP         15
 337 
 338 #define RXERR_COUNTER_MASK              0xFFFFF
 339 #define RXERR_RPT_RST                   BIT(27)
 340 #define _RXERR_RPT_SEL(type)            ((type) << 28)
 341 
 342 /*  Note:
 343  *      The NAV upper value is very important to WiFi 11n 5.2.3 NAV test.
 344  *      The default value is always too small, but the WiFi TestPlan test
 345  *      by 25,000 microseconds of NAV through sending CTS in the air.
 346  *      We must update this value greater than 25,000 microseconds to pass
 347  *      the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and
 348  *      the offset should be 0x0652.
 349  */
 350 #define REG_NAV_UPPER                   0x0652  /*  unit of 128 */
 351 
 352 /* WMA, BA, CCX */
 353 /* define REG_NAV_CTRL                  0x0650 */
 354 #define REG_BACAMCMD                    0x0654
 355 #define REG_BACAMCONTENT                0x0658
 356 #define REG_LBDLY                       0x0660
 357 #define REG_FWDLY                       0x0661
 358 #define REG_RXERR_RPT                   0x0664
 359 #define REG_WMAC_TRXPTCL_CTL            0x0668
 360 
 361 /*  Security */
 362 #define REG_CAMCMD                      0x0670
 363 #define REG_CAMWRITE                    0x0674
 364 #define REG_CAMREAD                     0x0678
 365 #define REG_CAMDBG                      0x067C
 366 #define REG_SECCFG                      0x0680
 367 
 368 /*  Power */
 369 #define REG_WOW_CTRL                    0x0690
 370 #define REG_PS_RX_INFO                  0x0692
 371 #define REG_UAPSD_TID                   0x0693
 372 #define REG_WKFMCAM_CMD                 0x0698
 373 #define REG_WKFMCAM_NUM_88E             0x698
 374 #define REG_RXFLTMAP0                   0x06A0
 375 #define REG_RXFLTMAP1                   0x06A2
 376 #define REG_RXFLTMAP2                   0x06A4
 377 #define REG_BCN_PSR_RPT                 0x06A8
 378 #define REG_BT_COEX_TABLE               0x06C0
 379 
 380 /*  Hardware Port 2 */
 381 #define REG_MACID1                      0x0700
 382 #define REG_BSSID1                      0x0708
 383 
 384 /*      0xFE00h ~ 0xFE55h       USB Configuration */
 385 #define REG_USB_INFO                    0xFE17
 386 #define REG_USB_SPECIAL_OPTION          0xFE55
 387 #define REG_USB_DMA_AGG_TO              0xFE5B
 388 #define REG_USB_AGG_TO                  0xFE5C
 389 #define REG_USB_AGG_TH                  0xFE5D
 390 
 391 /*  For normal chip */
 392 #define REG_NORMAL_SIE_VID              0xFE60          /*  0xFE60~0xFE61 */
 393 #define REG_NORMAL_SIE_PID              0xFE62          /*  0xFE62~0xFE63 */
 394 #define REG_NORMAL_SIE_OPTIONAL         0xFE64
 395 #define REG_NORMAL_SIE_EP               0xFE65          /*  0xFE65~0xFE67 */
 396 #define REG_NORMAL_SIE_PHY              0xFE68          /*  0xFE68~0xFE6B */
 397 #define REG_NORMAL_SIE_OPTIONAL2        0xFE6C
 398 #define REG_NORMAL_SIE_GPS_EP           0xFE6D  /*  0xFE6D, for RTL8723 only. */
 399 #define REG_NORMAL_SIE_MAC_ADDR         0xFE70          /*  0xFE70~0xFE75 */
 400 #define REG_NORMAL_SIE_STRING           0xFE80          /*  0xFE80~0xFEDF */
 401 
 402 /*  TODO: use these definition when using REG_xxx naming rule. */
 403 /*  NOTE: DO NOT Remove these definition. Use later. */
 404 
 405 #define EFUSE_CTRL                      REG_EFUSE_CTRL  /*  E-Fuse Control. */
 406 #define EFUSE_TEST                      REG_EFUSE_TEST  /*  E-Fuse Test. */
 407 #define MSR                             (REG_CR + 2)    /*  Media Status reg */
 408 #define ISR                             REG_HISR_88E
 409 /*  Timing Sync Function Timer Register. */
 410 #define TSFR                            REG_TSFTR
 411 
 412 #define         PBP                     REG_PBP
 413 
 414 /*  Redifine MACID register, to compatible prior ICs. */
 415 /*  MAC ID Register, Offset 0x0050-0x0053 */
 416 #define IDR0                            REG_MACID
 417 /*  MAC ID Register, Offset 0x0054-0x0055 */
 418 #define IDR4                            (REG_MACID + 4)
 419 
 420 /*  9. Security Control Registers       (Offset: ) */
 421 /* IN 8190 Data Sheet is called CAMcmd */
 422 #define RWCAM                           REG_CAMCMD
 423 /*  Software write CAM input content */
 424 #define WCAMI                           REG_CAMWRITE
 425 /*  Software read/write CAM config */
 426 #define RCAMO                           REG_CAMREAD
 427 #define CAMDBG                          REG_CAMDBG
 428 /* Security Configuration Register */
 429 #define SECR                            REG_SECCFG
 430 
 431 /*  Unused register */
 432 #define UnusedRegister                  0x1BF
 433 #define DCAM                            UnusedRegister
 434 #define PSR                             UnusedRegister
 435 #define BBAddr                          UnusedRegister
 436 #define PhyDataR                        UnusedRegister
 437 
 438 /*  Min Spacing related settings. */
 439 #define MAX_MSS_DENSITY_2T              0x13
 440 #define MAX_MSS_DENSITY_1T              0x0A
 441 
 442 /*  EEPROM enable when set 1 */
 443 #define CmdEEPROM_En                    BIT(5)
 444 /*  System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
 445 #define CmdEERPOMSEL                    BIT(4)
 446 #define Cmd9346CR_9356SEL               BIT(4)
 447 
 448 /*        8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */
 449 #define GPIOSEL_GPIO                    0
 450 #define GPIOSEL_ENBT                    BIT(5)
 451 
 452 /*        8192C GPIO PIN Control Register (offset 0x44, 4 byte) */
 453 /*  GPIO pins input value */
 454 #define GPIO_IN                         REG_GPIO_PIN_CTRL
 455 /*  GPIO pins output value */
 456 #define GPIO_OUT                        (REG_GPIO_PIN_CTRL + 1)
 457 /*  GPIO pins output enable when a bit is set to "1"; otherwise,
 458  *  input is configured.
 459  */
 460 #define GPIO_IO_SEL                     (REG_GPIO_PIN_CTRL + 2)
 461 #define GPIO_MOD                        (REG_GPIO_PIN_CTRL + 3)
 462 
 463 /* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
 464 #define HSIMR_GPIO12_0_INT_EN           BIT(0)
 465 #define HSIMR_SPS_OCP_INT_EN            BIT(5)
 466 #define HSIMR_RON_INT_EN                BIT(6)
 467 #define HSIMR_PDN_INT_EN                BIT(7)
 468 #define HSIMR_GPIO9_INT_EN              BIT(25)
 469 
 470 /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
 471 #define HSISR_GPIO12_0_INT              BIT(0)
 472 #define HSISR_SPS_OCP_INT               BIT(5)
 473 #define HSISR_RON_INT_EN                BIT(6)
 474 #define HSISR_PDNINT                    BIT(7)
 475 #define HSISR_GPIO9_INT                 BIT(25)
 476 
 477 /*   8192C (MSR) Media Status Register  (Offset 0x4C, 8 bits) */
 478 /*
 479  * Network Type
 480  * 00: No link
 481  * 01: Link in ad hoc network
 482  * 10: Link in infrastructure network
 483  * 11: AP mode
 484  * Default: 00b.
 485  */
 486 #define MSR_NOLINK                      0x00
 487 #define MSR_ADHOC                       0x01
 488 #define MSR_INFRA                       0x02
 489 #define MSR_AP                          0x03
 490 
 491 /*   88EU (MSR) Media Status Register   (Offset 0x4C, 8 bits) */
 492 #define USB_INTR_CONTENT_C2H_OFFSET     0
 493 #define USB_INTR_CONTENT_CPWM1_OFFSET   16
 494 #define USB_INTR_CONTENT_CPWM2_OFFSET   20
 495 #define USB_INTR_CONTENT_HISR_OFFSET    48
 496 #define USB_INTR_CONTENT_HISRE_OFFSET   52
 497 
 498 /*  88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */
 499 /* IOL config for REG_FDHM0(Reg0x88) */
 500 #define CMD_INIT_LLT                    BIT(0)
 501 #define CMD_READ_EFUSE_MAP              BIT(1)
 502 #define CMD_EFUSE_PATCH                 BIT(2)
 503 #define CMD_IOCONFIG                    BIT(3)
 504 #define CMD_INIT_LLT_ERR                BIT(4)
 505 #define CMD_READ_EFUSE_MAP_ERR          BIT(5)
 506 #define CMD_EFUSE_PATCH_ERR             BIT(6)
 507 #define CMD_IOCONFIG_ERR                BIT(7)
 508 
 509 /*  6. Adaptive Control Registers  (Offset: 0x0160 - 0x01CF) */
 510 /*  8192C Response Rate Set Register    (offset 0x181, 24bits) */
 511 #define RRSR_1M                         BIT(0)
 512 #define RRSR_2M                         BIT(1)
 513 #define RRSR_5_5M                       BIT(2)
 514 #define RRSR_11M                        BIT(3)
 515 #define RRSR_6M                         BIT(4)
 516 #define RRSR_9M                         BIT(5)
 517 #define RRSR_12M                        BIT(6)
 518 #define RRSR_18M                        BIT(7)
 519 #define RRSR_24M                        BIT(8)
 520 #define RRSR_36M                        BIT(9)
 521 #define RRSR_48M                        BIT(10)
 522 #define RRSR_54M                        BIT(11)
 523 #define RRSR_MCS0                       BIT(12)
 524 #define RRSR_MCS1                       BIT(13)
 525 #define RRSR_MCS2                       BIT(14)
 526 #define RRSR_MCS3                       BIT(15)
 527 #define RRSR_MCS4                       BIT(16)
 528 #define RRSR_MCS5                       BIT(17)
 529 #define RRSR_MCS6                       BIT(18)
 530 #define RRSR_MCS7                       BIT(19)
 531 
 532 /*  8192C Response Rate Set Register    (offset 0x1BF, 8bits) */
 533 /*  WOL bit information */
 534 #define HAL92C_WOL_PTK_UPDATE_EVENT     BIT(0)
 535 #define HAL92C_WOL_GTK_UPDATE_EVENT     BIT(1)
 536 
 537 /*        8192C BW_OPMODE bits          (Offset 0x203, 8bit) */
 538 #define BW_OPMODE_20MHZ                 BIT(2)
 539 #define BW_OPMODE_5G                    BIT(1)
 540 
 541 /*        8192C CAM Config Setting (offset 0x250, 1 byte) */
 542 #define CAM_VALID                       BIT(15)
 543 #define CAM_NOTVALID                    0x0000
 544 #define CAM_USEDK                       BIT(5)
 545 
 546 #define CAM_CONTENT_COUNT               8
 547 
 548 #define CAM_NONE                        0x0
 549 #define CAM_WEP40                       0x01
 550 #define CAM_TKIP                        0x02
 551 #define CAM_AES                         0x04
 552 #define CAM_WEP104                      0x05
 553 #define CAM_SMS4                        0x6
 554 
 555 #define TOTAL_CAM_ENTRY                 32
 556 #define HALF_CAM_ENTRY                  16
 557 
 558 #define CAM_CONFIG_USEDK                true
 559 #define CAM_CONFIG_NO_USEDK             false
 560 
 561 #define CAM_WRITE                       BIT(16)
 562 #define CAM_READ                        0x00000000
 563 #define CAM_POLLINIG                    BIT(31)
 564 
 565 #define SCR_UseDK                       0x01
 566 #define SCR_TxSecEnable                 0x02
 567 #define SCR_RxSecEnable                 0x04
 568 
 569 /*  10. Power Save Control Registers     (Offset: 0x0260 - 0x02DF) */
 570 #define WOW_PMEN                        BIT(0) /*  Power management Enable. */
 571 #define WOW_WOMEN                       BIT(1) /*  WoW function on or off. */
 572 #define WOW_MAGIC                       BIT(2) /*  Magic packet */
 573 #define WOW_UWF                         BIT(3) /*  Unicast Wakeup frame. */
 574 
 575 /*  12. Host Interrupt Status Registers  (Offset: 0x0300 - 0x030F) */
 576 /*        8188 IMR/ISR bits */
 577 #define IMR_DISABLED_88E                0x0
 578 /*  IMR DW0(0x0060-0063) Bit 0-31 */
 579 #define IMR_TXCCK_88E                   BIT(30) /*  TXRPT interrupt when CCX bit of the packet is set */
 580 #define IMR_PSTIMEOUT_88E               BIT(29) /*  Power Save Time Out Interrupt */
 581 #define IMR_GTINT4_88E                  BIT(28) /*  When GTIMER4 expires, this bit is set to 1 */
 582 #define IMR_GTINT3_88E                  BIT(27) /*  When GTIMER3 expires, this bit is set to 1 */
 583 #define IMR_TBDER_88E                   BIT(26) /*  Transmit Beacon0 Error */
 584 #define IMR_TBDOK_88E                   BIT(25) /*  Transmit Beacon0 OK */
 585 #define IMR_TSF_BIT32_TOGGLE_88E        BIT(24) /*  TSF Timer BIT32 toggle indication interrupt */
 586 #define IMR_BCNDMAINT0_88E              BIT(20) /*  Beacon DMA Interrupt 0 */
 587 #define IMR_BCNDERR0_88E                BIT(16) /*  Beacon Queue DMA Error 0 */
 588 #define IMR_HSISR_IND_ON_INT_88E        BIT(15) /*  HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
 589 #define IMR_BCNDMAINT_E_88E             BIT(14) /*  Beacon DMA Interrupt Extension for Win7 */
 590 #define IMR_ATIMEND_88E                 BIT(12) /*  CTWidnow End or ATIM Window End */
 591 #define IMR_HISR1_IND_INT_88E           BIT(11) /*  HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
 592 #define IMR_C2HCMD_88E                  BIT(10) /*  CPU to Host Command INT Status, Write 1 clear */
 593 #define IMR_CPWM2_88E                   BIT(9)  /*  CPU power Mode exchange INT Status, Write 1 clear */
 594 #define IMR_CPWM_88E                    BIT(8)  /*  CPU power Mode exchange INT Status, Write 1 clear */
 595 #define IMR_HIGHDOK_88E                 BIT(7)  /*  High Queue DMA OK */
 596 #define IMR_MGNTDOK_88E                 BIT(6)  /*  Management Queue DMA OK */
 597 #define IMR_BKDOK_88E                   BIT(5)  /*  AC_BK DMA OK */
 598 #define IMR_BEDOK_88E                   BIT(4)  /*  AC_BE DMA OK */
 599 #define IMR_VIDOK_88E                   BIT(3)  /*  AC_VI DMA OK */
 600 #define IMR_VODOK_88E                   BIT(2)  /*  AC_VO DMA OK */
 601 #define IMR_RDU_88E                     BIT(1)  /*  Rx Descriptor Unavailable */
 602 #define IMR_ROK_88E                     BIT(0)  /*  Receive DMA OK */
 603 
 604 /*  IMR DW1(0x00B4-00B7) Bit 0-31 */
 605 #define IMR_BCNDMAINT7_88E              BIT(27) /*  Beacon DMA Interrupt 7 */
 606 #define IMR_BCNDMAINT6_88E              BIT(26) /*  Beacon DMA Interrupt 6 */
 607 #define IMR_BCNDMAINT5_88E              BIT(25) /*  Beacon DMA Interrupt 5 */
 608 #define IMR_BCNDMAINT4_88E              BIT(24) /*  Beacon DMA Interrupt 4 */
 609 #define IMR_BCNDMAINT3_88E              BIT(23) /*  Beacon DMA Interrupt 3 */
 610 #define IMR_BCNDMAINT2_88E              BIT(22) /*  Beacon DMA Interrupt 2 */
 611 #define IMR_BCNDMAINT1_88E              BIT(21) /*  Beacon DMA Interrupt 1 */
 612 #define IMR_BCNDERR7_88E                BIT(20) /*  Beacon DMA Error Int 7 */
 613 #define IMR_BCNDERR6_88E                BIT(19) /*  Beacon DMA Error Int 6 */
 614 #define IMR_BCNDERR5_88E                BIT(18) /*  Beacon DMA Error Int 5 */
 615 #define IMR_BCNDERR4_88E                BIT(17) /*  Beacon DMA Error Int 4 */
 616 #define IMR_BCNDERR3_88E                BIT(16) /*  Beacon DMA Error Int 3 */
 617 #define IMR_BCNDERR2_88E                BIT(15) /*  Beacon DMA Error Int 2 */
 618 #define IMR_BCNDERR1_88E                BIT(14) /*  Beacon DMA Error Int 1 */
 619 #define IMR_ATIMEND_E_88E               BIT(13) /*  ATIM Window End Ext for Win7 */
 620 #define IMR_TXERR_88E                   BIT(11) /*  Tx Err Flag Int Status, write 1 clear. */
 621 #define IMR_RXERR_88E                   BIT(10) /*  Rx Err Flag INT Status, Write 1 clear */
 622 #define IMR_TXFOVW_88E                  BIT(9)  /*  Transmit FIFO Overflow */
 623 #define IMR_RXFOVW_88E                  BIT(8)  /*  Receive FIFO Overflow */
 624 
 625 #define HAL_NIC_UNPLUG_ISR              0xFFFFFFFF      /*  The value when the NIC is unplugged for PCI. */
 626 
 627 /*  8192C EFUSE */
 628 #define         HWSET_MAX_SIZE                  256
 629 #define         HWSET_MAX_SIZE_88E              512
 630 
 631 /*===================================================================
 632 =====================================================================
 633 Here the register defines are for 92C. When the define is as same with 92C,
 634 we will use the 92C's define for the consistency
 635 So the following defines for 92C is not entire!!!!!!
 636 =====================================================================
 637 =====================================================================*/
 638 /*
 639  * Based on Datasheet V33---090401
 640  * Register Summary
 641  * Current IOREG MAP
 642  * 0x0000h ~ 0x00FFh   System Configuration (256 Bytes)
 643  * 0x0100h ~ 0x01FFh   MACTOP General Configuration (256 Bytes)
 644  * 0x0200h ~ 0x027Fh   TXDMA Configuration (128 Bytes)
 645  * 0x0280h ~ 0x02FFh   RXDMA Configuration (128 Bytes)
 646  * 0x0300h ~ 0x03FFh   PCIE EMAC Reserved Region (256 Bytes)
 647  * 0x0400h ~ 0x04FFh   Protocol Configuration (256 Bytes)
 648  * 0x0500h ~ 0x05FFh   EDCA Configuration (256 Bytes)
 649  * 0x0600h ~ 0x07FFh   WMAC Configuration (512 Bytes)
 650  * 0x2000h ~ 0x3FFFh   8051 FW Download Region (8196 Bytes)
 651  */
 652 /*               8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */
 653 /*  Note:
 654  *      The bits of stopping AC(VO/VI/BE/BK) queue in datasheet
 655  *      RTL8192S/RTL8192C are wrong,
 656  *      the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2,
 657  *      and BK - Bit3.
 658  *      8723 and 88E may be not correct either in the earlier version.
 659  */
 660 #define         StopBecon                       BIT(6)
 661 #define         StopHigh                        BIT(5)
 662 #define         StopMgt                         BIT(4)
 663 #define         StopBK                          BIT(3)
 664 #define         StopBE                          BIT(2)
 665 #define         StopVI                          BIT(1)
 666 #define         StopVO                          BIT(0)
 667 
 668 /*        8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */
 669 #define RCR_APPFCS              BIT(31) /* WMAC append FCS after payload */
 670 #define RCR_APP_MIC             BIT(30)
 671 #define RCR_APP_PHYSTS          BIT(28)
 672 #define RCR_APP_ICV             BIT(29)
 673 #define RCR_APP_PHYST_RXFF      BIT(28)
 674 #define RCR_APP_BA_SSN          BIT(27) /* Accept BA SSN */
 675 #define RCR_ENMBID              BIT(24) /* Enable Multiple BssId. */
 676 #define RCR_LSIGEN              BIT(23)
 677 #define RCR_MFBEN               BIT(22)
 678 #define RCR_HTC_LOC_CTRL        BIT(14)   /* MFC<--HTC=1 MFC-->HTC=0 */
 679 #define RCR_AMF                 BIT(13) /* Accept management type frame */
 680 #define RCR_ACF                 BIT(12) /* Accept control type frame */
 681 #define RCR_ADF                 BIT(11) /* Accept data type frame */
 682 #define RCR_AICV                BIT(9)  /* Accept ICV error packet */
 683 #define RCR_ACRC32              BIT(8)  /* Accept CRC32 error packet */
 684 #define RCR_CBSSID_BCN          BIT(7)  /* Accept BSSID match packet
 685                                          * (Rx beacon, probe rsp)
 686                                          */
 687 #define RCR_CBSSID_DATA         BIT(6)  /* Accept BSSID match (Data)*/
 688 #define RCR_CBSSID              RCR_CBSSID_DATA /* Accept BSSID match */
 689 #define RCR_APWRMGT             BIT(5)  /* Accept power management pkt*/
 690 #define RCR_ADD3                BIT(4)  /* Accept address 3 match pkt */
 691 #define RCR_AB                  BIT(3)  /* Accept broadcast packet */
 692 #define RCR_AM                  BIT(2)  /* Accept multicast packet */
 693 #define RCR_APM                 BIT(1)  /* Accept physical match pkt */
 694 #define RCR_AAP                 BIT(0)  /* Accept all unicast packet */
 695 #define RCR_MXDMA_OFFSET        8
 696 #define RCR_FIFO_OFFSET         13
 697 
 698 /*      0xFE00h ~ 0xFE55h       USB Configuration */
 699 #define REG_USB_INFO                    0xFE17
 700 #define REG_USB_SPECIAL_OPTION          0xFE55
 701 #define REG_USB_DMA_AGG_TO              0xFE5B
 702 #define REG_USB_AGG_TO                  0xFE5C
 703 #define REG_USB_AGG_TH                  0xFE5D
 704 
 705 #define REG_USB_HRPWM                   0xFE58
 706 #define REG_USB_HCPWM                   0xFE57
 707 /*        8192C Register Bit and Content definition */
 708 /*      0x0000h ~ 0x00FFh       System Configuration */
 709 
 710 /* 2 SYS_ISO_CTRL */
 711 #define ISO_MD2PP                       BIT(0)
 712 #define ISO_UA2USB                      BIT(1)
 713 #define ISO_UD2CORE                     BIT(2)
 714 #define ISO_PA2PCIE                     BIT(3)
 715 #define ISO_PD2CORE                     BIT(4)
 716 #define ISO_IP2MAC                      BIT(5)
 717 #define ISO_DIOP                        BIT(6)
 718 #define ISO_DIOE                        BIT(7)
 719 #define ISO_EB2CORE                     BIT(8)
 720 #define ISO_DIOR                        BIT(9)
 721 #define PWC_EV12V                       BIT(15)
 722 
 723 /* 2 SYS_FUNC_EN */
 724 #define FEN_BBRSTB                      BIT(0)
 725 #define FEN_BB_GLB_RSTn                 BIT(1)
 726 #define FEN_USBA                        BIT(2)
 727 #define FEN_UPLL                        BIT(3)
 728 #define FEN_USBD                        BIT(4)
 729 #define FEN_DIO_PCIE                    BIT(5)
 730 #define FEN_PCIEA                       BIT(6)
 731 #define FEN_PPLL                        BIT(7)
 732 #define FEN_PCIED                       BIT(8)
 733 #define FEN_DIOE                        BIT(9)
 734 #define FEN_CPUEN                       BIT(10)
 735 #define FEN_DCORE                       BIT(11)
 736 #define FEN_ELDR                        BIT(12)
 737 #define FEN_DIO_RF                      BIT(13)
 738 #define FEN_HWPDN                       BIT(14)
 739 #define FEN_MREGEN                      BIT(15)
 740 
 741 /* 2 APS_FSMCO */
 742 #define PFM_LDALL                       BIT(0)
 743 #define PFM_ALDN                        BIT(1)
 744 #define PFM_LDKP                        BIT(2)
 745 #define PFM_WOWL                        BIT(3)
 746 #define EnPDN                           BIT(4)
 747 #define PDN_PL                          BIT(5)
 748 #define APFM_ONMAC                      BIT(8)
 749 #define APFM_OFF                        BIT(9)
 750 #define APFM_RSM                        BIT(10)
 751 #define AFSM_HSUS                       BIT(11)
 752 #define AFSM_PCIE                       BIT(12)
 753 #define APDM_MAC                        BIT(13)
 754 #define APDM_HOST                       BIT(14)
 755 #define APDM_HPDN                       BIT(15)
 756 #define RDY_MACON                       BIT(16)
 757 #define SUS_HOST                        BIT(17)
 758 #define ROP_ALD                         BIT(20)
 759 #define ROP_PWR                         BIT(21)
 760 #define ROP_SPS                         BIT(22)
 761 #define SOP_MRST                        BIT(25)
 762 #define SOP_FUSE                        BIT(26)
 763 #define SOP_ABG                         BIT(27)
 764 #define SOP_AMB                         BIT(28)
 765 #define SOP_RCK                         BIT(29)
 766 #define SOP_A8M                         BIT(30)
 767 #define XOP_BTCK                        BIT(31)
 768 
 769 /* 2 SYS_CLKR */
 770 #define ANAD16V_EN                      BIT(0)
 771 #define ANA8M                           BIT(1)
 772 #define MACSLP                          BIT(4)
 773 #define LOADER_CLK_EN                   BIT(5)
 774 
 775 /* 2 9346CR */
 776 
 777 #define         BOOT_FROM_EEPROM        BIT(4)
 778 #define         EEPROM_EN               BIT(5)
 779 
 780 /* 2 SPS0_CTRL */
 781 
 782 /* 2 SPS_OCP_CFG */
 783 
 784 /* 2 RF_CTRL */
 785 #define RF_EN                           BIT(0)
 786 #define RF_RSTB                         BIT(1)
 787 #define RF_SDMRSTB                      BIT(2)
 788 
 789 /* 2 LDOV12D_CTRL */
 790 #define LDV12_EN                        BIT(0)
 791 #define LDV12_SDBY                      BIT(1)
 792 #define LPLDO_HSM                       BIT(2)
 793 #define LPLDO_LSM_DIS                   BIT(3)
 794 #define _LDV12_VADJ(x)                  (((x) & 0xF) << 4)
 795 
 796 /* 2EFUSE_CTRL */
 797 #define ALD_EN                          BIT(18)
 798 #define EF_PD                           BIT(19)
 799 #define EF_FLAG                         BIT(31)
 800 
 801 /* 2 EFUSE_TEST (For RTL8723 partially) */
 802 #define EF_TRPT                         BIT(7)
 803 /*  00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
 804 #define EF_CELL_SEL                     (BIT(8) | BIT(9))
 805 #define LDOE25_EN                       BIT(31)
 806 #define EFUSE_SEL(x)                    (((x) & 0x3) << 8)
 807 #define EFUSE_SEL_MASK                  0x300
 808 #define EFUSE_WIFI_SEL_0                0x0
 809 #define EFUSE_BT_SEL_0                  0x1
 810 #define EFUSE_BT_SEL_1                  0x2
 811 #define EFUSE_BT_SEL_2                  0x3
 812 
 813 #define EFUSE_ACCESS_ON                 0x69    /*  For RTL8723 only. */
 814 #define EFUSE_ACCESS_OFF                0x00    /*  For RTL8723 only. */
 815 
 816 /* 2 8051FWDL */
 817 /* 2 MCUFWDL */
 818 #define MCUFWDL_EN                      BIT(0)
 819 #define MCUFWDL_RDY                     BIT(1)
 820 #define FWDL_ChkSum_rpt                 BIT(2)
 821 #define MACINI_RDY                      BIT(3)
 822 #define BBINI_RDY                       BIT(4)
 823 #define RFINI_RDY                       BIT(5)
 824 #define WINTINI_RDY                     BIT(6)
 825 #define RAM_DL_SEL                      BIT(7) /*  1:RAM, 0:ROM */
 826 #define ROM_DLEN                        BIT(19)
 827 #define CPRST                           BIT(23)
 828 
 829 /* 2 REG_SYS_CFG */
 830 #define XCLK_VLD                        BIT(0)
 831 #define ACLK_VLD                        BIT(1)
 832 #define UCLK_VLD                        BIT(2)
 833 #define PCLK_VLD                        BIT(3)
 834 #define PCIRSTB                         BIT(4)
 835 #define V15_VLD                         BIT(5)
 836 #define SW_OFFLOAD_EN                   BIT(7)
 837 #define SIC_IDLE                        BIT(8)
 838 #define BD_MAC2                         BIT(9)
 839 #define BD_MAC1                         BIT(10)
 840 #define IC_MACPHY_MODE                  BIT(11)
 841 #define CHIP_VER                        (BIT(12) | BIT(13) | BIT(14) | BIT(15))
 842 #define BT_FUNC                         BIT(16)
 843 #define VENDOR_ID                       BIT(19)
 844 #define PAD_HWPD_IDN                    BIT(22)
 845 #define TRP_VAUX_EN                     BIT(23) /*  RTL ID */
 846 #define TRP_BT_EN                       BIT(24)
 847 #define BD_PKG_SEL                      BIT(25)
 848 #define BD_HCI_SEL                      BIT(26)
 849 #define TYPE_ID                         BIT(27)
 850 
 851 #define CHIP_VER_RTL_MASK               0xF000  /* Bit 12 ~ 15 */
 852 #define CHIP_VER_RTL_SHIFT              12
 853 
 854 /* 2REG_GPIO_OUTSTS (For RTL8723 only) */
 855 #define EFS_HCI_SEL                     (BIT(0) | BIT(1))
 856 #define PAD_HCI_SEL                     (BIT(2) | BIT(3))
 857 #define HCI_SEL                         (BIT(4) | BIT(5))
 858 #define PKG_SEL_HCI                     BIT(6)
 859 #define FEN_GPS                         BIT(7)
 860 #define FEN_BT                          BIT(8)
 861 #define FEN_WL                          BIT(9)
 862 #define FEN_PCI                         BIT(10)
 863 #define FEN_USB                         BIT(11)
 864 #define BTRF_HWPDN_N                    BIT(12)
 865 #define WLRF_HWPDN_N                    BIT(13)
 866 #define PDN_BT_N                        BIT(14)
 867 #define PDN_GPS_N                       BIT(15)
 868 #define BT_CTL_HWPDN                    BIT(16)
 869 #define GPS_CTL_HWPDN                   BIT(17)
 870 #define PPHY_SUSB                       BIT(20)
 871 #define UPHY_SUSB                       BIT(21)
 872 #define PCI_SUSEN                       BIT(22)
 873 #define USB_SUSEN                       BIT(23)
 874 #define RF_RL_ID                        (BIT(31) | BIT(30) | BIT(29) | BIT(28))
 875 
 876 /* 2SYS_CFG */
 877 #define RTL_ID                          BIT(23) /*  TestChip ID, 1:Test(RLE); 0:MP(RL) */
 878 
 879 /*      0x0100h ~ 0x01FFh       MACTOP General Configuration */
 880 
 881 /* 2 Function Enable Registers */
 882 /* 2 CR */
 883 
 884 #define HCI_TXDMA_EN                    BIT(0)
 885 #define HCI_RXDMA_EN                    BIT(1)
 886 #define TXDMA_EN                        BIT(2)
 887 #define RXDMA_EN                        BIT(3)
 888 #define PROTOCOL_EN                     BIT(4)
 889 #define SCHEDULE_EN                     BIT(5)
 890 #define MACTXEN                         BIT(6)
 891 #define MACRXEN                         BIT(7)
 892 #define ENSWBCN                         BIT(8)
 893 #define ENSEC                           BIT(9)
 894 #define CALTMR_EN                       BIT(10) /*  32k CAL TMR enable */
 895 
 896 /*  Network type */
 897 #define _NETTYPE(x)                     (((x) & 0x3) << 16)
 898 #define MASK_NETTYPE                    0x30000
 899 #define NT_NO_LINK                      0x0
 900 #define NT_LINK_AD_HOC                  0x1
 901 #define NT_LINK_AP                      0x2
 902 #define NT_AS_AP                        0x3
 903 
 904 /* 2 PBP - Page Size Register */
 905 #define GET_RX_PAGE_SIZE(value)         ((value) & 0xF)
 906 #define GET_TX_PAGE_SIZE(value)         (((value) & 0xF0) >> 4)
 907 #define _PSRX_MASK                      0xF
 908 #define _PSTX_MASK                      0xF0
 909 #define _PSRX(x)                        (x)
 910 #define _PSTX(x)                        ((x) << 4)
 911 
 912 #define PBP_64                          0x0
 913 #define PBP_128                         0x1
 914 #define PBP_256                         0x2
 915 #define PBP_512                         0x3
 916 #define PBP_1024                        0x4
 917 
 918 /* 2 TX/RXDMA */
 919 #define RXDMA_ARBBW_EN                  BIT(0)
 920 #define RXSHFT_EN                       BIT(1)
 921 #define RXDMA_AGG_EN                    BIT(2)
 922 #define QS_VO_QUEUE                     BIT(8)
 923 #define QS_VI_QUEUE                     BIT(9)
 924 #define QS_BE_QUEUE                     BIT(10)
 925 #define QS_BK_QUEUE                     BIT(11)
 926 #define QS_MANAGER_QUEUE                BIT(12)
 927 #define QS_HIGH_QUEUE                   BIT(13)
 928 
 929 #define HQSEL_VOQ                       BIT(0)
 930 #define HQSEL_VIQ                       BIT(1)
 931 #define HQSEL_BEQ                       BIT(2)
 932 #define HQSEL_BKQ                       BIT(3)
 933 #define HQSEL_MGTQ                      BIT(4)
 934 #define HQSEL_HIQ                       BIT(5)
 935 
 936 /*  For normal driver, 0x10C */
 937 #define _TXDMA_HIQ_MAP(x)               (((x) & 0x3) << 14)
 938 #define _TXDMA_MGQ_MAP(x)               (((x) & 0x3) << 12)
 939 #define _TXDMA_BKQ_MAP(x)               (((x) & 0x3) << 10)
 940 #define _TXDMA_BEQ_MAP(x)               (((x) & 0x3) << 8)
 941 #define _TXDMA_VIQ_MAP(x)               (((x) & 0x3) << 6)
 942 #define _TXDMA_VOQ_MAP(x)               (((x) & 0x3) << 4)
 943 
 944 #define QUEUE_LOW                       1
 945 #define QUEUE_NORMAL                    2
 946 #define QUEUE_HIGH                      3
 947 
 948 /* 2 TRXFF_BNDY */
 949 
 950 /* 2 LLT_INIT */
 951 #define _LLT_NO_ACTIVE                  0x0
 952 #define _LLT_WRITE_ACCESS               0x1
 953 #define _LLT_READ_ACCESS                0x2
 954 
 955 #define _LLT_INIT_DATA(x)               ((x) & 0xFF)
 956 #define _LLT_INIT_ADDR(x)               (((x) & 0xFF) << 8)
 957 #define _LLT_OP(x)                      (((x) & 0x3) << 30)
 958 #define _LLT_OP_VALUE(x)                (((x) >> 30) & 0x3)
 959 
 960 /*      0x0200h ~ 0x027Fh       TXDMA Configuration */
 961 /* 2RQPN */
 962 #define _HPQ(x)                         ((x) & 0xFF)
 963 #define _LPQ(x)                         (((x) & 0xFF) << 8)
 964 #define _PUBQ(x)                        (((x) & 0xFF) << 16)
 965 /*  NOTE: in RQPN_NPQ register */
 966 #define _NPQ(x)                         ((x) & 0xFF)
 967 
 968 #define HPQ_PUBLIC_DIS                  BIT(24)
 969 #define LPQ_PUBLIC_DIS                  BIT(25)
 970 #define LD_RQPN                         BIT(31)
 971 
 972 /* 2TDECTRL */
 973 #define BCN_VALID                       BIT(16)
 974 #define BCN_HEAD(x)                     (((x) & 0xFF) << 8)
 975 #define BCN_HEAD_MASK                   0xFF00
 976 
 977 /* 2 TDECTL */
 978 #define BLK_DESC_NUM_SHIFT              4
 979 #define BLK_DESC_NUM_MASK               0xF
 980 
 981 /* 2 TXDMA_OFFSET_CHK */
 982 #define DROP_DATA_EN                    BIT(9)
 983 
 984 /*      0x0280h ~ 0x028Bh       RX DMA Configuration */
 985 
 986 /*     REG_RXDMA_CONTROL, 0x0286h */
 987 
 988 /* 2 REG_RXPKT_NUM, 0x0284 */
 989 #define         RXPKT_RELEASE_POLL      BIT(16)
 990 #define RXDMA_IDLE                      BIT(17)
 991 #define RW_RELEASE_EN                   BIT(18)
 992 
 993 /*      0x0400h ~ 0x047Fh       Protocol Configuration */
 994 /* 2 FWHW_TXQ_CTRL */
 995 #define EN_AMPDU_RTY_NEW                BIT(7)
 996 
 997 /* 2 SPEC SIFS */
 998 #define _SPEC_SIFS_CCK(x)               ((x) & 0xFF)
 999 #define _SPEC_SIFS_OFDM(x)              (((x) & 0xFF) << 8)
1000 
1001 /* 2 RL */
1002 #define RETRY_LIMIT_SHORT_SHIFT         8
1003 #define RETRY_LIMIT_LONG_SHIFT          0
1004 
1005 /*      0x0500h ~ 0x05FFh       EDCA Configuration */
1006 
1007 /* 2 EDCA setting */
1008 #define AC_PARAM_TXOP_LIMIT_OFFSET      16
1009 #define AC_PARAM_ECW_MAX_OFFSET         12
1010 #define AC_PARAM_ECW_MIN_OFFSET         8
1011 #define AC_PARAM_AIFS_OFFSET            0
1012 
1013 #define _LRL(x)                 ((x) & 0x3F)
1014 #define _SRL(x)                 (((x) & 0x3F) << 8)
1015 
1016 /* 2 BCN_CTRL */
1017 #define EN_MBSSID               BIT(1)
1018 #define EN_TXBCN_RPT            BIT(2)
1019 #define EN_BCN_FUNCTION         BIT(3)
1020 #define DIS_TSF_UPDATE          BIT(3)
1021 
1022 /*  The same function but different bit field. */
1023 #define DIS_TSF_UDT0_NORMAL_CHIP        BIT(4)
1024 #define DIS_TSF_UDT0_TEST_CHIP  BIT(5)
1025 #define STOP_BCNQ               BIT(6)
1026 
1027 /* 2 ACMHWCTRL */
1028 #define AcmHw_HwEn              BIT(0)
1029 #define AcmHw_BeqEn             BIT(1)
1030 #define AcmHw_ViqEn             BIT(2)
1031 #define AcmHw_VoqEn             BIT(3)
1032 #define AcmHw_BeqStatus         BIT(4)
1033 #define AcmHw_ViqStatus         BIT(5)
1034 #define AcmHw_VoqStatus         BIT(6)
1035 
1036 /*      0x0600h ~ 0x07FFh       WMAC Configuration */
1037 /* 2APSD_CTRL */
1038 #define APSDOFF                 BIT(6)
1039 #define APSDOFF_STATUS          BIT(7)
1040 
1041 #define RATE_BITMAP_ALL         0xFFFFF
1042 
1043 /*  Only use CCK 1M rate for ACK */
1044 #define RATE_RRSR_CCK_ONLY_1M   0xFFFF1
1045 
1046 /* 2 TCR */
1047 #define TSFRST                  BIT(0)
1048 #define DIS_GCLK                BIT(1)
1049 #define PAD_SEL                 BIT(2)
1050 #define PWR_ST                  BIT(6)
1051 #define PWRBIT_OW_EN            BIT(7)
1052 #define ACRC                    BIT(8)
1053 #define CFENDFORM               BIT(9)
1054 #define ICV                     BIT(10)
1055 
1056 /* 2 RCR */
1057 #define AAP                     BIT(0)
1058 #define APM                     BIT(1)
1059 #define AM                      BIT(2)
1060 #define AB                      BIT(3)
1061 #define ADD3                    BIT(4)
1062 #define APWRMGT                 BIT(5)
1063 #define CBSSID                  BIT(6)
1064 #define CBSSID_DATA             BIT(6)
1065 #define CBSSID_BCN              BIT(7)
1066 #define ACRC32                  BIT(8)
1067 #define AICV                    BIT(9)
1068 #define ADF                     BIT(11)
1069 #define ACF                     BIT(12)
1070 #define AMF                     BIT(13)
1071 #define HTC_LOC_CTRL            BIT(14)
1072 #define UC_DATA_EN              BIT(16)
1073 #define BM_DATA_EN              BIT(17)
1074 #define MFBEN                   BIT(22)
1075 #define LSIGEN                  BIT(23)
1076 #define EnMBID                  BIT(24)
1077 #define APP_BASSN               BIT(27)
1078 #define APP_PHYSTS              BIT(28)
1079 #define APP_ICV                 BIT(29)
1080 #define APP_MIC                 BIT(30)
1081 #define APP_FCS                 BIT(31)
1082 
1083 /* 2 SECCFG */
1084 #define SCR_TxUseDK             BIT(0)  /* Force Tx Use Default Key */
1085 #define SCR_RxUseDK             BIT(1)  /* Force Rx Use Default Key */
1086 #define SCR_TxEncEnable         BIT(2)  /* Enable Tx Encryption */
1087 #define SCR_RxDecEnable         BIT(3)  /* Enable Rx Decryption */
1088 #define SCR_SKByA2              BIT(4)  /* Search kEY BY A2 */
1089 #define SCR_NoSKMC              BIT(5)  /* No Key Search Multicast */
1090 #define SCR_TXBCUSEDK           BIT(6)  /* Force Tx Bcast pkt Use Default Key */
1091 #define SCR_RXBCUSEDK           BIT(7)  /* Force Rx Bcast pkt Use Default Key */
1092 
1093 /*      RTL8188E SDIO Configuration */
1094 
1095 /*  I/O bus domain address mapping */
1096 #define SDIO_LOCAL_BASE                 0x10250000
1097 #define WLAN_IOREG_BASE                 0x10260000
1098 #define FIRMWARE_FIFO_BASE              0x10270000
1099 #define TX_HIQ_BASE                     0x10310000
1100 #define TX_MIQ_BASE                     0x10320000
1101 #define TX_LOQ_BASE                     0x10330000
1102 #define RX_RX0FF_BASE                   0x10340000
1103 
1104 /*  SDIO host local register space mapping. */
1105 #define SDIO_LOCAL_MSK                  0x0FFF
1106 #define WLAN_IOREG_MSK                  0x7FFF
1107 #define WLAN_FIFO_MSK                   0x1FFF  /*  Aggregation Length[12:0] */
1108 #define WLAN_RX0FF_MSK                  0x0003
1109 
1110 /*  Without ref to the SDIO Device ID */
1111 #define SDIO_WITHOUT_REF_DEVICE_ID      0
1112 #define SDIO_LOCAL_DEVICE_ID            0       /*  0b[16], 000b[15:13] */
1113 #define WLAN_TX_HIQ_DEVICE_ID           4       /*  0b[16], 100b[15:13] */
1114 #define WLAN_TX_MIQ_DEVICE_ID           5       /*  0b[16], 101b[15:13] */
1115 #define WLAN_TX_LOQ_DEVICE_ID           6       /*  0b[16], 110b[15:13] */
1116 #define WLAN_RX0FF_DEVICE_ID            7       /*  0b[16], 111b[15:13] */
1117 #define WLAN_IOREG_DEVICE_ID            8       /*  1b[16] */
1118 
1119 /*  SDIO Tx Free Page Index */
1120 #define HI_QUEUE_IDX                    0
1121 #define MID_QUEUE_IDX                   1
1122 #define LOW_QUEUE_IDX                   2
1123 #define PUBLIC_QUEUE_IDX                3
1124 
1125 #define SDIO_MAX_TX_QUEUE               3       /*  HIQ, MIQ and LOQ */
1126 #define SDIO_MAX_RX_QUEUE               1
1127 
1128 /*  SDIO Tx Control */
1129 #define SDIO_REG_TX_CTRL                0x0000
1130 /*  SDIO Host Interrupt Mask */
1131 #define SDIO_REG_HIMR                   0x0014
1132 /*  SDIO Host Interrupt Service Routine */
1133 #define SDIO_REG_HISR                   0x0018
1134 /*  HCI Current Power Mode */
1135 #define SDIO_REG_HCPWM                  0x0019
1136 /*  RXDMA Request Length */
1137 #define SDIO_REG_RX0_REQ_LEN            0x001C
1138 /*  Free Tx Buffer Page */
1139 #define SDIO_REG_FREE_TXPG              0x0020
1140 /*  HCI Current Power Mode 1 */
1141 #define SDIO_REG_HCPWM1                 0x0024
1142 /*  HCI Current Power Mode 2 */
1143 #define SDIO_REG_HCPWM2                 0x0026
1144 /*  HTSF Informaion */
1145 #define SDIO_REG_HTSFR_INFO             0x0030
1146 /*  HCI Request Power Mode 1 */
1147 #define SDIO_REG_HRPWM1                 0x0080
1148 /*  HCI Request Power Mode 2 */
1149 #define SDIO_REG_HRPWM2                 0x0082
1150 /*  HCI Power Save Clock */
1151 #define SDIO_REG_HPS_CLKR               0x0084
1152 /*  SDIO HCI Suspend Control */
1153 #define SDIO_REG_HSUS_CTRL              0x0086
1154 /*  SDIO Host Extension Interrupt Mask Always */
1155 #define SDIO_REG_HIMR_ON                0x0090
1156 /*  SDIO Host Extension Interrupt Status Always */
1157 #define SDIO_REG_HISR_ON                0x0091
1158 
1159 #define SDIO_HIMR_DISABLED                      0
1160 
1161 /*  RTL8188E SDIO Host Interrupt Mask Register */
1162 #define SDIO_HIMR_RX_REQUEST_MSK                BIT(0)
1163 #define SDIO_HIMR_AVAL_MSK                      BIT(1)
1164 #define SDIO_HIMR_TXERR_MSK                     BIT(2)
1165 #define SDIO_HIMR_RXERR_MSK                     BIT(3)
1166 #define SDIO_HIMR_TXFOVW_MSK                    BIT(4)
1167 #define SDIO_HIMR_RXFOVW_MSK                    BIT(5)
1168 #define SDIO_HIMR_TXBCNOK_MSK                   BIT(6)
1169 #define SDIO_HIMR_TXBCNERR_MSK                  BIT(7)
1170 #define SDIO_HIMR_BCNERLY_INT_MSK               BIT(16)
1171 #define SDIO_HIMR_C2HCMD_MSK                    BIT(17)
1172 #define SDIO_HIMR_CPWM1_MSK                     BIT(18)
1173 #define SDIO_HIMR_CPWM2_MSK                     BIT(19)
1174 #define SDIO_HIMR_HSISR_IND_MSK                 BIT(20)
1175 #define SDIO_HIMR_GTINT3_IND_MSK                BIT(21)
1176 #define SDIO_HIMR_GTINT4_IND_MSK                BIT(22)
1177 #define SDIO_HIMR_PSTIMEOUT_MSK                 BIT(23)
1178 #define SDIO_HIMR_OCPINT_MSK                    BIT(24)
1179 #define SDIO_HIMR_ATIMEND_MSK                   BIT(25)
1180 #define SDIO_HIMR_ATIMEND_E_MSK                 BIT(26)
1181 #define SDIO_HIMR_CTWEND_MSK                    BIT(27)
1182 
1183 /* RTL8188E SDIO Specific */
1184 #define SDIO_HIMR_MCU_ERR_MSK                   BIT(28)
1185 #define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK          BIT(29)
1186 
1187 /*  SDIO Host Interrupt Service Routine */
1188 #define SDIO_HISR_RX_REQUEST                    BIT(0)
1189 #define SDIO_HISR_AVAL                          BIT(1)
1190 #define SDIO_HISR_TXERR                         BIT(2)
1191 #define SDIO_HISR_RXERR                         BIT(3)
1192 #define SDIO_HISR_TXFOVW                        BIT(4)
1193 #define SDIO_HISR_RXFOVW                        BIT(5)
1194 #define SDIO_HISR_TXBCNOK                       BIT(6)
1195 #define SDIO_HISR_TXBCNERR                      BIT(7)
1196 #define SDIO_HISR_BCNERLY_INT                   BIT(16)
1197 #define SDIO_HISR_C2HCMD                        BIT(17)
1198 #define SDIO_HISR_CPWM1                         BIT(18)
1199 #define SDIO_HISR_CPWM2                         BIT(19)
1200 #define SDIO_HISR_HSISR_IND                     BIT(20)
1201 #define SDIO_HISR_GTINT3_IND                    BIT(21)
1202 #define SDIO_HISR_GTINT4_IND                    BIT(22)
1203 #define SDIO_HISR_PSTIME                        BIT(23)
1204 #define SDIO_HISR_OCPINT                        BIT(24)
1205 #define SDIO_HISR_ATIMEND                       BIT(25)
1206 #define SDIO_HISR_ATIMEND_E                     BIT(26)
1207 #define SDIO_HISR_CTWEND                        BIT(27)
1208 
1209 /* RTL8188E SDIO Specific */
1210 #define SDIO_HISR_MCU_ERR                       BIT(28)
1211 #define SDIO_HISR_TSF_BIT32_TOGGLE              BIT(29)
1212 
1213 #define MASK_SDIO_HISR_CLEAR                            \
1214         (SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\
1215          SDIO_HISR_RXFOVW | SDIO_HISR_TXBCNOK | SDIO_HISR_TXBCNERR |\
1216          SDIO_HISR_C2HCMD | SDIO_HISR_CPWM1 | SDIO_HISR_CPWM2 |\
1217          SDIO_HISR_HSISR_IND | SDIO_HISR_GTINT3_IND | SDIO_HISR_GTINT4_IND |\
1218          SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT)
1219 
1220 /*  SDIO HCI Suspend Control Register */
1221 #define HCI_RESUME_PWR_RDY              BIT(1)
1222 #define HCI_SUS_CTRL                    BIT(0)
1223 
1224 /*  SDIO Tx FIFO related */
1225 /*  The number of Tx FIFO free page */
1226 #define SDIO_TX_FREE_PG_QUEUE                   4
1227 #define SDIO_TX_FIFO_PAGE_SZ                    128
1228 
1229 /*      0xFE00h ~ 0xFE55h       USB Configuration */
1230 
1231 /* 2 USB Information (0xFE17) */
1232 #define USB_IS_HIGH_SPEED                       0
1233 #define USB_IS_FULL_SPEED                       1
1234 #define USB_SPEED_MASK                          BIT(5)
1235 
1236 #define USB_NORMAL_SIE_EP_MASK                  0xF
1237 #define USB_NORMAL_SIE_EP_SHIFT                 4
1238 
1239 /* 2 Special Option */
1240 #define USB_AGG_EN                              BIT(3)
1241 
1242 /*  0; Use interrupt endpoint to upload interrupt pkt */
1243 /*  1; Use bulk endpoint to upload interrupt pkt, */
1244 #define INT_BULK_SEL                            BIT(4)
1245 
1246 /* 2REG_C2HEVT_CLEAR */
1247 /*  Set by driver and notify FW that the driver has read
1248  *  the C2H command message
1249  */
1250 #define C2H_EVT_HOST_CLOSE      0x00
1251 /*  Set by FW indicating that FW had set the C2H command
1252  *  message and it's not yet read by driver.
1253  */
1254 #define C2H_EVT_FW_CLOSE        0xFF
1255 
1256 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
1257 /*  Enable GPIO[9] as WiFi HW PDn source */
1258 #define WL_HWPDN_EN                             BIT(0)
1259 /*  WiFi HW PDn polarity control */
1260 #define WL_HWPDN_SL                             BIT(1)
1261 /*  WiFi function enable */
1262 #define WL_FUNC_EN                              BIT(2)
1263 /*  Enable GPIO[9] as WiFi RF HW PDn source */
1264 #define WL_HWROF_EN                             BIT(3)
1265 /*  Enable GPIO[11] as BT HW PDn source */
1266 #define BT_HWPDN_EN                             BIT(16)
1267 /*  BT HW PDn polarity control */
1268 #define BT_HWPDN_SL                             BIT(17)
1269 /*  BT function enable */
1270 #define BT_FUNC_EN                              BIT(18)
1271 /*  Enable GPIO[11] as BT/GPS RF HW PDn source */
1272 #define BT_HWROF_EN                             BIT(19)
1273 /*  Enable GPIO[10] as GPS HW PDn source */
1274 #define GPS_HWPDN_EN                            BIT(20)
1275 /*  GPS HW PDn polarity control */
1276 #define GPS_HWPDN_SL                            BIT(21)
1277 /*  GPS function enable */
1278 #define GPS_FUNC_EN                             BIT(22)
1279 
1280 /* 3 REG_LIFECTRL_CTRL */
1281 #define HAL92C_EN_PKT_LIFE_TIME_BK              BIT(3)
1282 #define HAL92C_EN_PKT_LIFE_TIME_BE              BIT(2)
1283 #define HAL92C_EN_PKT_LIFE_TIME_VI              BIT(1)
1284 #define HAL92C_EN_PKT_LIFE_TIME_VO              BIT(0)
1285 
1286 #define HAL92C_MSDU_LIFE_TIME_UNIT              128     /*  in us */
1287 
1288 /*  General definitions */
1289 #define LAST_ENTRY_OF_TX_PKT_BUFFER             176 /*  22k 22528 bytes */
1290 
1291 #define POLLING_LLT_THRESHOLD                   20
1292 #define POLLING_READY_TIMEOUT_COUNT             1000
1293 /*  GPIO BIT */
1294 #define HAL_8192C_HW_GPIO_WPS_BIT               BIT(2)
1295 
1296 /*      8192C EEPROM/EFUSE share register definition. */
1297 
1298 /*      EEPROM/Efuse PG Offset for 88EE/88EU/88ES */
1299 #define EEPROM_TX_PWR_INX_88E                   0x10
1300 
1301 #define EEPROM_ChannelPlan_88E                  0xB8
1302 #define EEPROM_XTAL_88E                         0xB9
1303 #define EEPROM_THERMAL_METER_88E                0xBA
1304 #define EEPROM_IQK_LCK_88E                      0xBB
1305 
1306 #define EEPROM_RF_BOARD_OPTION_88E              0xC1
1307 #define EEPROM_RF_FEATURE_OPTION_88E            0xC2
1308 #define EEPROM_RF_BT_SETTING_88E                0xC3
1309 #define EEPROM_VERSION_88E                      0xC4
1310 #define EEPROM_CUSTOMERID_88E                   0xC5
1311 #define EEPROM_RF_ANTENNA_OPT_88E               0xC9
1312 
1313 /*  RTL88EE */
1314 #define EEPROM_MAC_ADDR_88EE                    0xD0
1315 #define EEPROM_VID_88EE                         0xD6
1316 #define EEPROM_DID_88EE                         0xD8
1317 #define EEPROM_SVID_88EE                        0xDA
1318 #define EEPROM_SMID_88EE                        0xDC
1319 
1320 /* RTL88EU */
1321 #define EEPROM_MAC_ADDR_88EU                    0xD7
1322 #define EEPROM_VID_88EU                         0xD0
1323 #define EEPROM_PID_88EU                         0xD2
1324 #define EEPROM_USB_OPTIONAL_FUNCTION0           0xD4
1325 
1326 /*  RTL88ES */
1327 #define EEPROM_MAC_ADDR_88ES                    0x11A
1328 
1329 /*              EEPROM/Efuse Value Type */
1330 #define EETYPE_TX_PWR                           0x0
1331 
1332 /*  Default Value for EEPROM or EFUSE!!! */
1333 #define EEPROM_Default_TSSI                     0x0
1334 #define EEPROM_Default_TxPowerDiff              0x0
1335 #define EEPROM_Default_CrystalCap               0x5
1336 /*  Default: 2X2, RTL8192CE(QFPN68) */
1337 #define EEPROM_Default_BoardType                0x02
1338 #define EEPROM_Default_TxPower                  0x1010
1339 #define EEPROM_Default_HT2T_TxPwr               0x10
1340 
1341 #define EEPROM_Default_LegacyHTTxPowerDiff      0x3
1342 #define EEPROM_Default_ThermalMeter             0x12
1343 
1344 #define EEPROM_Default_AntTxPowerDiff           0x0
1345 #define EEPROM_Default_TxPwDiff_CrystalCap      0x5
1346 #define EEPROM_Default_TxPowerLevel             0x2A
1347 
1348 #define EEPROM_Default_HT40_2SDiff              0x0
1349 /*  HT20<->40 default Tx Power Index Difference */
1350 #define EEPROM_Default_HT20_Diff                2
1351 #define EEPROM_Default_LegacyHTTxPowerDiff      0x3
1352 #define EEPROM_Default_HT40_PwrMaxOffset        0
1353 #define EEPROM_Default_HT20_PwrMaxOffset        0
1354 
1355 #define EEPROM_Default_CrystalCap_88E           0x20
1356 #define EEPROM_Default_ThermalMeter_88E         0x18
1357 
1358 /* New EFUSE default value */
1359 #define         EEPROM_DEFAULT_24G_INDEX        0x2D
1360 #define         EEPROM_DEFAULT_24G_HT20_DIFF    0X02
1361 #define         EEPROM_DEFAULT_24G_OFDM_DIFF    0X04
1362 
1363 #define         EEPROM_DEFAULT_5G_INDEX         0X2A
1364 #define         EEPROM_DEFAULT_5G_HT20_DIFF     0X00
1365 #define         EEPROM_DEFAULT_5G_OFDM_DIFF     0X04
1366 
1367 #define         EEPROM_DEFAULT_DIFF             0XFE
1368 #define EEPROM_DEFAULT_CHANNEL_PLAN             0x7F
1369 #define EEPROM_DEFAULT_BOARD_OPTION             0x00
1370 #define EEPROM_DEFAULT_FEATURE_OPTION           0x00
1371 #define EEPROM_DEFAULT_BT_OPTION                0x10
1372 
1373 /*  For debug */
1374 #define EEPROM_Default_PID                      0x1234
1375 #define EEPROM_Default_VID                      0x5678
1376 #define EEPROM_Default_CustomerID               0xAB
1377 #define EEPROM_Default_CustomerID_8188E         0x00
1378 #define EEPROM_Default_SubCustomerID            0xCD
1379 #define EEPROM_Default_Version                  0
1380 
1381 #define EEPROM_CHANNEL_PLAN_FCC                 0x0
1382 #define EEPROM_CHANNEL_PLAN_IC                  0x1
1383 #define EEPROM_CHANNEL_PLAN_ETSI                0x2
1384 #define EEPROM_CHANNEL_PLAN_SPA                 0x3
1385 #define EEPROM_CHANNEL_PLAN_FRANCE              0x4
1386 #define EEPROM_CHANNEL_PLAN_MKK                 0x5
1387 #define EEPROM_CHANNEL_PLAN_MKK1                0x6
1388 #define EEPROM_CHANNEL_PLAN_ISRAEL              0x7
1389 #define EEPROM_CHANNEL_PLAN_TELEC               0x8
1390 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA         0x9
1391 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13       0xA
1392 #define EEPROM_CHANNEL_PLAN_NCC                 0xB
1393 #define EEPROM_USB_OPTIONAL1                    0xE
1394 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK          0x80
1395 
1396 #define EEPROM_CID_DEFAULT              0x0
1397 #define EEPROM_CID_TOSHIBA              0x4
1398 #define EEPROM_CID_CCX                  0x10 /*  CCX test. */
1399 #define EEPROM_CID_QMI                  0x0D
1400 #define EEPROM_CID_WHQL                 0xFE
1401 #define RTL_EEPROM_ID                   0x8129
1402 
1403 #endif /* __RTL8188E_SPEC_H__ */