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15 #ifndef __ODM_REGDEFINE11N_H__
16 #define __ODM_REGDEFINE11N_H__
17
18 #define ODM_REG_TX_ANT_CTRL_11N 0x80C
19 #define ODM_REG_RX_DEFAULT_A_11N 0x858
20 #define ODM_REG_ANTSEL_CTRL_11N 0x860
21 #define ODM_REG_RX_ANT_CTRL_11N 0x864
22 #define ODM_REG_PIN_CTRL_11N 0x870
23 #define ODM_REG_SC_CNT_11N 0x8C4
24
25 #define ODM_REG_ANT_MAPPING1_11N 0x914
26
27 #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
28 #define ODM_REG_CCK_CCA_11N 0xA0A
29 #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
30 #define ODM_REG_CCK_FA_RST_11N 0xA2C
31 #define ODM_REG_CCK_FA_MSB_11N 0xA58
32 #define ODM_REG_CCK_FA_LSB_11N 0xA5C
33 #define ODM_REG_CCK_CCA_CNT_11N 0xA60
34 #define ODM_REG_BB_PWR_SAV4_11N 0xA74
35
36 #define ODM_REG_LNA_SWITCH_11N 0xB2C
37
38 #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
39 #define ODM_REG_IGI_A_11N 0xC50
40 #define ODM_REG_ANTDIV_PARA1_11N 0xCA4
41 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
42
43 #define ODM_REG_OFDM_FA_RSTD_11N 0xD00
44 #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
45 #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
46 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
47
48 #define ODM_REG_ANTSEL_PIN_11N 0x4C
49 #define ODM_REG_RESP_TX_11N 0x6D8
50
51 #define ODM_BIT_IGI_11N 0x0000007F
52
53 #endif