root/drivers/staging/mt7621-pci/pci-mt7621.c

/* [<][>][^][v][top][bottom][index][help] */

DEFINITIONS

This source file includes following definitions.
  1. pcie_read
  2. pcie_write
  3. pcie_port_read
  4. pcie_port_write
  5. mt7621_pci_get_cfgaddr
  6. mt7621_pcie_map_bus
  7. read_config
  8. write_config
  9. mt7621_perst_gpio_pcie_assert
  10. mt7621_perst_gpio_pcie_deassert
  11. mt7621_pcie_port_is_linkup
  12. mt7621_pcie_port_clk_disable
  13. mt7621_control_assert
  14. mt7621_control_deassert
  15. mt7621_reset_port
  16. setup_cm_memory_region
  17. mt7621_pci_parse_request_of_pci_ranges
  18. mt7621_pcie_parse_port
  19. mt7621_pcie_parse_dt
  20. mt7621_pcie_init_port
  21. mt7621_pcie_init_ports
  22. mt7621_pcie_enable_port
  23. mt7621_pcie_enable_ports
  24. mt7621_pcie_init_virtual_bridges
  25. mt7621_pcie_request_resources
  26. mt7621_pcie_register_host
  27. mt7621_pci_probe
  28. mt7621_pci_init

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * BRIEF MODULE DESCRIPTION
   4  *     PCI init for Ralink RT2880 solution
   5  *
   6  * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
   7  *
   8  * May 2007 Bruce Chang
   9  * Initial Release
  10  *
  11  * May 2009 Bruce Chang
  12  * support RT2880/RT3883 PCIe
  13  *
  14  * May 2011 Bruce Chang
  15  * support RT6855/MT7620 PCIe
  16  */
  17 
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_pci.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/pci.h>
  29 #include <linux/phy/phy.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/reset.h>
  32 #include <linux/sys_soc.h>
  33 #include <mt7621.h>
  34 #include <ralink_regs.h>
  35 
  36 #include "../../pci/pci.h"
  37 
  38 /* sysctl */
  39 #define MT7621_GPIO_MODE                0x60
  40 
  41 /* MediaTek specific configuration registers */
  42 #define PCIE_FTS_NUM                    0x70c
  43 #define PCIE_FTS_NUM_MASK               GENMASK(15, 8)
  44 #define PCIE_FTS_NUM_L0(x)              (((x) & 0xff) << 8)
  45 
  46 /* rt_sysc_membase relative registers */
  47 #define RALINK_CLKCFG1                  0x30
  48 #define RALINK_PCIE_CLK_GEN             0x7c
  49 #define RALINK_PCIE_CLK_GEN1            0x80
  50 
  51 /* Host-PCI bridge registers */
  52 #define RALINK_PCI_PCICFG_ADDR          0x0000
  53 #define RALINK_PCI_PCIMSK_ADDR          0x000C
  54 #define RALINK_PCI_CONFIG_ADDR          0x0020
  55 #define RALINK_PCI_CONFIG_DATA          0x0024
  56 #define RALINK_PCI_MEMBASE              0x0028
  57 #define RALINK_PCI_IOBASE               0x002C
  58 
  59 /* PCICFG virtual bridges */
  60 #define MT7621_BR0_MASK                 GENMASK(19, 16)
  61 #define MT7621_BR1_MASK                 GENMASK(23, 20)
  62 #define MT7621_BR2_MASK                 GENMASK(27, 24)
  63 #define MT7621_BR_ALL_MASK              GENMASK(27, 16)
  64 #define MT7621_BR0_SHIFT                16
  65 #define MT7621_BR1_SHIFT                20
  66 #define MT7621_BR2_SHIFT                24
  67 
  68 /* PCIe RC control registers */
  69 #define MT7621_PCIE_OFFSET              0x2000
  70 #define MT7621_NEXT_PORT                0x1000
  71 
  72 #define RALINK_PCI_BAR0SETUP_ADDR       0x0010
  73 #define RALINK_PCI_IMBASEBAR0_ADDR      0x0018
  74 #define RALINK_PCI_ID                   0x0030
  75 #define RALINK_PCI_CLASS                0x0034
  76 #define RALINK_PCI_SUBID                0x0038
  77 #define RALINK_PCI_STATUS               0x0050
  78 
  79 /* Some definition values */
  80 #define PCIE_REVISION_ID                BIT(0)
  81 #define PCIE_CLASS_CODE                 (0x60400 << 8)
  82 #define PCIE_BAR_MAP_MAX                GENMASK(30, 16)
  83 #define PCIE_BAR_ENABLE                 BIT(0)
  84 #define PCIE_PORT_INT_EN(x)             BIT(20 + (x))
  85 #define PCIE_PORT_CLK_EN(x)             BIT(24 + (x))
  86 #define PCIE_PORT_LINKUP                BIT(0)
  87 
  88 #define PCIE_CLK_GEN_EN                 BIT(31)
  89 #define PCIE_CLK_GEN_DIS                0
  90 #define PCIE_CLK_GEN1_DIS               GENMASK(30, 24)
  91 #define PCIE_CLK_GEN1_EN                (BIT(27) | BIT(25))
  92 #define MEMORY_BASE                     0x0
  93 #define PERST_MODE_MASK                 GENMASK(11, 10)
  94 #define PERST_MODE_GPIO                 BIT(10)
  95 #define PERST_DELAY_US                  1000
  96 
  97 /**
  98  * struct mt7621_pcie_port - PCIe port information
  99  * @base: I/O mapped register base
 100  * @list: port list
 101  * @pcie: pointer to PCIe host info
 102  * @phy: pointer to PHY control block
 103  * @pcie_rst: pointer to port reset control
 104  * @slot: port slot
 105  * @enabled: indicates if port is enabled
 106  */
 107 struct mt7621_pcie_port {
 108         void __iomem *base;
 109         struct list_head list;
 110         struct mt7621_pcie *pcie;
 111         struct phy *phy;
 112         struct reset_control *pcie_rst;
 113         u32 slot;
 114         bool enabled;
 115 };
 116 
 117 /**
 118  * struct mt7621_pcie - PCIe host information
 119  * @base: IO Mapped Register Base
 120  * @io: IO resource
 121  * @mem: non-prefetchable memory resource
 122  * @busn: bus range
 123  * @offset: IO / Memory offset
 124  * @dev: Pointer to PCIe device
 125  * @ports: pointer to PCIe port information
 126  * @perst: gpio reset
 127  * @rst: pointer to pcie reset
 128  * @resets_inverted: depends on chip revision
 129  * reset lines are inverted.
 130  */
 131 struct mt7621_pcie {
 132         void __iomem *base;
 133         struct device *dev;
 134         struct resource io;
 135         struct resource mem;
 136         struct resource busn;
 137         struct {
 138                 resource_size_t mem;
 139                 resource_size_t io;
 140         } offset;
 141         struct list_head ports;
 142         struct gpio_desc *perst;
 143         struct reset_control *rst;
 144         bool resets_inverted;
 145 };
 146 
 147 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
 148 {
 149         return readl(pcie->base + reg);
 150 }
 151 
 152 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
 153 {
 154         writel(val, pcie->base + reg);
 155 }
 156 
 157 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
 158 {
 159         return readl(port->base + reg);
 160 }
 161 
 162 static inline void pcie_port_write(struct mt7621_pcie_port *port,
 163                                    u32 val, u32 reg)
 164 {
 165         writel(val, port->base + reg);
 166 }
 167 
 168 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 169                                          unsigned int func, unsigned int where)
 170 {
 171         return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
 172                 (func << 8) | (where & 0xfc) | 0x80000000;
 173 }
 174 
 175 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
 176                                          unsigned int devfn, int where)
 177 {
 178         struct mt7621_pcie *pcie = bus->sysdata;
 179         u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 180                                              PCI_FUNC(devfn), where);
 181 
 182         writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
 183 
 184         return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
 185 }
 186 
 187 struct pci_ops mt7621_pci_ops = {
 188         .map_bus        = mt7621_pcie_map_bus,
 189         .read           = pci_generic_config_read,
 190         .write          = pci_generic_config_write,
 191 };
 192 
 193 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 194 {
 195         u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 196 
 197         pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
 198         return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
 199 }
 200 
 201 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
 202                          u32 reg, u32 val)
 203 {
 204         u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 205 
 206         pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
 207         pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
 208 }
 209 
 210 static inline void mt7621_perst_gpio_pcie_assert(struct mt7621_pcie *pcie)
 211 {
 212         gpiod_set_value(pcie->perst, 0);
 213         mdelay(PERST_DELAY_US);
 214 }
 215 
 216 static inline void mt7621_perst_gpio_pcie_deassert(struct mt7621_pcie *pcie)
 217 {
 218         gpiod_set_value(pcie->perst, 1);
 219         mdelay(PERST_DELAY_US);
 220 }
 221 
 222 static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
 223 {
 224         return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
 225 }
 226 
 227 static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
 228 {
 229         rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
 230 }
 231 
 232 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
 233 {
 234         struct mt7621_pcie *pcie = port->pcie;
 235 
 236         if (pcie->resets_inverted)
 237                 reset_control_assert(port->pcie_rst);
 238         else
 239                 reset_control_deassert(port->pcie_rst);
 240 }
 241 
 242 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
 243 {
 244         struct mt7621_pcie *pcie = port->pcie;
 245 
 246         if (pcie->resets_inverted)
 247                 reset_control_deassert(port->pcie_rst);
 248         else
 249                 reset_control_assert(port->pcie_rst);
 250 }
 251 
 252 static void mt7621_reset_port(struct mt7621_pcie_port *port)
 253 {
 254         mt7621_control_assert(port);
 255         msleep(100);
 256         mt7621_control_deassert(port);
 257 }
 258 
 259 static void setup_cm_memory_region(struct mt7621_pcie *pcie)
 260 {
 261         struct resource *mem_resource = &pcie->mem;
 262         struct device *dev = pcie->dev;
 263         resource_size_t mask;
 264 
 265         if (mips_cps_numiocu(0)) {
 266                 /*
 267                  * FIXME: hardware doesn't accept mask values with 1s after
 268                  * 0s (e.g. 0xffef), so it would be great to warn if that's
 269                  * about to happen
 270                  */
 271                 mask = ~(mem_resource->end - mem_resource->start);
 272 
 273                 write_gcr_reg1_base(mem_resource->start);
 274                 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
 275                 dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
 276                         (unsigned long long)read_gcr_reg1_base(),
 277                         (unsigned long long)read_gcr_reg1_mask());
 278         }
 279 }
 280 
 281 static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
 282 {
 283         struct device *dev = pcie->dev;
 284         struct device_node *node = dev->of_node;
 285         struct of_pci_range_parser parser;
 286         struct of_pci_range range;
 287         int err;
 288 
 289         if (of_pci_range_parser_init(&parser, node)) {
 290                 dev_err(dev, "missing \"ranges\" property\n");
 291                 return -EINVAL;
 292         }
 293 
 294         for_each_of_pci_range(&parser, &range) {
 295                 struct resource *res = NULL;
 296 
 297                 switch (range.flags & IORESOURCE_TYPE_BITS) {
 298                 case IORESOURCE_IO:
 299                         ioremap(range.cpu_addr, range.size);
 300                         res = &pcie->io;
 301                         pcie->offset.io = 0x00000000UL;
 302                         break;
 303                 case IORESOURCE_MEM:
 304                         res = &pcie->mem;
 305                         pcie->offset.mem = 0x00000000UL;
 306                         break;
 307                 }
 308 
 309                 if (res)
 310                         of_pci_range_to_resource(&range, node, res);
 311         }
 312 
 313         err = of_pci_parse_bus_range(node, &pcie->busn);
 314         if (err < 0) {
 315                 dev_err(dev, "failed to parse bus ranges property: %d\n", err);
 316                 pcie->busn.name = node->name;
 317                 pcie->busn.start = 0;
 318                 pcie->busn.end = 0xff;
 319                 pcie->busn.flags = IORESOURCE_BUS;
 320         }
 321 
 322         return 0;
 323 }
 324 
 325 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
 326                                   struct device_node *node,
 327                                   int slot)
 328 {
 329         struct mt7621_pcie_port *port;
 330         struct device *dev = pcie->dev;
 331         struct device_node *pnode = dev->of_node;
 332         struct resource regs;
 333         char name[10];
 334         int err;
 335 
 336         port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
 337         if (!port)
 338                 return -ENOMEM;
 339 
 340         err = of_address_to_resource(pnode, slot + 1, &regs);
 341         if (err) {
 342                 dev_err(dev, "missing \"reg\" property\n");
 343                 return err;
 344         }
 345 
 346         port->base = devm_ioremap_resource(dev, &regs);
 347         if (IS_ERR(port->base))
 348                 return PTR_ERR(port->base);
 349 
 350         snprintf(name, sizeof(name), "pcie%d", slot);
 351         port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
 352         if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
 353                 dev_err(dev, "failed to get pcie%d reset control\n", slot);
 354                 return PTR_ERR(port->pcie_rst);
 355         }
 356 
 357         snprintf(name, sizeof(name), "pcie-phy%d", slot);
 358         port->phy = devm_phy_get(dev, name);
 359         if (IS_ERR(port->phy))
 360                 return PTR_ERR(port->phy);
 361 
 362         port->slot = slot;
 363         port->pcie = pcie;
 364 
 365         INIT_LIST_HEAD(&port->list);
 366         list_add_tail(&port->list, &pcie->ports);
 367 
 368         return 0;
 369 }
 370 
 371 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 372 {
 373         struct device *dev = pcie->dev;
 374         struct device_node *node = dev->of_node, *child;
 375         struct resource regs;
 376         int err;
 377 
 378         pcie->perst = devm_gpiod_get(dev, "perst", GPIOD_OUT_HIGH);
 379         if (IS_ERR(pcie->perst)) {
 380                 dev_err(dev, "failed to get gpio perst\n");
 381                 return PTR_ERR(pcie->perst);
 382         }
 383 
 384         err = of_address_to_resource(node, 0, &regs);
 385         if (err) {
 386                 dev_err(dev, "missing \"reg\" property\n");
 387                 return err;
 388         }
 389 
 390         pcie->base = devm_ioremap_resource(dev, &regs);
 391         if (IS_ERR(pcie->base))
 392                 return PTR_ERR(pcie->base);
 393 
 394         pcie->rst = devm_reset_control_get_exclusive(dev, "pcie");
 395         if (PTR_ERR(pcie->rst) == -EPROBE_DEFER) {
 396                 dev_err(dev, "failed to get pcie reset control\n");
 397                 return PTR_ERR(pcie->rst);
 398         }
 399 
 400         for_each_available_child_of_node(node, child) {
 401                 int slot;
 402 
 403                 err = of_pci_get_devfn(child);
 404                 if (err < 0) {
 405                         of_node_put(child);
 406                         dev_err(dev, "failed to parse devfn: %d\n", err);
 407                         return err;
 408                 }
 409 
 410                 slot = PCI_SLOT(err);
 411 
 412                 err = mt7621_pcie_parse_port(pcie, child, slot);
 413                 if (err) {
 414                         of_node_put(child);
 415                         return err;
 416                 }
 417         }
 418 
 419         return 0;
 420 }
 421 
 422 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 423 {
 424         struct mt7621_pcie *pcie = port->pcie;
 425         struct device *dev = pcie->dev;
 426         u32 slot = port->slot;
 427         int err;
 428 
 429         /*
 430          * Any MT7621 Ralink pcie controller that doesn't have 0x0101 at
 431          * the end of the chip_id has inverted PCI resets.
 432          */
 433         mt7621_reset_port(port);
 434 
 435         err = phy_init(port->phy);
 436         if (err) {
 437                 dev_err(dev, "failed to initialize port%d phy\n", slot);
 438                 return err;
 439         }
 440 
 441         err = phy_power_on(port->phy);
 442         if (err) {
 443                 dev_err(dev, "failed to power on port%d phy\n", slot);
 444                 phy_exit(port->phy);
 445                 return err;
 446         }
 447 
 448         port->enabled = true;
 449 
 450         return 0;
 451 }
 452 
 453 static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
 454 {
 455         struct device *dev = pcie->dev;
 456         struct mt7621_pcie_port *port, *tmp;
 457         u32 val = 0;
 458         int err;
 459 
 460         rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
 461 
 462         mt7621_perst_gpio_pcie_assert(pcie);
 463 
 464         list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
 465                 u32 slot = port->slot;
 466 
 467                 err = mt7621_pcie_init_port(port);
 468                 if (err) {
 469                         dev_err(dev, "Initiating port %d failed\n", slot);
 470                         list_del(&port->list);
 471                 } else {
 472                         val = read_config(pcie, slot, PCIE_FTS_NUM);
 473                         dev_info(dev, "Port %d N_FTS = %x\n", slot,
 474                                  (unsigned int)val);
 475                 }
 476         }
 477 
 478         reset_control_assert(pcie->rst);
 479 
 480         mt7621_perst_gpio_pcie_deassert(pcie);
 481 
 482         list_for_each_entry(port, &pcie->ports, list) {
 483                 u32 slot = port->slot;
 484 
 485                 if (!mt7621_pcie_port_is_linkup(port)) {
 486                         dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
 487                                 slot);
 488                         phy_power_off(port->phy);
 489                         mt7621_control_assert(port);
 490                         mt7621_pcie_port_clk_disable(port);
 491                         port->enabled = false;
 492                 }
 493         }
 494 
 495         rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
 496         rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
 497         rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
 498         rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
 499         msleep(50);
 500         reset_control_deassert(pcie->rst);
 501 }
 502 
 503 static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
 504 {
 505         struct mt7621_pcie *pcie = port->pcie;
 506         u32 slot = port->slot;
 507         u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
 508         u32 val;
 509 
 510         /* enable pcie interrupt */
 511         val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
 512         val |= PCIE_PORT_INT_EN(slot);
 513         pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 514 
 515         /* map 2G DDR region */
 516         pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
 517                    offset + RALINK_PCI_BAR0SETUP_ADDR);
 518         pcie_write(pcie, MEMORY_BASE,
 519                    offset + RALINK_PCI_IMBASEBAR0_ADDR);
 520 
 521         /* configure class code and revision ID */
 522         pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
 523                    offset + RALINK_PCI_CLASS);
 524 }
 525 
 526 static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
 527 {
 528         struct device *dev = pcie->dev;
 529         struct mt7621_pcie_port *port;
 530         u8 num_slots_enabled = 0;
 531         u32 slot;
 532         u32 val;
 533 
 534         list_for_each_entry(port, &pcie->ports, list) {
 535                 if (port->enabled) {
 536                         mt7621_pcie_enable_port(port);
 537                         dev_info(dev, "PCIE%d enabled\n", num_slots_enabled);
 538                         num_slots_enabled++;
 539                 }
 540         }
 541 
 542         for (slot = 0; slot < num_slots_enabled; slot++) {
 543                 val = read_config(pcie, slot, PCI_COMMAND);
 544                 val |= PCI_COMMAND_MASTER;
 545                 write_config(pcie, slot, PCI_COMMAND, val);
 546                 /* configure RC FTS number to 250 when it leaves L0s */
 547                 val = read_config(pcie, slot, PCIE_FTS_NUM);
 548                 val &= ~PCIE_FTS_NUM_MASK;
 549                 val |= PCIE_FTS_NUM_L0(0x50);
 550                 write_config(pcie, slot, PCIE_FTS_NUM, val);
 551         }
 552 }
 553 
 554 static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
 555 {
 556         u32 pcie_link_status = 0;
 557         u32 val = 0;
 558         struct mt7621_pcie_port *port;
 559 
 560         list_for_each_entry(port, &pcie->ports, list) {
 561                 u32 slot = port->slot;
 562 
 563                 if (port->enabled)
 564                         pcie_link_status |= BIT(slot);
 565         }
 566 
 567         if (pcie_link_status == 0)
 568                 return -1;
 569 
 570         /*
 571          * pcie(2/1/0) link status      pcie2_num       pcie1_num       pcie0_num
 572          * 3'b000                       x               x               x
 573          * 3'b001                       x               x               0
 574          * 3'b010                       x               0               x
 575          * 3'b011                       x               1               0
 576          * 3'b100                       0               x               x
 577          * 3'b101                       1               x               0
 578          * 3'b110                       1               0               x
 579          * 3'b111                       2               1               0
 580          */
 581         switch (pcie_link_status) {
 582         case 2:
 583                 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
 584                 val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK);
 585                 val |= 0x1 << MT7621_BR0_SHIFT;
 586                 val |= 0x0 << MT7621_BR1_SHIFT;
 587                 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 588                 break;
 589         case 4:
 590                 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
 591                 val &= ~MT7621_BR_ALL_MASK;
 592                 val |= 0x1 << MT7621_BR0_SHIFT;
 593                 val |= 0x2 << MT7621_BR1_SHIFT;
 594                 val |= 0x0 << MT7621_BR2_SHIFT;
 595                 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 596                 break;
 597         case 5:
 598                 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
 599                 val &= ~MT7621_BR_ALL_MASK;
 600                 val |= 0x0 << MT7621_BR0_SHIFT;
 601                 val |= 0x2 << MT7621_BR1_SHIFT;
 602                 val |= 0x1 << MT7621_BR2_SHIFT;
 603                 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 604                 break;
 605         case 6:
 606                 val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
 607                 val &= ~MT7621_BR_ALL_MASK;
 608                 val |= 0x2 << MT7621_BR0_SHIFT;
 609                 val |= 0x0 << MT7621_BR1_SHIFT;
 610                 val |= 0x1 << MT7621_BR2_SHIFT;
 611                 pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 612                 break;
 613         }
 614 
 615         return 0;
 616 }
 617 
 618 static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
 619                                          struct list_head *res)
 620 {
 621         struct device *dev = pcie->dev;
 622 
 623         pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
 624         pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
 625         pci_add_resource(res, &pcie->busn);
 626 
 627         return devm_request_pci_bus_resources(dev, res);
 628 }
 629 
 630 static int mt7621_pcie_register_host(struct pci_host_bridge *host,
 631                                      struct list_head *res)
 632 {
 633         struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
 634 
 635         list_splice_init(res, &host->windows);
 636         host->busnr = pcie->busn.start;
 637         host->dev.parent = pcie->dev;
 638         host->ops = &mt7621_pci_ops;
 639         host->map_irq = of_irq_parse_and_map_pci;
 640         host->swizzle_irq = pci_common_swizzle;
 641         host->sysdata = pcie;
 642 
 643         return pci_host_probe(host);
 644 }
 645 
 646 static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
 647         { .soc_id = "mt7621", .revision = "E2" }
 648 };
 649 
 650 static int mt7621_pci_probe(struct platform_device *pdev)
 651 {
 652         struct device *dev = &pdev->dev;
 653         const struct soc_device_attribute *attr;
 654         struct mt7621_pcie *pcie;
 655         struct pci_host_bridge *bridge;
 656         int err;
 657         LIST_HEAD(res);
 658 
 659         if (!dev->of_node)
 660                 return -ENODEV;
 661 
 662         bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 663         if (!bridge)
 664                 return -ENOMEM;
 665 
 666         pcie = pci_host_bridge_priv(bridge);
 667         pcie->dev = dev;
 668         platform_set_drvdata(pdev, pcie);
 669         INIT_LIST_HEAD(&pcie->ports);
 670 
 671         attr = soc_device_match(mt7621_pci_quirks_match);
 672         if (attr)
 673                 pcie->resets_inverted = true;
 674 
 675         err = mt7621_pcie_parse_dt(pcie);
 676         if (err) {
 677                 dev_err(dev, "Parsing DT failed\n");
 678                 return err;
 679         }
 680 
 681         /* set resources limits */
 682         iomem_resource.start = 0;
 683         iomem_resource.end = ~0UL; /* no limit */
 684         ioport_resource.start = 0;
 685         ioport_resource.end = ~0UL; /* no limit */
 686 
 687         mt7621_pcie_init_ports(pcie);
 688 
 689         err = mt7621_pcie_init_virtual_bridges(pcie);
 690         if (err) {
 691                 dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
 692                 return 0;
 693         }
 694 
 695         mt7621_pcie_enable_ports(pcie);
 696 
 697         err = mt7621_pci_parse_request_of_pci_ranges(pcie);
 698         if (err) {
 699                 dev_err(dev, "Error requesting pci resources from ranges");
 700                 return err;
 701         }
 702 
 703         setup_cm_memory_region(pcie);
 704 
 705         err = mt7621_pcie_request_resources(pcie, &res);
 706         if (err) {
 707                 dev_err(dev, "Error requesting resources\n");
 708                 return err;
 709         }
 710 
 711         err = mt7621_pcie_register_host(bridge, &res);
 712         if (err) {
 713                 dev_err(dev, "Error registering host\n");
 714                 return err;
 715         }
 716 
 717         return 0;
 718 }
 719 
 720 static const struct of_device_id mt7621_pci_ids[] = {
 721         { .compatible = "mediatek,mt7621-pci" },
 722         {},
 723 };
 724 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
 725 
 726 static struct platform_driver mt7621_pci_driver = {
 727         .probe = mt7621_pci_probe,
 728         .driver = {
 729                 .name = "mt7621-pci",
 730                 .of_match_table = of_match_ptr(mt7621_pci_ids),
 731         },
 732 };
 733 
 734 static int __init mt7621_pci_init(void)
 735 {
 736         return platform_driver_register(&mt7621_pci_driver);
 737 }
 738 
 739 module_init(mt7621_pci_init);

/* [<][>][^][v][top][bottom][index][help] */