root/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*****************************************************************************
   3  *      Copyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.
   4  *
   5  * Module:      __INC_HAL8192SPHYREG_H
   6  *
   7  *
   8  * Note:        1. Define PMAC/BB register map
   9  *                      2. Define RF register map
  10  *                      3. PMAC/BB register bit mask.
  11  *                      4. RF reg bit mask.
  12  *                      5. Other BB/RF relative definition.
  13  *
  14  *
  15  * Export:      Constants, macro, functions(API), global variables(None).
  16  *
  17  * Abbrev:
  18  *
  19  * History:
  20  *      Data                    Who             Remark
  21  *      08/07/2007      MHC             1. Porting from 9x series PHYCFG.h.
  22  *                                              2. Reorganize code architecture.
  23  *      09/25/2008      MH              1. Add RL6052 register definition
  24  *
  25  *****************************************************************************/
  26 #ifndef __RTL871X_MP_PHY_REGDEF_H
  27 #define __RTL871X_MP_PHY_REGDEF_H
  28 
  29 
  30 /*--------------------------Define Parameters-------------------------------*/
  31 
  32 /*============================================================
  33  *       8192S Regsiter offset definition
  34  *============================================================
  35  *
  36  *
  37  * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
  38  * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
  39  * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
  40  * 3. RF register 0x00-2E
  41  * 4. Bit Mask for BB/RF register
  42  * 5. Other definition for BB/RF R/W
  43  *
  44  * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
  45  * 1. Page1(0x100)
  46  */
  47 #define rPMAC_Reset                     0x100
  48 #define rPMAC_TxStart                   0x104
  49 #define rPMAC_TxLegacySIG               0x108
  50 #define rPMAC_TxHTSIG1                  0x10c
  51 #define rPMAC_TxHTSIG2                  0x110
  52 #define rPMAC_PHYDebug                  0x114
  53 #define rPMAC_TxPacketNum               0x118
  54 #define rPMAC_TxIdle                    0x11c
  55 #define rPMAC_TxMACHeader0              0x120
  56 #define rPMAC_TxMACHeader1              0x124
  57 #define rPMAC_TxMACHeader2              0x128
  58 #define rPMAC_TxMACHeader3              0x12c
  59 #define rPMAC_TxMACHeader4              0x130
  60 #define rPMAC_TxMACHeader5              0x134
  61 #define rPMAC_TxDataType                0x138
  62 #define rPMAC_TxRandomSeed              0x13c
  63 #define rPMAC_CCKPLCPPreamble           0x140
  64 #define rPMAC_CCKPLCPHeader             0x144
  65 #define rPMAC_CCKCRC16                  0x148
  66 #define rPMAC_OFDMRxCRC32OK             0x170
  67 #define rPMAC_OFDMRxCRC32Er             0x174
  68 #define rPMAC_OFDMRxParityEr            0x178
  69 #define rPMAC_OFDMRxCRC8Er              0x17c
  70 #define rPMAC_CCKCRxRC16Er              0x180
  71 #define rPMAC_CCKCRxRC32Er              0x184
  72 #define rPMAC_CCKCRxRC32OK              0x188
  73 #define rPMAC_TxStatus                  0x18c
  74 
  75 /*
  76  * 2. Page2(0x200)
  77  *
  78  * The following two definition are only used for USB interface.
  79  *#define RF_BB_CMD_ADDR        0x02c0  // RF/BB read/write command address.
  80  *#define RF_BB_CMD_DATA        0x02c4  // RF/BB read/write command data.
  81  *
  82  *
  83  * 3. Page8(0x800)
  84  */
  85 #define rFPGA0_RFMOD                    0x800   /*RF mode & CCK TxSC RF
  86                                                  * BW Setting??
  87                                                  */
  88 #define rFPGA0_TxInfo                   0x804   /* Status report?? */
  89 #define rFPGA0_PSDFunction              0x808
  90 #define rFPGA0_TxGainStage              0x80c   /* Set TX PWR init gain? */
  91 #define rFPGA0_RFTiming1                0x810   /* Useless now */
  92 #define rFPGA0_RFTiming2                0x814
  93 #define rFPGA0_XA_HSSIParameter1        0x820   /* RF 3 wire register */
  94 #define rFPGA0_XA_HSSIParameter2        0x824
  95 #define rFPGA0_XB_HSSIParameter1        0x828
  96 #define rFPGA0_XB_HSSIParameter2        0x82c
  97 #define rFPGA0_XC_HSSIParameter1        0x830
  98 #define rFPGA0_XC_HSSIParameter2        0x834
  99 #define rFPGA0_XD_HSSIParameter1        0x838
 100 #define rFPGA0_XD_HSSIParameter2        0x83c
 101 #define rFPGA0_XA_LSSIParameter         0x840
 102 #define rFPGA0_XB_LSSIParameter         0x844
 103 #define rFPGA0_XC_LSSIParameter         0x848
 104 #define rFPGA0_XD_LSSIParameter         0x84c
 105 
 106 #define rFPGA0_RFWakeUpParameter        0x850   /* Useless now */
 107 #define rFPGA0_RFSleepUpParameter       0x854
 108 
 109 #define rFPGA0_XAB_SwitchControl        0x858   /* RF Channel switch */
 110 #define rFPGA0_XCD_SwitchControl        0x85c
 111 
 112 #define rFPGA0_XA_RFInterfaceOE         0x860   /* RF Channel switch */
 113 #define rFPGA0_XB_RFInterfaceOE         0x864
 114 #define rFPGA0_XC_RFInterfaceOE         0x868
 115 #define rFPGA0_XD_RFInterfaceOE         0x86c
 116 #define rFPGA0_XAB_RFInterfaceSW        0x870   /* RF Interface Software Ctrl */
 117 #define rFPGA0_XCD_RFInterfaceSW        0x874
 118 
 119 #define rFPGA0_XAB_RFParameter          0x878   /* RF Parameter */
 120 #define rFPGA0_XCD_RFParameter          0x87c
 121 
 122 #define rFPGA0_AnalogParameter1         0x880   /* Crystal cap setting
 123                                                  * RF-R/W protection
 124                                                  * for parameter4??
 125                                                  */
 126 #define rFPGA0_AnalogParameter2         0x884
 127 #define rFPGA0_AnalogParameter3         0x888   /* Useless now */
 128 #define rFPGA0_AnalogParameter4         0x88c
 129 
 130 #define rFPGA0_XA_LSSIReadBack          0x8a0   /* Tranceiver LSSI Readback */
 131 #define rFPGA0_XB_LSSIReadBack          0x8a4
 132 #define rFPGA0_XC_LSSIReadBack          0x8a8
 133 #define rFPGA0_XD_LSSIReadBack          0x8ac
 134 
 135 #define rFPGA0_PSDReport                0x8b4   /* Useless now */
 136 #define rFPGA0_XAB_RFInterfaceRB        0x8e0   /* Useless now */
 137 #define rFPGA0_XCD_RFInterfaceRB        0x8e4   /* Useless now */
 138 
 139 /*
 140  * 4. Page9(0x900)
 141  */
 142 #define rFPGA1_RFMOD                    0x900   /* RF mode & OFDM TxSC */
 143 
 144 #define rFPGA1_TxBlock                  0x904   /* Useless now */
 145 #define rFPGA1_DebugSelect              0x908   /* Useless now */
 146 #define rFPGA1_TxInfo                   0x90c   /* Useless now */
 147 
 148 /*
 149  * 5. PageA(0xA00)
 150  *
 151  * Set Control channel to upper or lower.
 152  * These settings are required only for 40MHz
 153  */
 154 #define rCCK0_System                    0xa00
 155 
 156 #define rCCK0_AFESetting                0xa04   /* Disable init gain now */
 157 #define rCCK0_CCA                       0xa08   /* Disable init gain now */
 158 
 159 #define rCCK0_RxAGC1                    0xa0c
 160 /* AGC default value, saturation level
 161  * Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now.
 162  * Not the same as 90 series
 163  */
 164 #define rCCK0_RxAGC2                    0xa10   /* AGC & DAGC */
 165 
 166 #define rCCK0_RxHP                      0xa14
 167 
 168 #define rCCK0_DSPParameter1             0xa18   /* Timing recovery & Channel
 169                                                  * estimation threshold
 170                                                  */
 171 #define rCCK0_DSPParameter2             0xa1c   /* SQ threshold */
 172 
 173 #define rCCK0_TxFilter1                 0xa20
 174 #define rCCK0_TxFilter2                 0xa24
 175 #define rCCK0_DebugPort                 0xa28   /* debug port and Tx filter3 */
 176 #define rCCK0_FalseAlarmReport          0xa2c   /* 0xa2d useless now 0xa30-a4f
 177                                                  * channel report
 178                                                  */
 179 #define rCCK0_TRSSIReport               0xa50
 180 #define rCCK0_RxReport                  0xa54   /* 0xa57 */
 181 #define rCCK0_FACounterLower            0xa5c   /* 0xa5b */
 182 #define rCCK0_FACounterUpper            0xa58   /* 0xa5c */
 183 
 184 /*
 185  * 6. PageC(0xC00)
 186  */
 187 #define rOFDM0_LSTF                     0xc00
 188 #define rOFDM0_TRxPathEnable            0xc04
 189 #define rOFDM0_TRMuxPar                 0xc08
 190 #define rOFDM0_TRSWIsolation            0xc0c
 191 
 192 /*RxIQ DC offset, Rx digital filter, DC notch filter */
 193 #define rOFDM0_XARxAFE                  0xc10
 194 #define rOFDM0_XARxIQImbalance          0xc14  /* RxIQ imbalance matrix */
 195 #define rOFDM0_XBRxAFE                  0xc18
 196 #define rOFDM0_XBRxIQImbalance          0xc1c
 197 #define rOFDM0_XCRxAFE                  0xc20
 198 #define rOFDM0_XCRxIQImbalance          0xc24
 199 #define rOFDM0_XDRxAFE                  0xc28
 200 #define rOFDM0_XDRxIQImbalance          0xc2c
 201 
 202 #define rOFDM0_RxDetector1              0xc30  /* PD,BW & SBD DM tune
 203                                                 * init gain
 204                                                 */
 205 #define rOFDM0_RxDetector2              0xc34  /* SBD & Fame Sync. */
 206 #define rOFDM0_RxDetector3              0xc38  /* Frame Sync. */
 207 #define rOFDM0_RxDetector4              0xc3c  /* PD, SBD, Frame Sync &
 208                                                 * Short-GI
 209                                                 */
 210 
 211 #define rOFDM0_RxDSP                    0xc40  /* Rx Sync Path */
 212 #define rOFDM0_CFOandDAGC               0xc44  /* CFO & DAGC */
 213 #define rOFDM0_CCADropThreshold         0xc48 /* CCA Drop threshold */
 214 #define rOFDM0_ECCAThreshold            0xc4c /* energy CCA */
 215 
 216 #define rOFDM0_XAAGCCore1               0xc50   /* DIG */
 217 #define rOFDM0_XAAGCCore2               0xc54
 218 #define rOFDM0_XBAGCCore1               0xc58
 219 #define rOFDM0_XBAGCCore2               0xc5c
 220 #define rOFDM0_XCAGCCore1               0xc60
 221 #define rOFDM0_XCAGCCore2               0xc64
 222 #define rOFDM0_XDAGCCore1               0xc68
 223 #define rOFDM0_XDAGCCore2               0xc6c
 224 #define rOFDM0_AGCParameter1            0xc70
 225 #define rOFDM0_AGCParameter2            0xc74
 226 #define rOFDM0_AGCRSSITable             0xc78
 227 #define rOFDM0_HTSTFAGC                 0xc7c
 228 
 229 #define rOFDM0_XATxIQImbalance          0xc80   /* TX PWR TRACK and DIG */
 230 #define rOFDM0_XATxAFE                  0xc84
 231 #define rOFDM0_XBTxIQImbalance          0xc88
 232 #define rOFDM0_XBTxAFE                  0xc8c
 233 #define rOFDM0_XCTxIQImbalance          0xc90
 234 #define rOFDM0_XCTxAFE                  0xc94
 235 #define rOFDM0_XDTxIQImbalance          0xc98
 236 #define rOFDM0_XDTxAFE                  0xc9c
 237 
 238 #define rOFDM0_RxHPParameter            0xce0
 239 #define rOFDM0_TxPseudoNoiseWgt         0xce4
 240 #define rOFDM0_FrameSync                0xcf0
 241 #define rOFDM0_DFSReport                0xcf4
 242 #define rOFDM0_TxCoeff1                 0xca4
 243 #define rOFDM0_TxCoeff2                 0xca8
 244 #define rOFDM0_TxCoeff3                 0xcac
 245 #define rOFDM0_TxCoeff4                 0xcb0
 246 #define rOFDM0_TxCoeff5                 0xcb4
 247 #define rOFDM0_TxCoeff6                 0xcb8
 248 
 249 /*
 250  * 7. PageD(0xD00)
 251  */
 252 #define rOFDM1_LSTF                     0xd00
 253 #define rOFDM1_TRxPathEnable            0xd04
 254 
 255 #define rOFDM1_CFO                      0xd08   /* No setting now */
 256 #define rOFDM1_CSI1                     0xd10
 257 #define rOFDM1_SBD                      0xd14
 258 #define rOFDM1_CSI2                     0xd18
 259 #define rOFDM1_CFOTracking              0xd2c
 260 #define rOFDM1_TRxMesaure1              0xd34
 261 #define rOFDM1_IntfDet                  0xd3c
 262 #define rOFDM1_PseudoNoiseStateAB       0xd50
 263 #define rOFDM1_PseudoNoiseStateCD       0xd54
 264 #define rOFDM1_RxPseudoNoiseWgt         0xd58
 265 
 266 #define rOFDM_PHYCounter1               0xda0  /* cca, parity fail */
 267 #define rOFDM_PHYCounter2               0xda4  /* rate illegal, crc8 fail */
 268 #define rOFDM_PHYCounter3               0xda8  /* MCS not support */
 269 #define rOFDM_ShortCFOAB                0xdac  /* No setting now */
 270 #define rOFDM_ShortCFOCD                0xdb0
 271 #define rOFDM_LongCFOAB                 0xdb4
 272 #define rOFDM_LongCFOCD                 0xdb8
 273 #define rOFDM_TailCFOAB                 0xdbc
 274 #define rOFDM_TailCFOCD                 0xdc0
 275 #define rOFDM_PWMeasure1                0xdc4
 276 #define rOFDM_PWMeasure2                0xdc8
 277 #define rOFDM_BWReport                  0xdcc
 278 #define rOFDM_AGCReport                 0xdd0
 279 #define rOFDM_RxSNR                     0xdd4
 280 #define rOFDM_RxEVMCSI                  0xdd8
 281 #define rOFDM_SIGReport                 0xddc
 282 
 283 /*
 284  * 8. PageE(0xE00)
 285  */
 286 #define rTxAGC_Rate18_06                0xe00
 287 #define rTxAGC_Rate54_24                0xe04
 288 #define rTxAGC_CCK_Mcs32                0xe08
 289 #define rTxAGC_Mcs03_Mcs00              0xe10
 290 #define rTxAGC_Mcs07_Mcs04              0xe14
 291 #define rTxAGC_Mcs11_Mcs08              0xe18
 292 #define rTxAGC_Mcs15_Mcs12              0xe1c
 293 
 294 /* Analog- control in RX_WAIT_CCA : REG: EE0
 295  * [Analog- Power & Control Register]
 296  */
 297 #define         rRx_Wait_CCCA           0xe70
 298 #define rAnapar_Ctrl_BB                 0xee0
 299 
 300 /*
 301  * 7. RF Register 0x00-0x2E (RF 8256)
 302  *    RF-0222D 0x00-3F
 303  *
 304  * Zebra1
 305  */
 306 #define rZebra1_HSSIEnable              0x0     /* Useless now */
 307 #define rZebra1_TRxEnable1              0x1
 308 #define rZebra1_TRxEnable2              0x2
 309 #define rZebra1_AGC                     0x4
 310 #define rZebra1_ChargePump              0x5
 311 #define rZebra1_Channel                 0x7     /* RF channel switch */
 312 #define rZebra1_TxGain                  0x8     /* Useless now */
 313 #define rZebra1_TxLPF                   0x9
 314 #define rZebra1_RxLPF                   0xb
 315 #define rZebra1_RxHPFCorner             0xc
 316 
 317 /* Zebra4 */
 318 #define rGlobalCtrl                     0       /* Useless now */
 319 #define rRTL8256_TxLPF                  19
 320 #define rRTL8256_RxLPF                  11
 321 
 322 /* RTL8258 */
 323 #define rRTL8258_TxLPF                  0x11    /* Useless now */
 324 #define rRTL8258_RxLPF                  0x13
 325 #define rRTL8258_RSSILPF                0xa
 326 
 327 /* RL6052 Register definition */
 328 #define RF_AC                           0x00
 329 #define RF_IQADJ_G1                     0x01
 330 #define RF_IQADJ_G2                     0x02
 331 #define RF_POW_TRSW                     0x05
 332 
 333 #define RF_GAIN_RX                      0x06
 334 #define RF_GAIN_TX                      0x07
 335 
 336 #define RF_TXM_IDAC                     0x08
 337 #define RF_BS_IQGEN                     0x0F
 338 
 339 #define RF_MODE1                        0x10
 340 #define RF_MODE2                        0x11
 341 
 342 #define RF_RX_AGC_HP                    0x12
 343 #define RF_TX_AGC                       0x13
 344 #define RF_BIAS                         0x14
 345 #define RF_IPA                          0x15
 346 #define RF_POW_ABILITY                  0x17
 347 #define RF_MODE_AG                      0x18
 348 #define rRfChannel                      0x18    /* RF channel and BW switch */
 349 #define RF_CHNLBW                       0x18    /* RF channel and BW switch */
 350 #define RF_TOP                          0x19
 351 #define RF_RX_G1                        0x1A
 352 #define RF_RX_G2                        0x1B
 353 #define RF_RX_BB2                       0x1C
 354 #define RF_RX_BB1                       0x1D
 355 
 356 #define RF_RCK1                         0x1E
 357 #define RF_RCK2                         0x1F
 358 
 359 #define RF_TX_G1                        0x20
 360 #define RF_TX_G2                        0x21
 361 #define RF_TX_G3                        0x22
 362 
 363 #define RF_TX_BB1                       0x23
 364 #define RF_T_METER                      0x24
 365 
 366 #define RF_SYN_G1                       0x25    /* RF TX Power control */
 367 #define RF_SYN_G2                       0x26    /* RF TX Power control */
 368 #define RF_SYN_G3                       0x27    /* RF TX Power control */
 369 #define RF_SYN_G4                       0x28    /* RF TX Power control */
 370 #define RF_SYN_G5                       0x29    /* RF TX Power control */
 371 #define RF_SYN_G6                       0x2A    /* RF TX Power control */
 372 #define RF_SYN_G7                       0x2B    /* RF TX Power control */
 373 #define RF_SYN_G8                       0x2C    /* RF TX Power control */
 374 
 375 #define RF_RCK_OS                       0x30    /* RF TX PA control */
 376 
 377 #define RF_TXPA_G1                      0x31    /* RF TX PA control */
 378 #define RF_TXPA_G2                      0x32    /* RF TX PA control */
 379 #define RF_TXPA_G3                      0x33    /* RF TX PA control */
 380 
 381 /*
 382  * Bit Mask
 383  *
 384  * 1. Page1(0x100)
 385  */
 386 #define bBBResetB                       0x100   /* Useless now? */
 387 #define bGlobalResetB                   0x200
 388 #define bOFDMTxStart                    0x4
 389 #define bCCKTxStart                     0x8
 390 #define bCRC32Debug                     0x100
 391 #define bPMACLoopback                   0x10
 392 #define bTxLSIG                         0xffffff
 393 #define bOFDMTxRate                     0xf
 394 #define bOFDMTxReserved                 0x10
 395 #define bOFDMTxLength                   0x1ffe0
 396 #define bOFDMTxParity                   0x20000
 397 #define bTxHTSIG1                       0xffffff
 398 #define bTxHTMCSRate                    0x7f
 399 #define bTxHTBW                         0x80
 400 #define bTxHTLength                     0xffff00
 401 #define bTxHTSIG2                       0xffffff
 402 #define bTxHTSmoothing                  0x1
 403 #define bTxHTSounding                   0x2
 404 #define bTxHTReserved                   0x4
 405 #define bTxHTAggreation                 0x8
 406 #define bTxHTSTBC                       0x30
 407 #define bTxHTAdvanceCoding              0x40
 408 #define bTxHTShortGI                    0x80
 409 #define bTxHTNumberHT_LTF               0x300
 410 #define bTxHTCRC8                       0x3fc00
 411 #define bCounterReset                   0x10000
 412 #define bNumOfOFDMTx                    0xffff
 413 #define bNumOfCCKTx                     0xffff0000
 414 #define bTxIdleInterval                 0xffff
 415 #define bOFDMService                    0xffff0000
 416 #define bTxMACHeader                    0xffffffff
 417 #define bTxDataInit                     0xff
 418 #define bTxHTMode                       0x100
 419 #define bTxDataType                     0x30000
 420 #define bTxRandomSeed                   0xffffffff
 421 #define bCCKTxPreamble                  0x1
 422 #define bCCKTxSFD                       0xffff0000
 423 #define bCCKTxSIG                       0xff
 424 #define bCCKTxService                   0xff00
 425 #define bCCKLengthExt                   0x8000
 426 #define bCCKTxLength                    0xffff0000
 427 #define bCCKTxCRC16                     0xffff
 428 #define bCCKTxStatus                    0x1
 429 #define bOFDMTxStatus                   0x2
 430 #define IS_BB_REG_OFFSET_92S(_Offset)   ((_Offset >= 0x800) && \
 431                                         (_Offset <= 0xfff))
 432 
 433 /* 2. Page8(0x800) */
 434 #define bRFMOD                  0x1     /* Reg 0x800 rFPGA0_RFMOD */
 435 #define bJapanMode              0x2
 436 #define bCCKTxSC                0x30
 437 #define bCCKEn                  0x1000000
 438 #define bOFDMEn                 0x2000000
 439 
 440 #define bOFDMRxADCPhase         0x10000 /* Useless now */
 441 #define bOFDMTxDACPhase         0x40000
 442 #define bXATxAGC                0x3f
 443 #define bXBTxAGC                0xf00   /* Reg 80c rFPGA0_TxGainStage */
 444 #define bXCTxAGC                0xf000
 445 #define bXDTxAGC                0xf0000
 446 
 447 #define bPAStart                0xf0000000      /* Useless now */
 448 #define bTRStart                0x00f00000
 449 #define bRFStart                0x0000f000
 450 #define bBBStart                0x000000f0
 451 #define bBBCCKStart             0x0000000f
 452 #define bPAEnd                  0xf          /* Reg0x814 */
 453 #define bTREnd                  0x0f000000
 454 #define bRFEnd                  0x000f0000
 455 #define bCCAMask                0x000000f0   /* T2R */
 456 #define bR2RCCAMask             0x00000f00
 457 #define bHSSI_R2TDelay          0xf8000000
 458 #define bHSSI_T2RDelay          0xf80000
 459 #define bContTxHSSI             0x400     /* change gain at continue Tx */
 460 #define bIGFromCCK              0x200
 461 #define bAGCAddress             0x3f
 462 #define bRxHPTx                 0x7000
 463 #define bRxHPT2R                0x38000
 464 #define bRxHPCCKIni             0xc0000
 465 #define bAGCTxCode              0xc00000
 466 #define bAGCRxCode              0x300000
 467 #define b3WireDataLength        0x800   /* Reg 0x820~84f rFPGA0_XA_HSSIParm1 */
 468 #define b3WireAddressLength     0x400
 469 #define b3WireRFPowerDown       0x1     /* Useless now */
 470 #define b5GPAPEPolarity         0x40000000
 471 #define b2GPAPEPolarity         0x80000000
 472 #define bRFSW_TxDefaultAnt      0x3
 473 #define bRFSW_TxOptionAnt       0x30
 474 #define bRFSW_RxDefaultAnt      0x300
 475 #define bRFSW_RxOptionAnt       0x3000
 476 #define bRFSI_3WireData         0x1
 477 #define bRFSI_3WireClock        0x2
 478 #define bRFSI_3WireLoad         0x4
 479 #define bRFSI_3WireRW           0x8
 480 #define bRFSI_3Wire             0xf
 481 #define bRFSI_RFENV             0x10    /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
 482 #define bRFSI_TRSW              0x20    /* Useless now */
 483 #define bRFSI_TRSWB             0x40
 484 #define bRFSI_ANTSW             0x100
 485 #define bRFSI_ANTSWB            0x200
 486 #define bRFSI_PAPE              0x400
 487 #define bRFSI_PAPE5G            0x800
 488 #define bBandSelect             0x1
 489 #define bHTSIG2_GI              0x80
 490 #define bHTSIG2_Smoothing       0x01
 491 #define bHTSIG2_Sounding        0x02
 492 #define bHTSIG2_Aggreaton       0x08
 493 #define bHTSIG2_STBC            0x30
 494 #define bHTSIG2_AdvCoding       0x40
 495 #define bHTSIG2_NumOfHTLTF      0x300
 496 #define bHTSIG2_CRC8            0x3fc
 497 #define bHTSIG1_MCS             0x7f
 498 #define bHTSIG1_BandWidth       0x80
 499 #define bHTSIG1_HTLength        0xffff
 500 #define bLSIG_Rate              0xf
 501 #define bLSIG_Reserved          0x10
 502 #define bLSIG_Length            0x1fffe
 503 #define bLSIG_Parity            0x20
 504 #define bCCKRxPhase             0x4
 505 #define bLSSIReadAddress        0x7f800000   /* T65 RF */
 506 #define bLSSIReadEdge           0x80000000   /* LSSI "Read" edge signal */
 507 #define bLSSIReadBackData       0xfffff         /* T65 RF */
 508 #define bLSSIReadOKFlag         0x1000  /* Useless now */
 509 #define bCCKSampleRate          0x8       /*0: 44MHz, 1:88MHz*/
 510 #define bRegulator0Standby      0x1
 511 #define bRegulatorPLLStandby    0x2
 512 #define bRegulator1Standby      0x4
 513 #define bPLLPowerUp             0x8
 514 #define bDPLLPowerUp            0x10
 515 #define bDA10PowerUp            0x20
 516 #define bAD7PowerUp             0x200
 517 #define bDA6PowerUp             0x2000
 518 #define bXtalPowerUp            0x4000
 519 #define b40MDClkPowerUP         0x8000
 520 #define bDA6DebugMode           0x20000
 521 #define bDA6Swing               0x380000
 522 
 523 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
 524 #define bADClkPhase             0x4000000
 525 
 526 #define b80MClkDelay            0x18000000      /* Useless */
 527 #define bAFEWatchDogEnable      0x20000000
 528 
 529 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
 530 #define bXtalCap01              0xc0000000
 531 #define bXtalCap23              0x3
 532 #define bXtalCap92x             0x0f000000
 533 #define bXtalCap                0x0f000000
 534 #define bIntDifClkEnable        0x400   /* Useless */
 535 #define bExtSigClkEnable        0x800
 536 #define bBandgapMbiasPowerUp    0x10000
 537 #define bAD11SHGain             0xc0000
 538 #define bAD11InputRange         0x700000
 539 #define bAD11OPCurrent          0x3800000
 540 #define bIPathLoopback          0x4000000
 541 #define bQPathLoopback          0x8000000
 542 #define bAFELoopback            0x10000000
 543 #define bDA10Swing              0x7e0
 544 #define bDA10Reverse            0x800
 545 #define bDAClkSource            0x1000
 546 #define bAD7InputRange          0x6000
 547 #define bAD7Gain                0x38000
 548 #define bAD7OutputCMMode        0x40000
 549 #define bAD7InputCMMode         0x380000
 550 #define bAD7Current             0xc00000
 551 #define bRegulatorAdjust        0x7000000
 552 #define bAD11PowerUpAtTx        0x1
 553 #define bDA10PSAtTx             0x10
 554 #define bAD11PowerUpAtRx        0x100
 555 #define bDA10PSAtRx             0x1000
 556 #define bCCKRxAGCFormat         0x200
 557 #define bPSDFFTSamplepPoint     0xc000
 558 #define bPSDAverageNum          0x3000
 559 #define bIQPathControl          0xc00
 560 #define bPSDFreq                0x3ff
 561 #define bPSDAntennaPath         0x30
 562 #define bPSDIQSwitch            0x40
 563 #define bPSDRxTrigger           0x400000
 564 #define bPSDTxTrigger           0x80000000
 565 #define bPSDSineToneScale       0x7f000000
 566 #define bPSDReport              0xffff
 567 
 568 /* 3. Page9(0x900) */
 569 #define bOFDMTxSC               0x30000000      /* Useless */
 570 #define bCCKTxOn                0x1
 571 #define bOFDMTxOn               0x2
 572 #define bDebugPage              0xfff  /* reset debug page and HWord, LWord */
 573 #define bDebugItem              0xff   /* reset debug page and LWord */
 574 #define bAntL                   0x10
 575 #define bAntNonHT               0x100
 576 #define bAntHT1                 0x1000
 577 #define bAntHT2                 0x10000
 578 #define bAntHT1S1               0x100000
 579 #define bAntNonHTS1             0x1000000
 580 
 581 /* 4. PageA(0xA00) */
 582 #define bCCKBBMode              0x3     /* Useless */
 583 #define bCCKTxPowerSaving       0x80
 584 #define bCCKRxPowerSaving       0x40
 585 
 586 #define bCCKSideBand            0x10    /* Reg 0xa00 rCCK0_System 20/40 switch*/
 587 #define bCCKScramble            0x8     /* Useless */
 588 #define bCCKAntDiversity        0x8000
 589 #define bCCKCarrierRecovery     0x4000
 590 #define bCCKTxRate              0x3000
 591 #define bCCKDCCancel            0x0800
 592 #define bCCKISICancel           0x0400
 593 #define bCCKMatchFilter         0x0200
 594 #define bCCKEqualizer           0x0100
 595 #define bCCKPreambleDetect      0x800000
 596 #define bCCKFastFalseCCA        0x400000
 597 #define bCCKChEstStart          0x300000
 598 #define bCCKCCACount            0x080000
 599 #define bCCKcs_lim              0x070000
 600 #define bCCKBistMode            0x80000000
 601 #define bCCKCCAMask             0x40000000
 602 #define bCCKTxDACPhase          0x4
 603 #define bCCKRxADCPhase          0x20000000   /* r_rx_clk */
 604 #define bCCKr_cp_mode0          0x0100
 605 #define bCCKTxDCOffset          0xf0
 606 #define bCCKRxDCOffset          0xf
 607 #define bCCKCCAMode             0xc000
 608 #define bCCKFalseCS_lim         0x3f00
 609 #define bCCKCS_ratio            0xc00000
 610 #define bCCKCorgBit_sel         0x300000
 611 #define bCCKPD_lim              0x0f0000
 612 #define bCCKNewCCA              0x80000000
 613 #define bCCKRxHPofIG            0x8000
 614 #define bCCKRxIG                0x7f00
 615 #define bCCKLNAPolarity         0x800000
 616 #define bCCKRx1stGain           0x7f0000
 617 #define bCCKRFExtend            0x20000000 /* CCK Rx initial gain polarity */
 618 #define bCCKRxAGCSatLevel       0x1f000000
 619 #define bCCKRxAGCSatCount       0xe0
 620 #define bCCKRxRFSettle          0x1f       /* AGCsamp_dly */
 621 #define bCCKFixedRxAGC          0x8000
 622 #define bCCKAntennaPolarity     0x2000
 623 #define bCCKTxFilterType        0x0c00
 624 #define bCCKRxAGCReportType     0x0300
 625 #define bCCKRxDAGCEn            0x80000000
 626 #define bCCKRxDAGCPeriod        0x20000000
 627 #define bCCKRxDAGCSatLevel      0x1f000000
 628 #define bCCKTimingRecovery      0x800000
 629 #define bCCKTxC0                0x3f0000
 630 #define bCCKTxC1                0x3f000000
 631 #define bCCKTxC2                0x3f
 632 #define bCCKTxC3                0x3f00
 633 #define bCCKTxC4                0x3f0000
 634 #define bCCKTxC5                0x3f000000
 635 #define bCCKTxC6                0x3f
 636 #define bCCKTxC7                0x3f00
 637 #define bCCKDebugPort           0xff0000
 638 #define bCCKDACDebug            0x0f000000
 639 #define bCCKFalseAlarmEnable    0x8000
 640 #define bCCKFalseAlarmRead      0x4000
 641 #define bCCKTRSSI               0x7f
 642 #define bCCKRxAGCReport         0xfe
 643 #define bCCKRxReport_AntSel     0x80000000
 644 #define bCCKRxReport_MFOff      0x40000000
 645 #define bCCKRxRxReport_SQLoss   0x20000000
 646 #define bCCKRxReport_Pktloss    0x10000000
 647 #define bCCKRxReport_Lockedbit  0x08000000
 648 #define bCCKRxReport_RateError  0x04000000
 649 #define bCCKRxReport_RxRate     0x03000000
 650 #define bCCKRxFACounterLower    0xff
 651 #define bCCKRxFACounterUpper    0xff000000
 652 #define bCCKRxHPAGCStart        0xe000
 653 #define bCCKRxHPAGCFinal        0x1c00
 654 #define bCCKRxFalseAlarmEnable  0x8000
 655 #define bCCKFACounterFreeze     0x4000
 656 #define bCCKTxPathSel           0x10000000
 657 #define bCCKDefaultRxPath       0xc000000
 658 #define bCCKOptionRxPath        0x3000000
 659 
 660 /* 5. PageC(0xC00) */
 661 #define bNumOfSTF               0x3     /* Useless */
 662 #define bShift_L                0xc0
 663 #define bGI_TH                  0xc
 664 #define bRxPathA                0x1
 665 #define bRxPathB                0x2
 666 #define bRxPathC                0x4
 667 #define bRxPathD                0x8
 668 #define bTxPathA                0x1
 669 #define bTxPathB                0x2
 670 #define bTxPathC                0x4
 671 #define bTxPathD                0x8
 672 #define bTRSSIFreq              0x200
 673 #define bADCBackoff             0x3000
 674 #define bDFIRBackoff            0xc000
 675 #define bTRSSILatchPhase        0x10000
 676 #define bRxIDCOffset            0xff
 677 #define bRxQDCOffset            0xff00
 678 #define bRxDFIRMode             0x1800000
 679 #define bRxDCNFType             0xe000000
 680 #define bRXIQImb_A              0x3ff
 681 #define bRXIQImb_B              0xfc00
 682 #define bRXIQImb_C              0x3f0000
 683 #define bRXIQImb_D              0xffc00000
 684 #define bDC_dc_Notch            0x60000
 685 #define bRxNBINotch             0x1f000000
 686 #define bPD_TH                  0xf
 687 #define bPD_TH_Opt2             0xc000
 688 #define bPWED_TH                0x700
 689 #define bIfMF_Win_L             0x800
 690 #define bPD_Option              0x1000
 691 #define bMF_Win_L               0xe000
 692 #define bBW_Search_L            0x30000
 693 #define bwin_enh_L              0xc0000
 694 #define bBW_TH                  0x700000
 695 #define bED_TH2                 0x3800000
 696 #define bBW_option              0x4000000
 697 #define bRatio_TH               0x18000000
 698 #define bWindow_L               0xe0000000
 699 #define bSBD_Option             0x1
 700 #define bFrame_TH               0x1c
 701 #define bFS_Option              0x60
 702 #define bDC_Slope_check         0x80
 703 #define bFGuard_Counter_DC_L    0xe00
 704 #define bFrame_Weight_Short     0x7000
 705 #define bSub_Tune               0xe00000
 706 #define bFrame_DC_Length        0xe000000
 707 #define bSBD_start_offset       0x30000000
 708 #define bFrame_TH_2             0x7
 709 #define bFrame_GI2_TH           0x38
 710 #define bGI2_Sync_en            0x40
 711 #define bSarch_Short_Early      0x300
 712 #define bSarch_Short_Late       0xc00
 713 #define bSarch_GI2_Late         0x70000
 714 #define bCFOAntSum              0x1
 715 #define bCFOAcc                 0x2
 716 #define bCFOStartOffset         0xc
 717 #define bCFOLookBack            0x70
 718 #define bCFOSumWeight           0x80
 719 #define bDAGCEnable             0x10000
 720 #define bTXIQImb_A              0x3ff
 721 #define bTXIQImb_B              0xfc00
 722 #define bTXIQImb_C              0x3f0000
 723 #define bTXIQImb_D              0xffc00000
 724 #define bTxIDCOffset            0xff
 725 #define bTxQDCOffset            0xff00
 726 #define bTxDFIRMode             0x10000
 727 #define bTxPesudoNoiseOn        0x4000000
 728 #define bTxPesudoNoise_A        0xff
 729 #define bTxPesudoNoise_B        0xff00
 730 #define bTxPesudoNoise_C        0xff0000
 731 #define bTxPesudoNoise_D        0xff000000
 732 #define bCCADropOption          0x20000
 733 #define bCCADropThres           0xfff00000
 734 #define bEDCCA_H                0xf
 735 #define bEDCCA_L                0xf0
 736 #define bLambda_ED              0x300
 737 #define bRxInitialGain          0x7f
 738 #define bRxAntDivEn             0x80
 739 #define bRxAGCAddressForLNA     0x7f00
 740 #define bRxHighPowerFlow        0x8000
 741 #define bRxAGCFreezeThres       0xc0000
 742 #define bRxFreezeStep_AGC1      0x300000
 743 #define bRxFreezeStep_AGC2      0xc00000
 744 #define bRxFreezeStep_AGC3      0x3000000
 745 #define bRxFreezeStep_AGC0      0xc000000
 746 #define bRxRssi_Cmp_En          0x10000000
 747 #define bRxQuickAGCEn           0x20000000
 748 #define bRxAGCFreezeThresMode   0x40000000
 749 #define bRxOverFlowCheckType    0x80000000
 750 #define bRxAGCShift             0x7f
 751 #define bTRSW_Tri_Only          0x80
 752 #define bPowerThres             0x300
 753 #define bRxAGCEn                0x1
 754 #define bRxAGCTogetherEn        0x2
 755 #define bRxAGCMin               0x4
 756 #define bRxHP_Ini               0x7
 757 #define bRxHP_TRLNA             0x70
 758 #define bRxHP_RSSI              0x700
 759 #define bRxHP_BBP1              0x7000
 760 #define bRxHP_BBP2              0x70000
 761 #define bRxHP_BBP3              0x700000
 762 #define bRSSI_H                 0x7f0000     /* the threshold for high power */
 763 #define bRSSI_Gen               0x7f000000   /* the threshold for ant divers */
 764 #define bRxSettle_TRSW          0x7
 765 #define bRxSettle_LNA           0x38
 766 #define bRxSettle_RSSI          0x1c0
 767 #define bRxSettle_BBP           0xe00
 768 #define bRxSettle_RxHP          0x7000
 769 #define bRxSettle_AntSW_RSSI    0x38000
 770 #define bRxSettle_AntSW         0xc0000
 771 #define bRxProcessTime_DAGC     0x300000
 772 #define bRxSettle_HSSI          0x400000
 773 #define bRxProcessTime_BBPPW    0x800000
 774 #define bRxAntennaPowerShift    0x3000000
 775 #define bRSSITableSelect        0xc000000
 776 #define bRxHP_Final             0x7000000
 777 #define bRxHTSettle_BBP         0x7
 778 #define bRxHTSettle_HSSI        0x8
 779 #define bRxHTSettle_RxHP        0x70
 780 #define bRxHTSettle_BBPPW       0x80
 781 #define bRxHTSettle_Idle        0x300
 782 #define bRxHTSettle_Reserved    0x1c00
 783 #define bRxHTRxHPEn             0x8000
 784 #define bRxHTAGCFreezeThres     0x30000
 785 #define bRxHTAGCTogetherEn      0x40000
 786 #define bRxHTAGCMin             0x80000
 787 #define bRxHTAGCEn              0x100000
 788 #define bRxHTDAGCEn             0x200000
 789 #define bRxHTRxHP_BBP           0x1c00000
 790 #define bRxHTRxHP_Final         0xe0000000
 791 #define bRxPWRatioTH            0x3
 792 #define bRxPWRatioEn            0x4
 793 #define bRxMFHold               0x3800
 794 #define bRxPD_Delay_TH1         0x38
 795 #define bRxPD_Delay_TH2         0x1c0
 796 #define bRxPD_DC_COUNT_MAX      0x600
 797 #define bRxPD_Delay_TH          0x8000
 798 #define bRxProcess_Delay        0xf0000
 799 #define bRxSearchrange_GI2_Early 0x700000
 800 #define bRxFrame_Guard_Counter_L 0x3800000
 801 #define bRxSGI_Guard_L          0xc000000
 802 #define bRxSGI_Search_L         0x30000000
 803 #define bRxSGI_TH               0xc0000000
 804 #define bDFSCnt0                0xff
 805 #define bDFSCnt1                0xff00
 806 #define bDFSFlag                0xf0000
 807 #define bMFWeightSum            0x300000
 808 #define bMinIdxTH               0x7f000000
 809 #define bDAFormat               0x40000
 810 #define bTxChEmuEnable          0x01000000
 811 #define bTRSWIsolation_A        0x7f
 812 #define bTRSWIsolation_B        0x7f00
 813 #define bTRSWIsolation_C        0x7f0000
 814 #define bTRSWIsolation_D        0x7f000000
 815 #define bExtLNAGain             0x7c00
 816 
 817 /* 6. PageE(0xE00) */
 818 #define bSTBCEn                 0x4     /* Useless */
 819 #define bAntennaMapping         0x10
 820 #define bNss                    0x20
 821 #define bCFOAntSumD             0x200
 822 #define bPHYCounterReset        0x8000000
 823 #define bCFOReportGet           0x4000000
 824 #define bOFDMContinueTx         0x10000000
 825 #define bOFDMSingleCarrier      0x20000000
 826 #define bOFDMSingleTone         0x40000000
 827 #define bHTDetect               0x100
 828 #define bCFOEn                  0x10000
 829 #define bCFOValue               0xfff00000
 830 #define bSigTone_Re             0x3f
 831 #define bSigTone_Im             0x7f00
 832 #define bCounter_CCA            0xffff
 833 #define bCounter_ParityFail     0xffff0000
 834 #define bCounter_RateIllegal    0xffff
 835 #define bCounter_CRC8Fail       0xffff0000
 836 #define bCounter_MCSNoSupport   0xffff
 837 #define bCounter_FastSync       0xffff
 838 #define bShortCFO               0xfff
 839 #define bShortCFOTLength        12   /* total */
 840 #define bShortCFOFLength        11   /* fraction */
 841 #define bLongCFO                0x7ff
 842 #define bLongCFOTLength         11
 843 #define bLongCFOFLength         11
 844 #define bTailCFO                0x1fff
 845 #define bTailCFOTLength         13
 846 #define bTailCFOFLength         12
 847 #define bmax_en_pwdB            0xffff
 848 #define bCC_power_dB            0xffff0000
 849 #define bnoise_pwdB             0xffff
 850 #define bPowerMeasTLength       10
 851 #define bPowerMeasFLength       3
 852 #define bRx_HT_BW               0x1
 853 #define bRxSC                   0x6
 854 #define bRx_HT                  0x8
 855 #define bNB_intf_det_on         0x1
 856 #define bIntf_win_len_cfg       0x30
 857 #define bNB_Intf_TH_cfg         0x1c0
 858 #define bRFGain                 0x3f
 859 #define bTableSel               0x40
 860 #define bTRSW                   0x80
 861 #define bRxSNR_A                0xff
 862 #define bRxSNR_B                0xff00
 863 #define bRxSNR_C                0xff0000
 864 #define bRxSNR_D                0xff000000
 865 #define bSNREVMTLength          8
 866 #define bSNREVMFLength          1
 867 #define bCSI1st                 0xff
 868 #define bCSI2nd                 0xff00
 869 #define bRxEVM1st               0xff0000
 870 #define bRxEVM2nd               0xff000000
 871 #define bSIGEVM                 0xff
 872 #define bPWDB                   0xff00
 873 #define bSGIEN                  0x10000
 874 
 875 #define bSFactorQAM1            0xf     /* Useless */
 876 #define bSFactorQAM2            0xf0
 877 #define bSFactorQAM3            0xf00
 878 #define bSFactorQAM4            0xf000
 879 #define bSFactorQAM5            0xf0000
 880 #define bSFactorQAM6            0xf0000
 881 #define bSFactorQAM7            0xf00000
 882 #define bSFactorQAM8            0xf000000
 883 #define bSFactorQAM9            0xf0000000
 884 #define bCSIScheme              0x100000
 885 
 886 #define bNoiseLvlTopSet         0x3     /* Useless */
 887 #define bChSmooth               0x4
 888 #define bChSmoothCfg1           0x38
 889 #define bChSmoothCfg2           0x1c0
 890 #define bChSmoothCfg3           0xe00
 891 #define bChSmoothCfg4           0x7000
 892 #define bMRCMode                0x800000
 893 #define bTHEVMCfg               0x7000000
 894 
 895 #define bLoopFitType            0x1     /* Useless */
 896 #define bUpdCFO                 0x40
 897 #define bUpdCFOOffData          0x80
 898 #define bAdvUpdCFO              0x100
 899 #define bAdvTimeCtrl            0x800
 900 #define bUpdClko                0x1000
 901 #define bFC                     0x6000
 902 #define bTrackingMode           0x8000
 903 #define bPhCmpEnable            0x10000
 904 #define bUpdClkoLTF             0x20000
 905 #define bComChCFO               0x40000
 906 #define bCSIEstiMode            0x80000
 907 #define bAdvUpdEqz              0x100000
 908 #define bUChCfg                 0x7000000
 909 #define bUpdEqz                 0x8000000
 910 
 911 #define bTxAGCRate18_06         0x7f7f7f7f      /* Useless */
 912 #define bTxAGCRate54_24         0x7f7f7f7f
 913 #define bTxAGCRateMCS32         0x7f
 914 #define bTxAGCRateCCK           0x7f00
 915 #define bTxAGCRateMCS3_MCS0     0x7f7f7f7f
 916 #define bTxAGCRateMCS7_MCS4     0x7f7f7f7f
 917 #define bTxAGCRateMCS11_MCS8    0x7f7f7f7f
 918 #define bTxAGCRateMCS15_MCS12   0x7f7f7f7f
 919 
 920 /* Rx Pseduo noise */
 921 #define bRxPesudoNoiseOn         0x20000000     /* Useless */
 922 #define bRxPesudoNoise_A         0xff
 923 #define bRxPesudoNoise_B         0xff00
 924 #define bRxPesudoNoise_C         0xff0000
 925 #define bRxPesudoNoise_D         0xff000000
 926 #define bPesudoNoiseState_A      0xffff
 927 #define bPesudoNoiseState_B      0xffff0000
 928 #define bPesudoNoiseState_C      0xffff
 929 #define bPesudoNoiseState_D      0xffff0000
 930 
 931 /* 7. RF Register
 932  * Zebra1
 933  */
 934 #define bZebra1_HSSIEnable        0x8           /* Useless */
 935 #define bZebra1_TRxControl        0xc00
 936 #define bZebra1_TRxGainSetting    0x07f
 937 #define bZebra1_RxCorner          0xc00
 938 #define bZebra1_TxChargePump      0x38
 939 #define bZebra1_RxChargePump      0x7
 940 #define bZebra1_ChannelNum        0xf80
 941 #define bZebra1_TxLPFBW           0x400
 942 #define bZebra1_RxLPFBW           0x600
 943 
 944 /*Zebra4 */
 945 #define bRTL8256RegModeCtrl1      0x100 /* Useless */
 946 #define bRTL8256RegModeCtrl0      0x40
 947 #define bRTL8256_TxLPFBW          0x18
 948 #define bRTL8256_RxLPFBW          0x600
 949 
 950 /* RTL8258 */
 951 #define bRTL8258_TxLPFBW          0xc   /* Useless */
 952 #define bRTL8258_RxLPFBW          0xc00
 953 #define bRTL8258_RSSILPFBW        0xc0
 954 
 955 /*
 956  * Other Definition
 957  */
 958 
 959 /* byte endable for sb_write */
 960 #define bByte0                    0x1   /* Useless */
 961 #define bByte1                    0x2
 962 #define bByte2                    0x4
 963 #define bByte3                    0x8
 964 #define bWord0                    0x3
 965 #define bWord1                    0xc
 966 #define bDWord                    0xf
 967 
 968 /* for PutRegsetting & GetRegSetting BitMask */
 969 #define bMaskByte0                0xff  /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
 970 #define bMaskByte1                0xff00
 971 #define bMaskByte2                0xff0000
 972 #define bMaskByte3                0xff000000
 973 #define bMaskHWord                0xffff0000
 974 #define bMaskLWord                0x0000ffff
 975 #define bMaskDWord                0xffffffff
 976 
 977 /* for PutRFRegsetting & GetRFRegSetting BitMask */
 978 #define bRFRegOffsetMask        0xfffff
 979 #define bEnable                   0x1   /* Useless */
 980 #define bDisable                  0x0
 981 
 982 #define LeftAntenna               0x0   /* Useless */
 983 #define RightAntenna              0x1
 984 
 985 #define tCheckTxStatus            500   /* 500ms Useless */
 986 #define tUpdateRxCounter          100   /* 100ms */
 987 
 988 #define rateCCK     0   /* Useless */
 989 #define rateOFDM    1
 990 #define rateHT      2
 991 
 992 /* define Register-End */
 993 #define bPMAC_End       0x1ff   /* Useless */
 994 #define bFPGAPHY0_End   0x8ff
 995 #define bFPGAPHY1_End   0x9ff
 996 #define bCCKPHY0_End    0xaff
 997 #define bOFDMPHY0_End   0xcff
 998 #define bOFDMPHY1_End   0xdff
 999 
1000 #define bPMACControl    0x0     /* Useless */
1001 #define bWMACControl    0x1
1002 #define bWNICControl    0x2
1003 
1004 #define ANTENNA_A       0x1     /* Useless */
1005 #define ANTENNA_B       0x2
1006 #define ANTENNA_AB      0x3     /* ANTENNA_A |ANTENNA_B */
1007 
1008 #define ANTENNA_C       0x4
1009 #define ANTENNA_D       0x8
1010 
1011 
1012 /* accept all physical address */
1013 #define RCR_AAP         BIT(0)
1014 #define RCR_APM         BIT(1)          /* accept physical match */
1015 #define RCR_AM          BIT(2)          /* accept multicast */
1016 #define RCR_AB          BIT(3)          /* accept broadcast */
1017 #define RCR_ACRC32      BIT(5)          /* accept error packet */
1018 #define RCR_9356SEL     BIT(6)
1019 #define RCR_AICV        BIT(12)         /* Accept ICV error packet */
1020 #define RCR_RXFTH0      (BIT(13)|BIT(14)|BIT(15))       /* Rx FIFO threshold */
1021 #define RCR_ADF         BIT(18)         /* Accept Data(frame type) frame */
1022 #define RCR_ACF         BIT(19)         /* Accept control frame */
1023 #define RCR_AMF         BIT(20)         /* Accept management frame */
1024 #define RCR_ADD3        BIT(21)
1025 #define RCR_APWRMGT     BIT(22)         /* Accept power management packet */
1026 #define RCR_CBSSID      BIT(23)         /* Accept BSSID match packet */
1027 #define RCR_ENMARP      BIT(28)         /* enable mac auto reset phy */
1028 #define RCR_EnCS1       BIT(29)         /* enable carrier sense method 1 */
1029 #define RCR_EnCS2       BIT(30)         /* enable carrier sense method 2 */
1030 /* Rx Early mode is performed for packet size greater than 1536 */
1031 #define RCR_OnlyErlPkt  BIT(31)
1032 
1033 /*--------------------------Define Parameters-------------------------------*/
1034 
1035 
1036 #endif  /*__INC_HAL8192SPHYREG_H */
1037