root/drivers/staging/wusbcore/host/whci/whci-hc.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. usb_pipe_to_qh_type
  2. whc_qset_set_link_ptr
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Wireless Host Controller (WHC) data structures.
   4  *
   5  * Copyright (C) 2007 Cambridge Silicon Radio Ltd.
   6  */
   7 #ifndef _WHCI_WHCI_HC_H
   8 #define _WHCI_WHCI_HC_H
   9 
  10 #include <linux/list.h>
  11 
  12 /**
  13  * WHCI_PAGE_SIZE - page size use by WHCI
  14  *
  15  * WHCI assumes that host system uses pages of 4096 octets.
  16  */
  17 #define WHCI_PAGE_SIZE 4096
  18 
  19 
  20 /**
  21  * QTD_MAX_TXFER_SIZE - max number of bytes to transfer with a single
  22  * qtd.
  23  *
  24  * This is 2^20 - 1.
  25  */
  26 #define QTD_MAX_XFER_SIZE 1048575
  27 
  28 
  29 /**
  30  * struct whc_qtd - Queue Element Transfer Descriptors (qTD)
  31  *
  32  * This describes the data for a bulk, control or interrupt transfer.
  33  *
  34  * [WHCI] section 3.2.4
  35  */
  36 struct whc_qtd {
  37         __le32 status; /*< remaining transfer len and transfer status */
  38         __le32 options;
  39         __le64 page_list_ptr; /*< physical pointer to data buffer page list*/
  40         __u8   setup[8];      /*< setup data for control transfers */
  41 } __attribute__((packed));
  42 
  43 #define QTD_STS_ACTIVE     (1 << 31)  /* enable execution of transaction */
  44 #define QTD_STS_HALTED     (1 << 30)  /* transfer halted */
  45 #define QTD_STS_DBE        (1 << 29)  /* data buffer error */
  46 #define QTD_STS_BABBLE     (1 << 28)  /* babble detected */
  47 #define QTD_STS_RCE        (1 << 27)  /* retry count exceeded */
  48 #define QTD_STS_LAST_PKT   (1 << 26)  /* set Last Packet Flag in WUSB header */
  49 #define QTD_STS_INACTIVE   (1 << 25)  /* queue set is marked inactive */
  50 #define QTD_STS_IALT_VALID (1 << 23)                          /* iAlt field is valid */
  51 #define QTD_STS_IALT(i)    (QTD_STS_IALT_VALID | ((i) << 20)) /* iAlt field */
  52 #define QTD_STS_LEN(l)     ((l) << 0) /* transfer length */
  53 #define QTD_STS_TO_LEN(s)  ((s) & 0x000fffff)
  54 
  55 #define QTD_OPT_IOC      (1 << 1) /* page_list_ptr points to buffer directly */
  56 #define QTD_OPT_SMALL    (1 << 0) /* interrupt on complete */
  57 
  58 /**
  59  * struct whc_itd - Isochronous Queue Element Transfer Descriptors (iTD)
  60  *
  61  * This describes the data and other parameters for an isochronous
  62  * transfer.
  63  *
  64  * [WHCI] section 3.2.5
  65  */
  66 struct whc_itd {
  67         __le16 presentation_time;    /*< presentation time for OUT transfers */
  68         __u8   num_segments;         /*< number of data segments in segment list */
  69         __u8   status;               /*< command execution status */
  70         __le32 options;              /*< misc transfer options */
  71         __le64 page_list_ptr;        /*< physical pointer to data buffer page list */
  72         __le64 seg_list_ptr;         /*< physical pointer to segment list */
  73 } __attribute__((packed));
  74 
  75 #define ITD_STS_ACTIVE   (1 << 7) /* enable execution of transaction */
  76 #define ITD_STS_DBE      (1 << 5) /* data buffer error */
  77 #define ITD_STS_BABBLE   (1 << 4) /* babble detected */
  78 #define ITD_STS_INACTIVE (1 << 1) /* queue set is marked inactive */
  79 
  80 #define ITD_OPT_IOC      (1 << 1) /* interrupt on complete */
  81 #define ITD_OPT_SMALL    (1 << 0) /* page_list_ptr points to buffer directly */
  82 
  83 /**
  84  * Page list entry.
  85  *
  86  * A TD's page list must contain sufficient page list entries for the
  87  * total data length in the TD.
  88  *
  89  * [WHCI] section 3.2.4.3
  90  */
  91 struct whc_page_list_entry {
  92         __le64 buf_ptr; /*< physical pointer to buffer */
  93 } __attribute__((packed));
  94 
  95 /**
  96  * struct whc_seg_list_entry - Segment list entry.
  97  *
  98  * Describes a portion of the data buffer described in the containing
  99  * qTD's page list.
 100  *
 101  * seg_ptr = qtd->page_list_ptr[qtd->seg_list_ptr[seg].idx].buf_ptr
 102  *           + qtd->seg_list_ptr[seg].offset;
 103  *
 104  * Segments can't cross page boundries.
 105  *
 106  * [WHCI] section 3.2.5.5
 107  */
 108 struct whc_seg_list_entry {
 109         __le16 len;    /*< segment length */
 110         __u8   idx;    /*< index into page list */
 111         __u8   status; /*< segment status */
 112         __le16 offset; /*< 12 bit offset into page */
 113 } __attribute__((packed));
 114 
 115 /**
 116  * struct whc_qhead - endpoint and status information for a qset.
 117  *
 118  * [WHCI] section 3.2.6
 119  */
 120 struct whc_qhead {
 121         __le64 link; /*< next qset in list */
 122         __le32 info1;
 123         __le32 info2;
 124         __le32 info3;
 125         __le16 status;
 126         __le16 err_count;  /*< transaction error count */
 127         __le32 cur_window;
 128         __le32 scratch[3]; /*< h/w scratch area */
 129         union {
 130                 struct whc_qtd qtd;
 131                 struct whc_itd itd;
 132         } overlay;
 133 } __attribute__((packed));
 134 
 135 #define QH_LINK_PTR_MASK (~0x03Full)
 136 #define QH_LINK_PTR(ptr) ((ptr) & QH_LINK_PTR_MASK)
 137 #define QH_LINK_IQS      (1 << 4) /* isochronous queue set */
 138 #define QH_LINK_NTDS(n)  (((n) - 1) << 1) /* number of TDs in queue set */
 139 #define QH_LINK_T        (1 << 0) /* last queue set in periodic schedule list */
 140 
 141 #define QH_INFO1_EP(e)           ((e) << 0)  /* endpoint number */
 142 #define QH_INFO1_DIR_IN          (1 << 4)    /* IN transfer */
 143 #define QH_INFO1_DIR_OUT         (0 << 4)    /* OUT transfer */
 144 #define QH_INFO1_TR_TYPE_CTRL    (0x0 << 5)  /* control transfer */
 145 #define QH_INFO1_TR_TYPE_ISOC    (0x1 << 5)  /* isochronous transfer */
 146 #define QH_INFO1_TR_TYPE_BULK    (0x2 << 5)  /* bulk transfer */
 147 #define QH_INFO1_TR_TYPE_INT     (0x3 << 5)  /* interrupt */
 148 #define QH_INFO1_TR_TYPE_LP_INT  (0x7 << 5)  /* low power interrupt */
 149 #define QH_INFO1_DEV_INFO_IDX(i) ((i) << 8)  /* index into device info buffer */
 150 #define QH_INFO1_SET_INACTIVE    (1 << 15)   /* set inactive after transfer */
 151 #define QH_INFO1_MAX_PKT_LEN(l)  ((l) << 16) /* maximum packet length */
 152 
 153 #define QH_INFO2_BURST(b)        ((b) << 0)  /* maximum burst length */
 154 #define QH_INFO2_DBP(p)          ((p) << 5)  /* data burst policy (see [WUSB] table 5-7) */
 155 #define QH_INFO2_MAX_COUNT(c)    ((c) << 8)  /* max isoc/int pkts per zone */
 156 #define QH_INFO2_RQS             (1 << 15)   /* reactivate queue set */
 157 #define QH_INFO2_MAX_RETRY(r)    ((r) << 16) /* maximum transaction retries */
 158 #define QH_INFO2_MAX_SEQ(s)      ((s) << 20) /* maximum sequence number */
 159 #define QH_INFO3_MAX_DELAY(d)    ((d) << 0)  /* maximum stream delay in 125 us units (isoc only) */
 160 #define QH_INFO3_INTERVAL(i)     ((i) << 16) /* segment interval in 125 us units (isoc only) */
 161 
 162 #define QH_INFO3_TX_RATE(r)      ((r) << 24) /* PHY rate (see [ECMA-368] section 10.3.1.1) */
 163 #define QH_INFO3_TX_PWR(p)       ((p) << 29) /* transmit power (see [WUSB] section 5.2.1.2) */
 164 
 165 #define QH_STATUS_FLOW_CTRL      (1 << 15)
 166 #define QH_STATUS_ICUR(i)        ((i) << 5)
 167 #define QH_STATUS_TO_ICUR(s)     (((s) >> 5) & 0x7)
 168 #define QH_STATUS_SEQ_MASK       0x1f
 169 
 170 /**
 171  * usb_pipe_to_qh_type - USB core pipe type to QH transfer type
 172  *
 173  * Returns the QH type field for a USB core pipe type.
 174  */
 175 static inline unsigned usb_pipe_to_qh_type(unsigned pipe)
 176 {
 177         static const unsigned type[] = {
 178                 [PIPE_ISOCHRONOUS] = QH_INFO1_TR_TYPE_ISOC,
 179                 [PIPE_INTERRUPT]   = QH_INFO1_TR_TYPE_INT,
 180                 [PIPE_CONTROL]     = QH_INFO1_TR_TYPE_CTRL,
 181                 [PIPE_BULK]        = QH_INFO1_TR_TYPE_BULK,
 182         };
 183         return type[usb_pipetype(pipe)];
 184 }
 185 
 186 /**
 187  * Maxiumum number of TDs in a qset.
 188  */
 189 #define WHCI_QSET_TD_MAX 8
 190 
 191 /**
 192  * struct whc_qset - WUSB data transfers to a specific endpoint
 193  * @qh: the QHead of this qset
 194  * @qtd: up to 8 qTDs (for qsets for control, bulk and interrupt
 195  * transfers)
 196  * @itd: up to 8 iTDs (for qsets for isochronous transfers)
 197  * @qset_dma: DMA address for this qset
 198  * @whc: WHCI HC this qset is for
 199  * @ep: endpoint
 200  * @stds: list of sTDs queued to this qset
 201  * @ntds: number of qTDs queued (not necessarily the same as nTDs
 202  * field in the QH)
 203  * @td_start: index of the first qTD in the list
 204  * @td_end: index of next free qTD in the list (provided
 205  *          ntds < WHCI_QSET_TD_MAX)
 206  *
 207  * Queue Sets (qsets) are added to the asynchronous schedule list
 208  * (ASL) or the periodic zone list (PZL).
 209  *
 210  * qsets may contain up to 8 TDs (either qTDs or iTDs as appropriate).
 211  * Each TD may refer to at most 1 MiB of data. If a single transfer
 212  * has > 8MiB of data, TDs can be reused as they are completed since
 213  * the TD list is used as a circular buffer.  Similarly, several
 214  * (smaller) transfers may be queued in a qset.
 215  *
 216  * WHCI controllers may cache portions of the qsets in the ASL and
 217  * PZL, requiring the WHCD to inform the WHC that the lists have been
 218  * updated (fields changed or qsets inserted or removed).  For safe
 219  * insertion and removal of qsets from the lists the schedule must be
 220  * stopped to avoid races in updating the QH link pointers.
 221  *
 222  * Since the HC is free to execute qsets in any order, all transfers
 223  * to an endpoint should use the same qset to ensure transfers are
 224  * executed in the order they're submitted.
 225  *
 226  * [WHCI] section 3.2.3
 227  */
 228 struct whc_qset {
 229         struct whc_qhead qh;
 230         union {
 231                 struct whc_qtd qtd[WHCI_QSET_TD_MAX];
 232                 struct whc_itd itd[WHCI_QSET_TD_MAX];
 233         };
 234 
 235         /* private data for WHCD */
 236         dma_addr_t qset_dma;
 237         struct whc *whc;
 238         struct usb_host_endpoint *ep;
 239         struct list_head stds;
 240         int ntds;
 241         int td_start;
 242         int td_end;
 243         struct list_head list_node;
 244         unsigned in_sw_list:1;
 245         unsigned in_hw_list:1;
 246         unsigned remove:1;
 247         unsigned reset:1;
 248         struct urb *pause_after_urb;
 249         struct completion remove_complete;
 250         uint16_t max_packet;
 251         uint8_t max_burst;
 252         uint8_t max_seq;
 253 };
 254 
 255 static inline void whc_qset_set_link_ptr(u64 *ptr, u64 target)
 256 {
 257         if (target)
 258                 *ptr = (*ptr & ~(QH_LINK_PTR_MASK | QH_LINK_T)) | QH_LINK_PTR(target);
 259         else
 260                 *ptr = QH_LINK_T;
 261 }
 262 
 263 /**
 264  * struct di_buf_entry - Device Information (DI) buffer entry.
 265  *
 266  * There's one of these per connected device.
 267  */
 268 struct di_buf_entry {
 269         __le32 availability_info[8]; /*< MAS availability information, one MAS per bit */
 270         __le32 addr_sec_info;        /*< addressing and security info */
 271         __le32 reserved[7];
 272 } __attribute__((packed));
 273 
 274 #define WHC_DI_SECURE           (1 << 31)
 275 #define WHC_DI_DISABLE          (1 << 30)
 276 #define WHC_DI_KEY_IDX(k)       ((k) << 8)
 277 #define WHC_DI_KEY_IDX_MASK     0x0000ff00
 278 #define WHC_DI_DEV_ADDR(a)      ((a) << 0)
 279 #define WHC_DI_DEV_ADDR_MASK    0x000000ff
 280 
 281 /**
 282  * struct dn_buf_entry - Device Notification (DN) buffer entry.
 283  *
 284  * [WHCI] section 3.2.8
 285  */
 286 struct dn_buf_entry {
 287         __u8   msg_size;    /*< number of octets of valid DN data */
 288         __u8   reserved1;
 289         __u8   src_addr;    /*< source address */
 290         __u8   status;      /*< buffer entry status */
 291         __le32 tkid;        /*< TKID for source device, valid if secure bit is set */
 292         __u8   dn_data[56]; /*< up to 56 octets of DN data */
 293 } __attribute__((packed));
 294 
 295 #define WHC_DN_STATUS_VALID  (1 << 7) /* buffer entry is valid */
 296 #define WHC_DN_STATUS_SECURE (1 << 6) /* notification received using secure frame */
 297 
 298 #define WHC_N_DN_ENTRIES (4096 / sizeof(struct dn_buf_entry))
 299 
 300 /* The Add MMC IE WUSB Generic Command may take up to 256 bytes of
 301    data. [WHCI] section 2.4.7. */
 302 #define WHC_GEN_CMD_DATA_LEN 256
 303 
 304 /*
 305  * HC registers.
 306  *
 307  * [WHCI] section 2.4
 308  */
 309 
 310 #define WHCIVERSION          0x00
 311 
 312 #define WHCSPARAMS           0x04
 313 #  define WHCSPARAMS_TO_N_MMC_IES(p) (((p) >> 16) & 0xff)
 314 #  define WHCSPARAMS_TO_N_KEYS(p)    (((p) >> 8) & 0xff)
 315 #  define WHCSPARAMS_TO_N_DEVICES(p) (((p) >> 0) & 0x7f)
 316 
 317 #define WUSBCMD              0x08
 318 #  define WUSBCMD_BCID(b)            ((b) << 16)
 319 #  define WUSBCMD_BCID_MASK          (0xff << 16)
 320 #  define WUSBCMD_ASYNC_QSET_RM      (1 << 12)
 321 #  define WUSBCMD_PERIODIC_QSET_RM   (1 << 11)
 322 #  define WUSBCMD_WUSBSI(s)          ((s) << 8)
 323 #  define WUSBCMD_WUSBSI_MASK        (0x7 << 8)
 324 #  define WUSBCMD_ASYNC_SYNCED_DB    (1 << 7)
 325 #  define WUSBCMD_PERIODIC_SYNCED_DB (1 << 6)
 326 #  define WUSBCMD_ASYNC_UPDATED      (1 << 5)
 327 #  define WUSBCMD_PERIODIC_UPDATED   (1 << 4)
 328 #  define WUSBCMD_ASYNC_EN           (1 << 3)
 329 #  define WUSBCMD_PERIODIC_EN        (1 << 2)
 330 #  define WUSBCMD_WHCRESET           (1 << 1)
 331 #  define WUSBCMD_RUN                (1 << 0)
 332 
 333 #define WUSBSTS              0x0c
 334 #  define WUSBSTS_ASYNC_SCHED             (1 << 15)
 335 #  define WUSBSTS_PERIODIC_SCHED          (1 << 14)
 336 #  define WUSBSTS_DNTS_SCHED              (1 << 13)
 337 #  define WUSBSTS_HCHALTED                (1 << 12)
 338 #  define WUSBSTS_GEN_CMD_DONE            (1 << 9)
 339 #  define WUSBSTS_CHAN_TIME_ROLLOVER      (1 << 8)
 340 #  define WUSBSTS_DNTS_OVERFLOW           (1 << 7)
 341 #  define WUSBSTS_BPST_ADJUSTMENT_CHANGED (1 << 6)
 342 #  define WUSBSTS_HOST_ERR                (1 << 5)
 343 #  define WUSBSTS_ASYNC_SCHED_SYNCED      (1 << 4)
 344 #  define WUSBSTS_PERIODIC_SCHED_SYNCED   (1 << 3)
 345 #  define WUSBSTS_DNTS_INT                (1 << 2)
 346 #  define WUSBSTS_ERR_INT                 (1 << 1)
 347 #  define WUSBSTS_INT                     (1 << 0)
 348 #  define WUSBSTS_INT_MASK                0x3ff
 349 
 350 #define WUSBINTR             0x10
 351 #  define WUSBINTR_GEN_CMD_DONE             (1 << 9)
 352 #  define WUSBINTR_CHAN_TIME_ROLLOVER       (1 << 8)
 353 #  define WUSBINTR_DNTS_OVERFLOW            (1 << 7)
 354 #  define WUSBINTR_BPST_ADJUSTMENT_CHANGED  (1 << 6)
 355 #  define WUSBINTR_HOST_ERR                 (1 << 5)
 356 #  define WUSBINTR_ASYNC_SCHED_SYNCED       (1 << 4)
 357 #  define WUSBINTR_PERIODIC_SCHED_SYNCED    (1 << 3)
 358 #  define WUSBINTR_DNTS_INT                 (1 << 2)
 359 #  define WUSBINTR_ERR_INT                  (1 << 1)
 360 #  define WUSBINTR_INT                      (1 << 0)
 361 #  define WUSBINTR_ALL 0x3ff
 362 
 363 #define WUSBGENCMDSTS        0x14
 364 #  define WUSBGENCMDSTS_ACTIVE (1 << 31)
 365 #  define WUSBGENCMDSTS_ERROR  (1 << 24)
 366 #  define WUSBGENCMDSTS_IOC    (1 << 23)
 367 #  define WUSBGENCMDSTS_MMCIE_ADD 0x01
 368 #  define WUSBGENCMDSTS_MMCIE_RM  0x02
 369 #  define WUSBGENCMDSTS_SET_MAS   0x03
 370 #  define WUSBGENCMDSTS_CHAN_STOP 0x04
 371 #  define WUSBGENCMDSTS_RWP_EN    0x05
 372 
 373 #define WUSBGENCMDPARAMS     0x18
 374 #define WUSBGENADDR          0x20
 375 #define WUSBASYNCLISTADDR    0x28
 376 #define WUSBDNTSBUFADDR      0x30
 377 #define WUSBDEVICEINFOADDR   0x38
 378 
 379 #define WUSBSETSECKEYCMD     0x40
 380 #  define WUSBSETSECKEYCMD_SET    (1 << 31)
 381 #  define WUSBSETSECKEYCMD_ERASE  (1 << 30)
 382 #  define WUSBSETSECKEYCMD_GTK    (1 << 8)
 383 #  define WUSBSETSECKEYCMD_IDX(i) ((i) << 0)
 384 
 385 #define WUSBTKID             0x44
 386 #define WUSBSECKEY           0x48
 387 #define WUSBPERIODICLISTBASE 0x58
 388 #define WUSBMASINDEX         0x60
 389 
 390 #define WUSBDNTSCTRL         0x64
 391 #  define WUSBDNTSCTRL_ACTIVE      (1 << 31)
 392 #  define WUSBDNTSCTRL_INTERVAL(i) ((i) << 8)
 393 #  define WUSBDNTSCTRL_SLOTS(s)    ((s) << 0)
 394 
 395 #define WUSBTIME             0x68
 396 #  define WUSBTIME_CHANNEL_TIME_MASK 0x00ffffff
 397 
 398 #define WUSBBPST             0x6c
 399 #define WUSBDIBUPDATED       0x70
 400 
 401 #endif /* #ifndef _WHCI_WHCI_HC_H */
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