root/arch/mips/ralink/rt288x.c

DEFINITIONS

1. ralink_clk_init
2. ralink_of_remap
3. prom_soc_init

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  * Parts of this file are based on Ralink's 2.6.21 BSP
   5  *
   6  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   7  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   8  * Copyright (C) 2013 John Crispin <john@phrozen.org>
   9  */
  10 
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 
  14 #include <asm/mipsregs.h>
  15 #include <asm/mach-ralink/ralink_regs.h>
  16 #include <asm/mach-ralink/rt288x.h>
  17 #include <asm/mach-ralink/pinmux.h>
  18 
  19 #include "common.h"
  20 
  21 static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
  22 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
  23 static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
  24 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
  25 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
  26 static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
  27 static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
  28 
  29 static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
  30         GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
  31         GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
  32         GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
  33         GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
  34         GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
  35         GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
  36         GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
  37         { 0 }
  38 };
  39 
  40 void __init ralink_clk_init(void)
  41 {
  42         unsigned long cpu_rate, wmac_rate = 40000000;
  43         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  44         t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
  45 
  46         switch (t) {
  47         case SYSTEM_CONFIG_CPUCLK_250:
  48                 cpu_rate = 250000000;
  49                 break;
  50         case SYSTEM_CONFIG_CPUCLK_266:
  51                 cpu_rate = 266666667;
  52                 break;
  53         case SYSTEM_CONFIG_CPUCLK_280:
  54                 cpu_rate = 280000000;
  55                 break;
  56         case SYSTEM_CONFIG_CPUCLK_300:
  57                 cpu_rate = 300000000;
  58                 break;
  59         }
  60 
  61         ralink_clk_add("cpu", cpu_rate);
  62         ralink_clk_add("300100.timer", cpu_rate / 2);
  63         ralink_clk_add("300120.watchdog", cpu_rate / 2);
  64         ralink_clk_add("300500.uart", cpu_rate / 2);
  65         ralink_clk_add("300900.i2c", cpu_rate / 2);
  66         ralink_clk_add("300c00.uartlite", cpu_rate / 2);
  67         ralink_clk_add("400000.ethernet", cpu_rate / 2);
  68         ralink_clk_add("480000.wmac", wmac_rate);
  69 }
  70 
  71 void __init ralink_of_remap(void)
  72 {
  73         rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
  74         rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
  75 
  76         if (!rt_sysc_membase || !rt_memc_membase)
  77                 panic("Failed to remap core resources");
  78 }
  79 
  80 void prom_soc_init(struct ralink_soc_info *soc_info)
  81 {
  82         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
  83         const char *name;
  84         u32 n0;
  85         u32 n1;
  86         u32 id;
  87 
  88         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  89         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  90         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  91 
  92         if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
  93                 soc_info->compatible = "ralink,r2880-soc";
  94                 name = "RT2880";
  95         } else {
  96                 panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
  97         }
  98 
  99         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 100                 "Ralink %s id:%u rev:%u",
 101                 name,
 102                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 103                 (id & CHIP_ID_REV_MASK));
 104 
 105         soc_info->mem_base = RT2880_SDRAM_BASE;
 106         soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
 107         soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
 108 
 109         rt2880_pinmux_data = rt2880_pinmux_data_act;
 110         ralink_soc = RT2880_SOC;
 111 }