1 // SPDX-License-Identifier: GPL-2.0+
2 /* vim: set ts=8 sw=8 noet tw=80 nowrap: */
3 /*
4 * comedi/drivers/ni_routing/ni_device_routes/pxie-6738.c
5 * List of valid routes for specific NI boards.
6 *
7 * COMEDI - Linux Control and Measurement Device Interface
8 * Copyright (C) 2016 Spencer E. Olson <olsonse@umich.edu>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 /*
22 * The contents of this file are generated using the tools in
23 * comedi/drivers/ni_routing/tools
24 *
25 * Please use those tools to help maintain the contents of this file.
26 */
27
28 #include "../ni_device_routes.h"
29 #include "all.h"
30
31 struct ni_device_routes ni_pxie_6738_device_routes = {
32 .device = "pxie-6738",
33 .routes = (struct ni_route_set[]){
34 {
35 .dest = NI_PFI(0),
36 .src = (int[]){
37 TRIGGER_LINE(0),
38 TRIGGER_LINE(1),
39 TRIGGER_LINE(2),
40 TRIGGER_LINE(3),
41 TRIGGER_LINE(4),
42 TRIGGER_LINE(5),
43 TRIGGER_LINE(6),
44 TRIGGER_LINE(7),
45 NI_CtrSource(0),
46 NI_CtrSource(1),
47 NI_CtrSource(2),
48 NI_CtrSource(3),
49 NI_CtrGate(0),
50 NI_CtrGate(1),
51 NI_CtrGate(2),
52 NI_CtrGate(3),
53 NI_CtrArmStartTrigger(0),
54 NI_CtrArmStartTrigger(1),
55 NI_CtrArmStartTrigger(2),
56 NI_CtrArmStartTrigger(3),
57 NI_CtrInternalOutput(0),
58 NI_CtrInternalOutput(1),
59 NI_CtrInternalOutput(2),
60 NI_CtrInternalOutput(3),
61 NI_CtrSampleClock(0),
62 NI_CtrSampleClock(1),
63 NI_CtrSampleClock(2),
64 NI_CtrSampleClock(3),
65 NI_AO_SampleClock,
66 NI_AO_StartTrigger,
67 NI_AO_PauseTrigger,
68 NI_DI_SampleClock,
69 NI_DI_StartTrigger,
70 NI_DI_ReferenceTrigger,
71 NI_DI_PauseTrigger,
72 NI_DO_SampleClock,
73 NI_DO_StartTrigger,
74 NI_DO_PauseTrigger,
75 NI_10MHzRefClock,
76 NI_ChangeDetectionEvent,
77 NI_WatchdogExpiredEvent,
78 0, /* Termination */
79 }
80 },
81 {
82 .dest = NI_PFI(1),
83 .src = (int[]){
84 TRIGGER_LINE(0),
85 TRIGGER_LINE(1),
86 TRIGGER_LINE(2),
87 TRIGGER_LINE(3),
88 TRIGGER_LINE(4),
89 TRIGGER_LINE(5),
90 TRIGGER_LINE(6),
91 TRIGGER_LINE(7),
92 NI_CtrSource(0),
93 NI_CtrSource(1),
94 NI_CtrSource(2),
95 NI_CtrSource(3),
96 NI_CtrGate(0),
97 NI_CtrGate(1),
98 NI_CtrGate(2),
99 NI_CtrGate(3),
100 NI_CtrArmStartTrigger(0),
101 NI_CtrArmStartTrigger(1),
102 NI_CtrArmStartTrigger(2),
103 NI_CtrArmStartTrigger(3),
104 NI_CtrInternalOutput(0),
105 NI_CtrInternalOutput(1),
106 NI_CtrInternalOutput(2),
107 NI_CtrInternalOutput(3),
108 NI_CtrSampleClock(0),
109 NI_CtrSampleClock(1),
110 NI_CtrSampleClock(2),
111 NI_CtrSampleClock(3),
112 NI_AO_SampleClock,
113 NI_AO_StartTrigger,
114 NI_AO_PauseTrigger,
115 NI_DI_SampleClock,
116 NI_DI_StartTrigger,
117 NI_DI_ReferenceTrigger,
118 NI_DI_PauseTrigger,
119 NI_DO_SampleClock,
120 NI_DO_StartTrigger,
121 NI_DO_PauseTrigger,
122 NI_10MHzRefClock,
123 NI_ChangeDetectionEvent,
124 NI_WatchdogExpiredEvent,
125 0, /* Termination */
126 }
127 },
128 {
129 .dest = NI_PFI(2),
130 .src = (int[]){
131 TRIGGER_LINE(0),
132 TRIGGER_LINE(1),
133 TRIGGER_LINE(2),
134 TRIGGER_LINE(3),
135 TRIGGER_LINE(4),
136 TRIGGER_LINE(5),
137 TRIGGER_LINE(6),
138 TRIGGER_LINE(7),
139 NI_CtrSource(0),
140 NI_CtrSource(1),
141 NI_CtrSource(2),
142 NI_CtrSource(3),
143 NI_CtrGate(0),
144 NI_CtrGate(1),
145 NI_CtrGate(2),
146 NI_CtrGate(3),
147 NI_CtrArmStartTrigger(0),
148 NI_CtrArmStartTrigger(1),
149 NI_CtrArmStartTrigger(2),
150 NI_CtrArmStartTrigger(3),
151 NI_CtrInternalOutput(0),
152 NI_CtrInternalOutput(1),
153 NI_CtrInternalOutput(2),
154 NI_CtrInternalOutput(3),
155 NI_CtrSampleClock(0),
156 NI_CtrSampleClock(1),
157 NI_CtrSampleClock(2),
158 NI_CtrSampleClock(3),
159 NI_AO_SampleClock,
160 NI_AO_StartTrigger,
161 NI_AO_PauseTrigger,
162 NI_DI_SampleClock,
163 NI_DI_StartTrigger,
164 NI_DI_ReferenceTrigger,
165 NI_DI_PauseTrigger,
166 NI_DO_SampleClock,
167 NI_DO_StartTrigger,
168 NI_DO_PauseTrigger,
169 NI_10MHzRefClock,
170 NI_ChangeDetectionEvent,
171 NI_WatchdogExpiredEvent,
172 0, /* Termination */
173 }
174 },
175 {
176 .dest = NI_PFI(3),
177 .src = (int[]){
178 TRIGGER_LINE(0),
179 TRIGGER_LINE(1),
180 TRIGGER_LINE(2),
181 TRIGGER_LINE(3),
182 TRIGGER_LINE(4),
183 TRIGGER_LINE(5),
184 TRIGGER_LINE(6),
185 TRIGGER_LINE(7),
186 NI_CtrSource(0),
187 NI_CtrSource(1),
188 NI_CtrSource(2),
189 NI_CtrSource(3),
190 NI_CtrGate(0),
191 NI_CtrGate(1),
192 NI_CtrGate(2),
193 NI_CtrGate(3),
194 NI_CtrArmStartTrigger(0),
195 NI_CtrArmStartTrigger(1),
196 NI_CtrArmStartTrigger(2),
197 NI_CtrArmStartTrigger(3),
198 NI_CtrInternalOutput(0),
199 NI_CtrInternalOutput(1),
200 NI_CtrInternalOutput(2),
201 NI_CtrInternalOutput(3),
202 NI_CtrSampleClock(0),
203 NI_CtrSampleClock(1),
204 NI_CtrSampleClock(2),
205 NI_CtrSampleClock(3),
206 NI_AO_SampleClock,
207 NI_AO_StartTrigger,
208 NI_AO_PauseTrigger,
209 NI_DI_SampleClock,
210 NI_DI_StartTrigger,
211 NI_DI_ReferenceTrigger,
212 NI_DI_PauseTrigger,
213 NI_DO_SampleClock,
214 NI_DO_StartTrigger,
215 NI_DO_PauseTrigger,
216 NI_10MHzRefClock,
217 NI_ChangeDetectionEvent,
218 NI_WatchdogExpiredEvent,
219 0, /* Termination */
220 }
221 },
222 {
223 .dest = NI_PFI(4),
224 .src = (int[]){
225 TRIGGER_LINE(0),
226 TRIGGER_LINE(1),
227 TRIGGER_LINE(2),
228 TRIGGER_LINE(3),
229 TRIGGER_LINE(4),
230 TRIGGER_LINE(5),
231 TRIGGER_LINE(6),
232 TRIGGER_LINE(7),
233 NI_CtrSource(0),
234 NI_CtrSource(1),
235 NI_CtrSource(2),
236 NI_CtrSource(3),
237 NI_CtrGate(0),
238 NI_CtrGate(1),
239 NI_CtrGate(2),
240 NI_CtrGate(3),
241 NI_CtrArmStartTrigger(0),
242 NI_CtrArmStartTrigger(1),
243 NI_CtrArmStartTrigger(2),
244 NI_CtrArmStartTrigger(3),
245 NI_CtrInternalOutput(0),
246 NI_CtrInternalOutput(1),
247 NI_CtrInternalOutput(2),
248 NI_CtrInternalOutput(3),
249 NI_CtrSampleClock(0),
250 NI_CtrSampleClock(1),
251 NI_CtrSampleClock(2),
252 NI_CtrSampleClock(3),
253 NI_AO_SampleClock,
254 NI_AO_StartTrigger,
255 NI_AO_PauseTrigger,
256 NI_DI_SampleClock,
257 NI_DI_StartTrigger,
258 NI_DI_ReferenceTrigger,
259 NI_DI_PauseTrigger,
260 NI_DO_SampleClock,
261 NI_DO_StartTrigger,
262 NI_DO_PauseTrigger,
263 NI_10MHzRefClock,
264 NI_ChangeDetectionEvent,
265 NI_WatchdogExpiredEvent,
266 0, /* Termination */
267 }
268 },
269 {
270 .dest = NI_PFI(5),
271 .src = (int[]){
272 TRIGGER_LINE(0),
273 TRIGGER_LINE(1),
274 TRIGGER_LINE(2),
275 TRIGGER_LINE(3),
276 TRIGGER_LINE(4),
277 TRIGGER_LINE(5),
278 TRIGGER_LINE(6),
279 TRIGGER_LINE(7),
280 NI_CtrSource(0),
281 NI_CtrSource(1),
282 NI_CtrSource(2),
283 NI_CtrSource(3),
284 NI_CtrGate(0),
285 NI_CtrGate(1),
286 NI_CtrGate(2),
287 NI_CtrGate(3),
288 NI_CtrArmStartTrigger(0),
289 NI_CtrArmStartTrigger(1),
290 NI_CtrArmStartTrigger(2),
291 NI_CtrArmStartTrigger(3),
292 NI_CtrInternalOutput(0),
293 NI_CtrInternalOutput(1),
294 NI_CtrInternalOutput(2),
295 NI_CtrInternalOutput(3),
296 NI_CtrSampleClock(0),
297 NI_CtrSampleClock(1),
298 NI_CtrSampleClock(2),
299 NI_CtrSampleClock(3),
300 NI_AO_SampleClock,
301 NI_AO_StartTrigger,
302 NI_AO_PauseTrigger,
303 NI_DI_SampleClock,
304 NI_DI_StartTrigger,
305 NI_DI_ReferenceTrigger,
306 NI_DI_PauseTrigger,
307 NI_DO_SampleClock,
308 NI_DO_StartTrigger,
309 NI_DO_PauseTrigger,
310 NI_10MHzRefClock,
311 NI_ChangeDetectionEvent,
312 NI_WatchdogExpiredEvent,
313 0, /* Termination */
314 }
315 },
316 {
317 .dest = NI_PFI(6),
318 .src = (int[]){
319 TRIGGER_LINE(0),
320 TRIGGER_LINE(1),
321 TRIGGER_LINE(2),
322 TRIGGER_LINE(3),
323 TRIGGER_LINE(4),
324 TRIGGER_LINE(5),
325 TRIGGER_LINE(6),
326 TRIGGER_LINE(7),
327 NI_CtrSource(0),
328 NI_CtrSource(1),
329 NI_CtrSource(2),
330 NI_CtrSource(3),
331 NI_CtrGate(0),
332 NI_CtrGate(1),
333 NI_CtrGate(2),
334 NI_CtrGate(3),
335 NI_CtrArmStartTrigger(0),
336 NI_CtrArmStartTrigger(1),
337 NI_CtrArmStartTrigger(2),
338 NI_CtrArmStartTrigger(3),
339 NI_CtrInternalOutput(0),
340 NI_CtrInternalOutput(1),
341 NI_CtrInternalOutput(2),
342 NI_CtrInternalOutput(3),
343 NI_CtrSampleClock(0),
344 NI_CtrSampleClock(1),
345 NI_CtrSampleClock(2),
346 NI_CtrSampleClock(3),
347 NI_AO_SampleClock,
348 NI_AO_StartTrigger,
349 NI_AO_PauseTrigger,
350 NI_DI_SampleClock,
351 NI_DI_StartTrigger,
352 NI_DI_ReferenceTrigger,
353 NI_DI_PauseTrigger,
354 NI_DO_SampleClock,
355 NI_DO_StartTrigger,
356 NI_DO_PauseTrigger,
357 NI_10MHzRefClock,
358 NI_ChangeDetectionEvent,
359 NI_WatchdogExpiredEvent,
360 0, /* Termination */
361 }
362 },
363 {
364 .dest = NI_PFI(7),
365 .src = (int[]){
366 TRIGGER_LINE(0),
367 TRIGGER_LINE(1),
368 TRIGGER_LINE(2),
369 TRIGGER_LINE(3),
370 TRIGGER_LINE(4),
371 TRIGGER_LINE(5),
372 TRIGGER_LINE(6),
373 TRIGGER_LINE(7),
374 NI_CtrSource(0),
375 NI_CtrSource(1),
376 NI_CtrSource(2),
377 NI_CtrSource(3),
378 NI_CtrGate(0),
379 NI_CtrGate(1),
380 NI_CtrGate(2),
381 NI_CtrGate(3),
382 NI_CtrArmStartTrigger(0),
383 NI_CtrArmStartTrigger(1),
384 NI_CtrArmStartTrigger(2),
385 NI_CtrArmStartTrigger(3),
386 NI_CtrInternalOutput(0),
387 NI_CtrInternalOutput(1),
388 NI_CtrInternalOutput(2),
389 NI_CtrInternalOutput(3),
390 NI_CtrSampleClock(0),
391 NI_CtrSampleClock(1),
392 NI_CtrSampleClock(2),
393 NI_CtrSampleClock(3),
394 NI_AO_SampleClock,
395 NI_AO_StartTrigger,
396 NI_AO_PauseTrigger,
397 NI_DI_SampleClock,
398 NI_DI_StartTrigger,
399 NI_DI_ReferenceTrigger,
400 NI_DI_PauseTrigger,
401 NI_DO_SampleClock,
402 NI_DO_StartTrigger,
403 NI_DO_PauseTrigger,
404 NI_10MHzRefClock,
405 NI_ChangeDetectionEvent,
406 NI_WatchdogExpiredEvent,
407 0, /* Termination */
408 }
409 },
410 {
411 .dest = TRIGGER_LINE(0),
412 .src = (int[]){
413 NI_PFI(0),
414 NI_PFI(1),
415 NI_PFI(2),
416 NI_PFI(3),
417 NI_PFI(4),
418 NI_PFI(5),
419 NI_PFI(6),
420 NI_PFI(7),
421 NI_CtrSource(0),
422 NI_CtrSource(1),
423 NI_CtrSource(2),
424 NI_CtrSource(3),
425 NI_CtrGate(0),
426 NI_CtrGate(1),
427 NI_CtrGate(2),
428 NI_CtrGate(3),
429 NI_CtrZ(0),
430 NI_CtrZ(1),
431 NI_CtrZ(2),
432 NI_CtrZ(3),
433 NI_CtrArmStartTrigger(0),
434 NI_CtrArmStartTrigger(1),
435 NI_CtrArmStartTrigger(2),
436 NI_CtrArmStartTrigger(3),
437 NI_CtrInternalOutput(0),
438 NI_CtrInternalOutput(1),
439 NI_CtrInternalOutput(2),
440 NI_CtrInternalOutput(3),
441 NI_CtrSampleClock(0),
442 NI_CtrSampleClock(1),
443 NI_CtrSampleClock(2),
444 NI_CtrSampleClock(3),
445 NI_AO_SampleClock,
446 NI_AO_StartTrigger,
447 NI_AO_PauseTrigger,
448 NI_DI_SampleClock,
449 NI_DI_StartTrigger,
450 NI_DI_ReferenceTrigger,
451 NI_DI_PauseTrigger,
452 NI_DO_SampleClock,
453 NI_DO_StartTrigger,
454 NI_DO_PauseTrigger,
455 NI_10MHzRefClock,
456 NI_ChangeDetectionEvent,
457 NI_WatchdogExpiredEvent,
458 0, /* Termination */
459 }
460 },
461 {
462 .dest = TRIGGER_LINE(1),
463 .src = (int[]){
464 NI_PFI(0),
465 NI_PFI(1),
466 NI_PFI(2),
467 NI_PFI(3),
468 NI_PFI(4),
469 NI_PFI(5),
470 NI_PFI(6),
471 NI_PFI(7),
472 NI_CtrSource(0),
473 NI_CtrSource(1),
474 NI_CtrSource(2),
475 NI_CtrSource(3),
476 NI_CtrGate(0),
477 NI_CtrGate(1),
478 NI_CtrGate(2),
479 NI_CtrGate(3),
480 NI_CtrZ(0),
481 NI_CtrZ(1),
482 NI_CtrZ(2),
483 NI_CtrZ(3),
484 NI_CtrArmStartTrigger(0),
485 NI_CtrArmStartTrigger(1),
486 NI_CtrArmStartTrigger(2),
487 NI_CtrArmStartTrigger(3),
488 NI_CtrInternalOutput(0),
489 NI_CtrInternalOutput(1),
490 NI_CtrInternalOutput(2),
491 NI_CtrInternalOutput(3),
492 NI_CtrSampleClock(0),
493 NI_CtrSampleClock(1),
494 NI_CtrSampleClock(2),
495 NI_CtrSampleClock(3),
496 NI_AO_SampleClock,
497 NI_AO_StartTrigger,
498 NI_AO_PauseTrigger,
499 NI_DI_SampleClock,
500 NI_DI_StartTrigger,
501 NI_DI_ReferenceTrigger,
502 NI_DI_PauseTrigger,
503 NI_DO_SampleClock,
504 NI_DO_StartTrigger,
505 NI_DO_PauseTrigger,
506 NI_10MHzRefClock,
507 NI_ChangeDetectionEvent,
508 NI_WatchdogExpiredEvent,
509 0, /* Termination */
510 }
511 },
512 {
513 .dest = TRIGGER_LINE(2),
514 .src = (int[]){
515 NI_PFI(0),
516 NI_PFI(1),
517 NI_PFI(2),
518 NI_PFI(3),
519 NI_PFI(4),
520 NI_PFI(5),
521 NI_PFI(6),
522 NI_PFI(7),
523 NI_CtrSource(0),
524 NI_CtrSource(1),
525 NI_CtrSource(2),
526 NI_CtrSource(3),
527 NI_CtrGate(0),
528 NI_CtrGate(1),
529 NI_CtrGate(2),
530 NI_CtrGate(3),
531 NI_CtrZ(0),
532 NI_CtrZ(1),
533 NI_CtrZ(2),
534 NI_CtrZ(3),
535 NI_CtrArmStartTrigger(0),
536 NI_CtrArmStartTrigger(1),
537 NI_CtrArmStartTrigger(2),
538 NI_CtrArmStartTrigger(3),
539 NI_CtrInternalOutput(0),
540 NI_CtrInternalOutput(1),
541 NI_CtrInternalOutput(2),
542 NI_CtrInternalOutput(3),
543 NI_CtrSampleClock(0),
544 NI_CtrSampleClock(1),
545 NI_CtrSampleClock(2),
546 NI_CtrSampleClock(3),
547 NI_AO_SampleClock,
548 NI_AO_StartTrigger,
549 NI_AO_PauseTrigger,
550 NI_DI_SampleClock,
551 NI_DI_StartTrigger,
552 NI_DI_ReferenceTrigger,
553 NI_DI_PauseTrigger,
554 NI_DO_SampleClock,
555 NI_DO_StartTrigger,
556 NI_DO_PauseTrigger,
557 NI_10MHzRefClock,
558 NI_ChangeDetectionEvent,
559 NI_WatchdogExpiredEvent,
560 0, /* Termination */
561 }
562 },
563 {
564 .dest = TRIGGER_LINE(3),
565 .src = (int[]){
566 NI_PFI(0),
567 NI_PFI(1),
568 NI_PFI(2),
569 NI_PFI(3),
570 NI_PFI(4),
571 NI_PFI(5),
572 NI_PFI(6),
573 NI_PFI(7),
574 NI_CtrSource(0),
575 NI_CtrSource(1),
576 NI_CtrSource(2),
577 NI_CtrSource(3),
578 NI_CtrGate(0),
579 NI_CtrGate(1),
580 NI_CtrGate(2),
581 NI_CtrGate(3),
582 NI_CtrZ(0),
583 NI_CtrZ(1),
584 NI_CtrZ(2),
585 NI_CtrZ(3),
586 NI_CtrArmStartTrigger(0),
587 NI_CtrArmStartTrigger(1),
588 NI_CtrArmStartTrigger(2),
589 NI_CtrArmStartTrigger(3),
590 NI_CtrInternalOutput(0),
591 NI_CtrInternalOutput(1),
592 NI_CtrInternalOutput(2),
593 NI_CtrInternalOutput(3),
594 NI_CtrSampleClock(0),
595 NI_CtrSampleClock(1),
596 NI_CtrSampleClock(2),
597 NI_CtrSampleClock(3),
598 NI_AO_SampleClock,
599 NI_AO_StartTrigger,
600 NI_AO_PauseTrigger,
601 NI_DI_SampleClock,
602 NI_DI_StartTrigger,
603 NI_DI_ReferenceTrigger,
604 NI_DI_PauseTrigger,
605 NI_DO_SampleClock,
606 NI_DO_StartTrigger,
607 NI_DO_PauseTrigger,
608 NI_10MHzRefClock,
609 NI_ChangeDetectionEvent,
610 NI_WatchdogExpiredEvent,
611 0, /* Termination */
612 }
613 },
614 {
615 .dest = TRIGGER_LINE(4),
616 .src = (int[]){
617 NI_PFI(0),
618 NI_PFI(1),
619 NI_PFI(2),
620 NI_PFI(3),
621 NI_PFI(4),
622 NI_PFI(5),
623 NI_PFI(6),
624 NI_PFI(7),
625 NI_CtrSource(0),
626 NI_CtrSource(1),
627 NI_CtrSource(2),
628 NI_CtrSource(3),
629 NI_CtrGate(0),
630 NI_CtrGate(1),
631 NI_CtrGate(2),
632 NI_CtrGate(3),
633 NI_CtrZ(0),
634 NI_CtrZ(1),
635 NI_CtrZ(2),
636 NI_CtrZ(3),
637 NI_CtrArmStartTrigger(0),
638 NI_CtrArmStartTrigger(1),
639 NI_CtrArmStartTrigger(2),
640 NI_CtrArmStartTrigger(3),
641 NI_CtrInternalOutput(0),
642 NI_CtrInternalOutput(1),
643 NI_CtrInternalOutput(2),
644 NI_CtrInternalOutput(3),
645 NI_CtrSampleClock(0),
646 NI_CtrSampleClock(1),
647 NI_CtrSampleClock(2),
648 NI_CtrSampleClock(3),
649 NI_AO_SampleClock,
650 NI_AO_StartTrigger,
651 NI_AO_PauseTrigger,
652 NI_DI_SampleClock,
653 NI_DI_StartTrigger,
654 NI_DI_ReferenceTrigger,
655 NI_DI_PauseTrigger,
656 NI_DO_SampleClock,
657 NI_DO_StartTrigger,
658 NI_DO_PauseTrigger,
659 NI_10MHzRefClock,
660 NI_ChangeDetectionEvent,
661 NI_WatchdogExpiredEvent,
662 0, /* Termination */
663 }
664 },
665 {
666 .dest = TRIGGER_LINE(5),
667 .src = (int[]){
668 NI_PFI(0),
669 NI_PFI(1),
670 NI_PFI(2),
671 NI_PFI(3),
672 NI_PFI(4),
673 NI_PFI(5),
674 NI_PFI(6),
675 NI_PFI(7),
676 NI_CtrSource(0),
677 NI_CtrSource(1),
678 NI_CtrSource(2),
679 NI_CtrSource(3),
680 NI_CtrGate(0),
681 NI_CtrGate(1),
682 NI_CtrGate(2),
683 NI_CtrGate(3),
684 NI_CtrZ(0),
685 NI_CtrZ(1),
686 NI_CtrZ(2),
687 NI_CtrZ(3),
688 NI_CtrArmStartTrigger(0),
689 NI_CtrArmStartTrigger(1),
690 NI_CtrArmStartTrigger(2),
691 NI_CtrArmStartTrigger(3),
692 NI_CtrInternalOutput(0),
693 NI_CtrInternalOutput(1),
694 NI_CtrInternalOutput(2),
695 NI_CtrInternalOutput(3),
696 NI_CtrSampleClock(0),
697 NI_CtrSampleClock(1),
698 NI_CtrSampleClock(2),
699 NI_CtrSampleClock(3),
700 NI_AO_SampleClock,
701 NI_AO_StartTrigger,
702 NI_AO_PauseTrigger,
703 NI_DI_SampleClock,
704 NI_DI_StartTrigger,
705 NI_DI_ReferenceTrigger,
706 NI_DI_PauseTrigger,
707 NI_DO_SampleClock,
708 NI_DO_StartTrigger,
709 NI_DO_PauseTrigger,
710 NI_10MHzRefClock,
711 NI_ChangeDetectionEvent,
712 NI_WatchdogExpiredEvent,
713 0, /* Termination */
714 }
715 },
716 {
717 .dest = TRIGGER_LINE(6),
718 .src = (int[]){
719 NI_PFI(0),
720 NI_PFI(1),
721 NI_PFI(2),
722 NI_PFI(3),
723 NI_PFI(4),
724 NI_PFI(5),
725 NI_PFI(6),
726 NI_PFI(7),
727 NI_CtrSource(0),
728 NI_CtrSource(1),
729 NI_CtrSource(2),
730 NI_CtrSource(3),
731 NI_CtrGate(0),
732 NI_CtrGate(1),
733 NI_CtrGate(2),
734 NI_CtrGate(3),
735 NI_CtrZ(0),
736 NI_CtrZ(1),
737 NI_CtrZ(2),
738 NI_CtrZ(3),
739 NI_CtrArmStartTrigger(0),
740 NI_CtrArmStartTrigger(1),
741 NI_CtrArmStartTrigger(2),
742 NI_CtrArmStartTrigger(3),
743 NI_CtrInternalOutput(0),
744 NI_CtrInternalOutput(1),
745 NI_CtrInternalOutput(2),
746 NI_CtrInternalOutput(3),
747 NI_CtrSampleClock(0),
748 NI_CtrSampleClock(1),
749 NI_CtrSampleClock(2),
750 NI_CtrSampleClock(3),
751 NI_AO_SampleClock,
752 NI_AO_StartTrigger,
753 NI_AO_PauseTrigger,
754 NI_DI_SampleClock,
755 NI_DI_StartTrigger,
756 NI_DI_ReferenceTrigger,
757 NI_DI_PauseTrigger,
758 NI_DO_SampleClock,
759 NI_DO_StartTrigger,
760 NI_DO_PauseTrigger,
761 NI_10MHzRefClock,
762 NI_ChangeDetectionEvent,
763 NI_WatchdogExpiredEvent,
764 0, /* Termination */
765 }
766 },
767 {
768 .dest = TRIGGER_LINE(7),
769 .src = (int[]){
770 NI_PFI(0),
771 NI_PFI(1),
772 NI_PFI(2),
773 NI_PFI(3),
774 NI_PFI(4),
775 NI_PFI(5),
776 NI_PFI(6),
777 NI_PFI(7),
778 NI_CtrSource(0),
779 NI_CtrSource(1),
780 NI_CtrSource(2),
781 NI_CtrSource(3),
782 NI_CtrGate(0),
783 NI_CtrGate(1),
784 NI_CtrGate(2),
785 NI_CtrGate(3),
786 NI_CtrZ(0),
787 NI_CtrZ(1),
788 NI_CtrZ(2),
789 NI_CtrZ(3),
790 NI_CtrArmStartTrigger(0),
791 NI_CtrArmStartTrigger(1),
792 NI_CtrArmStartTrigger(2),
793 NI_CtrArmStartTrigger(3),
794 NI_CtrInternalOutput(0),
795 NI_CtrInternalOutput(1),
796 NI_CtrInternalOutput(2),
797 NI_CtrInternalOutput(3),
798 NI_CtrSampleClock(0),
799 NI_CtrSampleClock(1),
800 NI_CtrSampleClock(2),
801 NI_CtrSampleClock(3),
802 NI_AO_SampleClock,
803 NI_AO_StartTrigger,
804 NI_AO_PauseTrigger,
805 NI_DI_SampleClock,
806 NI_DI_StartTrigger,
807 NI_DI_ReferenceTrigger,
808 NI_DI_PauseTrigger,
809 NI_DO_SampleClock,
810 NI_DO_StartTrigger,
811 NI_DO_PauseTrigger,
812 NI_10MHzRefClock,
813 NI_ChangeDetectionEvent,
814 NI_WatchdogExpiredEvent,
815 0, /* Termination */
816 }
817 },
818 {
819 .dest = NI_CtrSource(0),
820 .src = (int[]){
821 NI_PFI(0),
822 NI_PFI(1),
823 NI_PFI(2),
824 NI_PFI(3),
825 NI_PFI(4),
826 NI_PFI(5),
827 NI_PFI(6),
828 NI_PFI(7),
829 TRIGGER_LINE(0),
830 TRIGGER_LINE(1),
831 TRIGGER_LINE(2),
832 TRIGGER_LINE(3),
833 TRIGGER_LINE(4),
834 TRIGGER_LINE(5),
835 TRIGGER_LINE(6),
836 TRIGGER_LINE(7),
837 NI_CtrSource(1),
838 NI_CtrSource(2),
839 NI_CtrSource(3),
840 NI_CtrGate(1),
841 NI_CtrGate(2),
842 NI_CtrGate(3),
843 NI_CtrArmStartTrigger(1),
844 NI_CtrArmStartTrigger(2),
845 NI_CtrArmStartTrigger(3),
846 NI_CtrInternalOutput(0),
847 NI_CtrInternalOutput(1),
848 NI_CtrInternalOutput(2),
849 NI_CtrInternalOutput(3),
850 NI_CtrSampleClock(1),
851 NI_CtrSampleClock(2),
852 NI_CtrSampleClock(3),
853 PXI_Clk10,
854 NI_AO_SampleClock,
855 NI_AO_StartTrigger,
856 NI_AO_PauseTrigger,
857 NI_DI_SampleClock,
858 NI_DI_StartTrigger,
859 NI_DI_ReferenceTrigger,
860 NI_DI_PauseTrigger,
861 NI_DO_SampleClock,
862 NI_DO_StartTrigger,
863 NI_DO_PauseTrigger,
864 NI_20MHzTimebase,
865 NI_100MHzTimebase,
866 NI_100kHzTimebase,
867 NI_10MHzRefClock,
868 NI_ChangeDetectionEvent,
869 NI_WatchdogExpiredEvent,
870 0, /* Termination */
871 }
872 },
873 {
874 .dest = NI_CtrSource(1),
875 .src = (int[]){
876 NI_PFI(0),
877 NI_PFI(1),
878 NI_PFI(2),
879 NI_PFI(3),
880 NI_PFI(4),
881 NI_PFI(5),
882 NI_PFI(6),
883 NI_PFI(7),
884 TRIGGER_LINE(0),
885 TRIGGER_LINE(1),
886 TRIGGER_LINE(2),
887 TRIGGER_LINE(3),
888 TRIGGER_LINE(4),
889 TRIGGER_LINE(5),
890 TRIGGER_LINE(6),
891 TRIGGER_LINE(7),
892 NI_CtrSource(0),
893 NI_CtrSource(2),
894 NI_CtrSource(3),
895 NI_CtrGate(0),
896 NI_CtrGate(2),
897 NI_CtrGate(3),
898 NI_CtrArmStartTrigger(0),
899 NI_CtrArmStartTrigger(2),
900 NI_CtrArmStartTrigger(3),
901 NI_CtrInternalOutput(0),
902 NI_CtrInternalOutput(1),
903 NI_CtrInternalOutput(2),
904 NI_CtrInternalOutput(3),
905 NI_CtrSampleClock(0),
906 NI_CtrSampleClock(2),
907 NI_CtrSampleClock(3),
908 PXI_Clk10,
909 NI_AO_SampleClock,
910 NI_AO_StartTrigger,
911 NI_AO_PauseTrigger,
912 NI_DI_SampleClock,
913 NI_DI_StartTrigger,
914 NI_DI_ReferenceTrigger,
915 NI_DI_PauseTrigger,
916 NI_DO_SampleClock,
917 NI_DO_StartTrigger,
918 NI_DO_PauseTrigger,
919 NI_20MHzTimebase,
920 NI_100MHzTimebase,
921 NI_100kHzTimebase,
922 NI_10MHzRefClock,
923 NI_ChangeDetectionEvent,
924 NI_WatchdogExpiredEvent,
925 0, /* Termination */
926 }
927 },
928 {
929 .dest = NI_CtrSource(2),
930 .src = (int[]){
931 NI_PFI(0),
932 NI_PFI(1),
933 NI_PFI(2),
934 NI_PFI(3),
935 NI_PFI(4),
936 NI_PFI(5),
937 NI_PFI(6),
938 NI_PFI(7),
939 TRIGGER_LINE(0),
940 TRIGGER_LINE(1),
941 TRIGGER_LINE(2),
942 TRIGGER_LINE(3),
943 TRIGGER_LINE(4),
944 TRIGGER_LINE(5),
945 TRIGGER_LINE(6),
946 TRIGGER_LINE(7),
947 NI_CtrSource(0),
948 NI_CtrSource(1),
949 NI_CtrSource(3),
950 NI_CtrGate(0),
951 NI_CtrGate(1),
952 NI_CtrGate(3),
953 NI_CtrArmStartTrigger(0),
954 NI_CtrArmStartTrigger(1),
955 NI_CtrArmStartTrigger(3),
956 NI_CtrInternalOutput(0),
957 NI_CtrInternalOutput(1),
958 NI_CtrInternalOutput(2),
959 NI_CtrInternalOutput(3),
960 NI_CtrSampleClock(0),
961 NI_CtrSampleClock(1),
962 NI_CtrSampleClock(3),
963 PXI_Clk10,
964 NI_AO_SampleClock,
965 NI_AO_StartTrigger,
966 NI_AO_PauseTrigger,
967 NI_DI_SampleClock,
968 NI_DI_StartTrigger,
969 NI_DI_ReferenceTrigger,
970 NI_DI_PauseTrigger,
971 NI_DO_SampleClock,
972 NI_DO_StartTrigger,
973 NI_DO_PauseTrigger,
974 NI_20MHzTimebase,
975 NI_100MHzTimebase,
976 NI_100kHzTimebase,
977 NI_10MHzRefClock,
978 NI_ChangeDetectionEvent,
979 NI_WatchdogExpiredEvent,
980 0, /* Termination */
981 }
982 },
983 {
984 .dest = NI_CtrSource(3),
985 .src = (int[]){
986 NI_PFI(0),
987 NI_PFI(1),
988 NI_PFI(2),
989 NI_PFI(3),
990 NI_PFI(4),
991 NI_PFI(5),
992 NI_PFI(6),
993 NI_PFI(7),
994 TRIGGER_LINE(0),
995 TRIGGER_LINE(1),
996 TRIGGER_LINE(2),
997 TRIGGER_LINE(3),
998 TRIGGER_LINE(4),
999 TRIGGER_LINE(5),
1000 TRIGGER_LINE(6),
1001 TRIGGER_LINE(7),
1002 NI_CtrSource(0),
1003 NI_CtrSource(1),
1004 NI_CtrSource(2),
1005 NI_CtrGate(0),
1006 NI_CtrGate(1),
1007 NI_CtrGate(2),
1008 NI_CtrArmStartTrigger(0),
1009 NI_CtrArmStartTrigger(1),
1010 NI_CtrArmStartTrigger(2),
1011 NI_CtrInternalOutput(0),
1012 NI_CtrInternalOutput(1),
1013 NI_CtrInternalOutput(2),
1014 NI_CtrInternalOutput(3),
1015 NI_CtrSampleClock(0),
1016 NI_CtrSampleClock(1),
1017 NI_CtrSampleClock(2),
1018 PXI_Clk10,
1019 NI_AO_SampleClock,
1020 NI_AO_StartTrigger,
1021 NI_AO_PauseTrigger,
1022 NI_DI_SampleClock,
1023 NI_DI_StartTrigger,
1024 NI_DI_ReferenceTrigger,
1025 NI_DI_PauseTrigger,
1026 NI_DO_SampleClock,
1027 NI_DO_StartTrigger,
1028 NI_DO_PauseTrigger,
1029 NI_20MHzTimebase,
1030 NI_100MHzTimebase,
1031 NI_100kHzTimebase,
1032 NI_10MHzRefClock,
1033 NI_ChangeDetectionEvent,
1034 NI_WatchdogExpiredEvent,
1035 0, /* Termination */
1036 }
1037 },
1038 {
1039 .dest = NI_CtrGate(0),
1040 .src = (int[]){
1041 NI_PFI(0),
1042 NI_PFI(1),
1043 NI_PFI(2),
1044 NI_PFI(3),
1045 NI_PFI(4),
1046 NI_PFI(5),
1047 NI_PFI(6),
1048 NI_PFI(7),
1049 TRIGGER_LINE(0),
1050 TRIGGER_LINE(1),
1051 TRIGGER_LINE(2),
1052 TRIGGER_LINE(3),
1053 TRIGGER_LINE(4),
1054 TRIGGER_LINE(5),
1055 TRIGGER_LINE(6),
1056 TRIGGER_LINE(7),
1057 NI_CtrSource(1),
1058 NI_CtrSource(2),
1059 NI_CtrSource(3),
1060 NI_CtrGate(1),
1061 NI_CtrGate(2),
1062 NI_CtrGate(3),
1063 NI_CtrArmStartTrigger(1),
1064 NI_CtrArmStartTrigger(2),
1065 NI_CtrArmStartTrigger(3),
1066 NI_CtrInternalOutput(0),
1067 NI_CtrInternalOutput(1),
1068 NI_CtrInternalOutput(2),
1069 NI_CtrInternalOutput(3),
1070 NI_CtrSampleClock(1),
1071 NI_CtrSampleClock(2),
1072 NI_CtrSampleClock(3),
1073 NI_AO_SampleClock,
1074 NI_AO_StartTrigger,
1075 NI_AO_PauseTrigger,
1076 NI_DI_SampleClock,
1077 NI_DI_StartTrigger,
1078 NI_DI_ReferenceTrigger,
1079 NI_DI_PauseTrigger,
1080 NI_DO_SampleClock,
1081 NI_DO_StartTrigger,
1082 NI_DO_PauseTrigger,
1083 NI_10MHzRefClock,
1084 NI_ChangeDetectionEvent,
1085 NI_WatchdogExpiredEvent,
1086 0, /* Termination */
1087 }
1088 },
1089 {
1090 .dest = NI_CtrGate(1),
1091 .src = (int[]){
1092 NI_PFI(0),
1093 NI_PFI(1),
1094 NI_PFI(2),
1095 NI_PFI(3),
1096 NI_PFI(4),
1097 NI_PFI(5),
1098 NI_PFI(6),
1099 NI_PFI(7),
1100 TRIGGER_LINE(0),
1101 TRIGGER_LINE(1),
1102 TRIGGER_LINE(2),
1103 TRIGGER_LINE(3),
1104 TRIGGER_LINE(4),
1105 TRIGGER_LINE(5),
1106 TRIGGER_LINE(6),
1107 TRIGGER_LINE(7),
1108 NI_CtrSource(0),
1109 NI_CtrSource(2),
1110 NI_CtrSource(3),
1111 NI_CtrGate(0),
1112 NI_CtrGate(2),
1113 NI_CtrGate(3),
1114 NI_CtrArmStartTrigger(0),
1115 NI_CtrArmStartTrigger(2),
1116 NI_CtrArmStartTrigger(3),
1117 NI_CtrInternalOutput(0),
1118 NI_CtrInternalOutput(1),
1119 NI_CtrInternalOutput(2),
1120 NI_CtrInternalOutput(3),
1121 NI_CtrSampleClock(0),
1122 NI_CtrSampleClock(2),
1123 NI_CtrSampleClock(3),
1124 NI_AO_SampleClock,
1125 NI_AO_StartTrigger,
1126 NI_AO_PauseTrigger,
1127 NI_DI_SampleClock,
1128 NI_DI_StartTrigger,
1129 NI_DI_ReferenceTrigger,
1130 NI_DI_PauseTrigger,
1131 NI_DO_SampleClock,
1132 NI_DO_StartTrigger,
1133 NI_DO_PauseTrigger,
1134 NI_10MHzRefClock,
1135 NI_ChangeDetectionEvent,
1136 NI_WatchdogExpiredEvent,
1137 0, /* Termination */
1138 }
1139 },
1140 {
1141 .dest = NI_CtrGate(2),
1142 .src = (int[]){
1143 NI_PFI(0),
1144 NI_PFI(1),
1145 NI_PFI(2),
1146 NI_PFI(3),
1147 NI_PFI(4),
1148 NI_PFI(5),
1149 NI_PFI(6),
1150 NI_PFI(7),
1151 TRIGGER_LINE(0),
1152 TRIGGER_LINE(1),
1153 TRIGGER_LINE(2),
1154 TRIGGER_LINE(3),
1155 TRIGGER_LINE(4),
1156 TRIGGER_LINE(5),
1157 TRIGGER_LINE(6),
1158 TRIGGER_LINE(7),
1159 NI_CtrSource(0),
1160 NI_CtrSource(1),
1161 NI_CtrSource(3),
1162 NI_CtrGate(0),
1163 NI_CtrGate(1),
1164 NI_CtrGate(3),
1165 NI_CtrArmStartTrigger(0),
1166 NI_CtrArmStartTrigger(1),
1167 NI_CtrArmStartTrigger(3),
1168 NI_CtrInternalOutput(0),
1169 NI_CtrInternalOutput(1),
1170 NI_CtrInternalOutput(2),
1171 NI_CtrInternalOutput(3),
1172 NI_CtrSampleClock(0),
1173 NI_CtrSampleClock(1),
1174 NI_CtrSampleClock(3),
1175 NI_AO_SampleClock,
1176 NI_AO_StartTrigger,
1177 NI_AO_PauseTrigger,
1178 NI_DI_SampleClock,
1179 NI_DI_StartTrigger,
1180 NI_DI_ReferenceTrigger,
1181 NI_DI_PauseTrigger,
1182 NI_DO_SampleClock,
1183 NI_DO_StartTrigger,
1184 NI_DO_PauseTrigger,
1185 NI_10MHzRefClock,
1186 NI_ChangeDetectionEvent,
1187 NI_WatchdogExpiredEvent,
1188 0, /* Termination */
1189 }
1190 },
1191 {
1192 .dest = NI_CtrGate(3),
1193 .src = (int[]){
1194 NI_PFI(0),
1195 NI_PFI(1),
1196 NI_PFI(2),
1197 NI_PFI(3),
1198 NI_PFI(4),
1199 NI_PFI(5),
1200 NI_PFI(6),
1201 NI_PFI(7),
1202 TRIGGER_LINE(0),
1203 TRIGGER_LINE(1),
1204 TRIGGER_LINE(2),
1205 TRIGGER_LINE(3),
1206 TRIGGER_LINE(4),
1207 TRIGGER_LINE(5),
1208 TRIGGER_LINE(6),
1209 TRIGGER_LINE(7),
1210 NI_CtrSource(0),
1211 NI_CtrSource(1),
1212 NI_CtrSource(2),
1213 NI_CtrGate(0),
1214 NI_CtrGate(1),
1215 NI_CtrGate(2),
1216 NI_CtrArmStartTrigger(0),
1217 NI_CtrArmStartTrigger(1),
1218 NI_CtrArmStartTrigger(2),
1219 NI_CtrInternalOutput(0),
1220 NI_CtrInternalOutput(1),
1221 NI_CtrInternalOutput(2),
1222 NI_CtrInternalOutput(3),
1223 NI_CtrSampleClock(0),
1224 NI_CtrSampleClock(1),
1225 NI_CtrSampleClock(2),
1226 NI_AO_SampleClock,
1227 NI_AO_StartTrigger,
1228 NI_AO_PauseTrigger,
1229 NI_DI_SampleClock,
1230 NI_DI_StartTrigger,
1231 NI_DI_ReferenceTrigger,
1232 NI_DI_PauseTrigger,
1233 NI_DO_SampleClock,
1234 NI_DO_StartTrigger,
1235 NI_DO_PauseTrigger,
1236 NI_10MHzRefClock,
1237 NI_ChangeDetectionEvent,
1238 NI_WatchdogExpiredEvent,
1239 0, /* Termination */
1240 }
1241 },
1242 {
1243 .dest = NI_CtrAux(0),
1244 .src = (int[]){
1245 NI_PFI(0),
1246 NI_PFI(1),
1247 NI_PFI(2),
1248 NI_PFI(3),
1249 NI_PFI(4),
1250 NI_PFI(5),
1251 NI_PFI(6),
1252 NI_PFI(7),
1253 TRIGGER_LINE(0),
1254 TRIGGER_LINE(1),
1255 TRIGGER_LINE(2),
1256 TRIGGER_LINE(3),
1257 TRIGGER_LINE(4),
1258 TRIGGER_LINE(5),
1259 TRIGGER_LINE(6),
1260 TRIGGER_LINE(7),
1261 NI_CtrSource(1),
1262 NI_CtrSource(2),
1263 NI_CtrSource(3),
1264 NI_CtrGate(0),
1265 NI_CtrGate(1),
1266 NI_CtrGate(2),
1267 NI_CtrGate(3),
1268 NI_CtrArmStartTrigger(1),
1269 NI_CtrArmStartTrigger(2),
1270 NI_CtrArmStartTrigger(3),
1271 NI_CtrInternalOutput(0),
1272 NI_CtrInternalOutput(1),
1273 NI_CtrInternalOutput(2),
1274 NI_CtrInternalOutput(3),
1275 NI_CtrSampleClock(1),
1276 NI_CtrSampleClock(2),
1277 NI_CtrSampleClock(3),
1278 NI_AO_SampleClock,
1279 NI_AO_StartTrigger,
1280 NI_AO_PauseTrigger,
1281 NI_DI_SampleClock,
1282 NI_DI_StartTrigger,
1283 NI_DI_ReferenceTrigger,
1284 NI_DI_PauseTrigger,
1285 NI_DO_SampleClock,
1286 NI_DO_StartTrigger,
1287 NI_DO_PauseTrigger,
1288 NI_10MHzRefClock,
1289 NI_ChangeDetectionEvent,
1290 NI_WatchdogExpiredEvent,
1291 0, /* Termination */
1292 }
1293 },
1294 {
1295 .dest = NI_CtrAux(1),
1296 .src = (int[]){
1297 NI_PFI(0),
1298 NI_PFI(1),
1299 NI_PFI(2),
1300 NI_PFI(3),
1301 NI_PFI(4),
1302 NI_PFI(5),
1303 NI_PFI(6),
1304 NI_PFI(7),
1305 TRIGGER_LINE(0),
1306 TRIGGER_LINE(1),
1307 TRIGGER_LINE(2),
1308 TRIGGER_LINE(3),
1309 TRIGGER_LINE(4),
1310 TRIGGER_LINE(5),
1311 TRIGGER_LINE(6),
1312 TRIGGER_LINE(7),
1313 NI_CtrSource(0),
1314 NI_CtrSource(2),
1315 NI_CtrSource(3),
1316 NI_CtrGate(0),
1317 NI_CtrGate(1),
1318 NI_CtrGate(2),
1319 NI_CtrGate(3),
1320 NI_CtrArmStartTrigger(0),
1321 NI_CtrArmStartTrigger(2),
1322 NI_CtrArmStartTrigger(3),
1323 NI_CtrInternalOutput(0),
1324 NI_CtrInternalOutput(1),
1325 NI_CtrInternalOutput(2),
1326 NI_CtrInternalOutput(3),
1327 NI_CtrSampleClock(0),
1328 NI_CtrSampleClock(2),
1329 NI_CtrSampleClock(3),
1330 NI_AO_SampleClock,
1331 NI_AO_StartTrigger,
1332 NI_AO_PauseTrigger,
1333 NI_DI_SampleClock,
1334 NI_DI_StartTrigger,
1335 NI_DI_ReferenceTrigger,
1336 NI_DI_PauseTrigger,
1337 NI_DO_SampleClock,
1338 NI_DO_StartTrigger,
1339 NI_DO_PauseTrigger,
1340 NI_10MHzRefClock,
1341 NI_ChangeDetectionEvent,
1342 NI_WatchdogExpiredEvent,
1343 0, /* Termination */
1344 }
1345 },
1346 {
1347 .dest = NI_CtrAux(2),
1348 .src = (int[]){
1349 NI_PFI(0),
1350 NI_PFI(1),
1351 NI_PFI(2),
1352 NI_PFI(3),
1353 NI_PFI(4),
1354 NI_PFI(5),
1355 NI_PFI(6),
1356 NI_PFI(7),
1357 TRIGGER_LINE(0),
1358 TRIGGER_LINE(1),
1359 TRIGGER_LINE(2),
1360 TRIGGER_LINE(3),
1361 TRIGGER_LINE(4),
1362 TRIGGER_LINE(5),
1363 TRIGGER_LINE(6),
1364 TRIGGER_LINE(7),
1365 NI_CtrSource(0),
1366 NI_CtrSource(1),
1367 NI_CtrSource(3),
1368 NI_CtrGate(0),
1369 NI_CtrGate(1),
1370 NI_CtrGate(2),
1371 NI_CtrGate(3),
1372 NI_CtrArmStartTrigger(0),
1373 NI_CtrArmStartTrigger(1),
1374 NI_CtrArmStartTrigger(3),
1375 NI_CtrInternalOutput(0),
1376 NI_CtrInternalOutput(1),
1377 NI_CtrInternalOutput(2),
1378 NI_CtrInternalOutput(3),
1379 NI_CtrSampleClock(0),
1380 NI_CtrSampleClock(1),
1381 NI_CtrSampleClock(3),
1382 NI_AO_SampleClock,
1383 NI_AO_StartTrigger,
1384 NI_AO_PauseTrigger,
1385 NI_DI_SampleClock,
1386 NI_DI_StartTrigger,
1387 NI_DI_ReferenceTrigger,
1388 NI_DI_PauseTrigger,
1389 NI_DO_SampleClock,
1390 NI_DO_StartTrigger,
1391 NI_DO_PauseTrigger,
1392 NI_10MHzRefClock,
1393 NI_ChangeDetectionEvent,
1394 NI_WatchdogExpiredEvent,
1395 0, /* Termination */
1396 }
1397 },
1398 {
1399 .dest = NI_CtrAux(3),
1400 .src = (int[]){
1401 NI_PFI(0),
1402 NI_PFI(1),
1403 NI_PFI(2),
1404 NI_PFI(3),
1405 NI_PFI(4),
1406 NI_PFI(5),
1407 NI_PFI(6),
1408 NI_PFI(7),
1409 TRIGGER_LINE(0),
1410 TRIGGER_LINE(1),
1411 TRIGGER_LINE(2),
1412 TRIGGER_LINE(3),
1413 TRIGGER_LINE(4),
1414 TRIGGER_LINE(5),
1415 TRIGGER_LINE(6),
1416 TRIGGER_LINE(7),
1417 NI_CtrSource(0),
1418 NI_CtrSource(1),
1419 NI_CtrSource(2),
1420 NI_CtrGate(0),
1421 NI_CtrGate(1),
1422 NI_CtrGate(2),
1423 NI_CtrGate(3),
1424 NI_CtrArmStartTrigger(0),
1425 NI_CtrArmStartTrigger(1),
1426 NI_CtrArmStartTrigger(2),
1427 NI_CtrInternalOutput(0),
1428 NI_CtrInternalOutput(1),
1429 NI_CtrInternalOutput(2),
1430 NI_CtrInternalOutput(3),
1431 NI_CtrSampleClock(0),
1432 NI_CtrSampleClock(1),
1433 NI_CtrSampleClock(2),
1434 NI_AO_SampleClock,
1435 NI_AO_StartTrigger,
1436 NI_AO_PauseTrigger,
1437 NI_DI_SampleClock,
1438 NI_DI_StartTrigger,
1439 NI_DI_ReferenceTrigger,
1440 NI_DI_PauseTrigger,
1441 NI_DO_SampleClock,
1442 NI_DO_StartTrigger,
1443 NI_DO_PauseTrigger,
1444 NI_10MHzRefClock,
1445 NI_ChangeDetectionEvent,
1446 NI_WatchdogExpiredEvent,
1447 0, /* Termination */
1448 }
1449 },
1450 {
1451 .dest = NI_CtrA(0),
1452 .src = (int[]){
1453 NI_PFI(0),
1454 NI_PFI(1),
1455 NI_PFI(2),
1456 NI_PFI(3),
1457 NI_PFI(4),
1458 NI_PFI(5),
1459 NI_PFI(6),
1460 NI_PFI(7),
1461 TRIGGER_LINE(0),
1462 TRIGGER_LINE(1),
1463 TRIGGER_LINE(2),
1464 TRIGGER_LINE(3),
1465 TRIGGER_LINE(4),
1466 TRIGGER_LINE(5),
1467 TRIGGER_LINE(6),
1468 TRIGGER_LINE(7),
1469 NI_CtrSource(1),
1470 NI_CtrSource(2),
1471 NI_CtrSource(3),
1472 NI_CtrGate(1),
1473 NI_CtrGate(2),
1474 NI_CtrGate(3),
1475 NI_CtrArmStartTrigger(1),
1476 NI_CtrArmStartTrigger(2),
1477 NI_CtrArmStartTrigger(3),
1478 NI_CtrInternalOutput(0),
1479 NI_CtrInternalOutput(1),
1480 NI_CtrInternalOutput(2),
1481 NI_CtrInternalOutput(3),
1482 NI_CtrSampleClock(1),
1483 NI_CtrSampleClock(2),
1484 NI_CtrSampleClock(3),
1485 NI_AO_SampleClock,
1486 NI_AO_StartTrigger,
1487 NI_AO_PauseTrigger,
1488 NI_DI_SampleClock,
1489 NI_DI_StartTrigger,
1490 NI_DI_ReferenceTrigger,
1491 NI_DI_PauseTrigger,
1492 NI_DO_SampleClock,
1493 NI_DO_StartTrigger,
1494 NI_DO_PauseTrigger,
1495 NI_10MHzRefClock,
1496 NI_ChangeDetectionEvent,
1497 NI_WatchdogExpiredEvent,
1498 0, /* Termination */
1499 }
1500 },
1501 {
1502 .dest = NI_CtrA(1),
1503 .src = (int[]){
1504 NI_PFI(0),
1505 NI_PFI(1),
1506 NI_PFI(2),
1507 NI_PFI(3),
1508 NI_PFI(4),
1509 NI_PFI(5),
1510 NI_PFI(6),
1511 NI_PFI(7),
1512 TRIGGER_LINE(0),
1513 TRIGGER_LINE(1),
1514 TRIGGER_LINE(2),
1515 TRIGGER_LINE(3),
1516 TRIGGER_LINE(4),
1517 TRIGGER_LINE(5),
1518 TRIGGER_LINE(6),
1519 TRIGGER_LINE(7),
1520 NI_CtrSource(0),
1521 NI_CtrSource(2),
1522 NI_CtrSource(3),
1523 NI_CtrGate(0),
1524 NI_CtrGate(2),
1525 NI_CtrGate(3),
1526 NI_CtrArmStartTrigger(0),
1527 NI_CtrArmStartTrigger(2),
1528 NI_CtrArmStartTrigger(3),
1529 NI_CtrInternalOutput(0),
1530 NI_CtrInternalOutput(1),
1531 NI_CtrInternalOutput(2),
1532 NI_CtrInternalOutput(3),
1533 NI_CtrSampleClock(0),
1534 NI_CtrSampleClock(2),
1535 NI_CtrSampleClock(3),
1536 NI_AO_SampleClock,
1537 NI_AO_StartTrigger,
1538 NI_AO_PauseTrigger,
1539 NI_DI_SampleClock,
1540 NI_DI_StartTrigger,
1541 NI_DI_ReferenceTrigger,
1542 NI_DI_PauseTrigger,
1543 NI_DO_SampleClock,
1544 NI_DO_StartTrigger,
1545 NI_DO_PauseTrigger,
1546 NI_10MHzRefClock,
1547 NI_ChangeDetectionEvent,
1548 NI_WatchdogExpiredEvent,
1549 0, /* Termination */
1550 }
1551 },
1552 {
1553 .dest = NI_CtrA(2),
1554 .src = (int[]){
1555 NI_PFI(0),
1556 NI_PFI(1),
1557 NI_PFI(2),
1558 NI_PFI(3),
1559 NI_PFI(4),
1560 NI_PFI(5),
1561 NI_PFI(6),
1562 NI_PFI(7),
1563 TRIGGER_LINE(0),
1564 TRIGGER_LINE(1),
1565 TRIGGER_LINE(2),
1566 TRIGGER_LINE(3),
1567 TRIGGER_LINE(4),
1568 TRIGGER_LINE(5),
1569 TRIGGER_LINE(6),
1570 TRIGGER_LINE(7),
1571 NI_CtrSource(0),
1572 NI_CtrSource(1),
1573 NI_CtrSource(3),
1574 NI_CtrGate(0),
1575 NI_CtrGate(1),
1576 NI_CtrGate(3),
1577 NI_CtrArmStartTrigger(0),
1578 NI_CtrArmStartTrigger(1),
1579 NI_CtrArmStartTrigger(3),
1580 NI_CtrInternalOutput(0),
1581 NI_CtrInternalOutput(1),
1582 NI_CtrInternalOutput(2),
1583 NI_CtrInternalOutput(3),
1584 NI_CtrSampleClock(0),
1585 NI_CtrSampleClock(1),
1586 NI_CtrSampleClock(3),
1587 NI_AO_SampleClock,
1588 NI_AO_StartTrigger,
1589 NI_AO_PauseTrigger,
1590 NI_DI_SampleClock,
1591 NI_DI_StartTrigger,
1592 NI_DI_ReferenceTrigger,
1593 NI_DI_PauseTrigger,
1594 NI_DO_SampleClock,
1595 NI_DO_StartTrigger,
1596 NI_DO_PauseTrigger,
1597 NI_10MHzRefClock,
1598 NI_ChangeDetectionEvent,
1599 NI_WatchdogExpiredEvent,
1600 0, /* Termination */
1601 }
1602 },
1603 {
1604 .dest = NI_CtrA(3),
1605 .src = (int[]){
1606 NI_PFI(0),
1607 NI_PFI(1),
1608 NI_PFI(2),
1609 NI_PFI(3),
1610 NI_PFI(4),
1611 NI_PFI(5),
1612 NI_PFI(6),
1613 NI_PFI(7),
1614 TRIGGER_LINE(0),
1615 TRIGGER_LINE(1),
1616 TRIGGER_LINE(2),
1617 TRIGGER_LINE(3),
1618 TRIGGER_LINE(4),
1619 TRIGGER_LINE(5),
1620 TRIGGER_LINE(6),
1621 TRIGGER_LINE(7),
1622 NI_CtrSource(0),
1623 NI_CtrSource(1),
1624 NI_CtrSource(2),
1625 NI_CtrGate(0),
1626 NI_CtrGate(1),
1627 NI_CtrGate(2),
1628 NI_CtrArmStartTrigger(0),
1629 NI_CtrArmStartTrigger(1),
1630 NI_CtrArmStartTrigger(2),
1631 NI_CtrInternalOutput(0),
1632 NI_CtrInternalOutput(1),
1633 NI_CtrInternalOutput(2),
1634 NI_CtrInternalOutput(3),
1635 NI_CtrSampleClock(0),
1636 NI_CtrSampleClock(1),
1637 NI_CtrSampleClock(2),
1638 NI_AO_SampleClock,
1639 NI_AO_StartTrigger,
1640 NI_AO_PauseTrigger,
1641 NI_DI_SampleClock,
1642 NI_DI_StartTrigger,
1643 NI_DI_ReferenceTrigger,
1644 NI_DI_PauseTrigger,
1645 NI_DO_SampleClock,
1646 NI_DO_StartTrigger,
1647 NI_DO_PauseTrigger,
1648 NI_10MHzRefClock,
1649 NI_ChangeDetectionEvent,
1650 NI_WatchdogExpiredEvent,
1651 0, /* Termination */
1652 }
1653 },
1654 {
1655 .dest = NI_CtrB(0),
1656 .src = (int[]){
1657 NI_PFI(0),
1658 NI_PFI(1),
1659 NI_PFI(2),
1660 NI_PFI(3),
1661 NI_PFI(4),
1662 NI_PFI(5),
1663 NI_PFI(6),
1664 NI_PFI(7),
1665 TRIGGER_LINE(0),
1666 TRIGGER_LINE(1),
1667 TRIGGER_LINE(2),
1668 TRIGGER_LINE(3),
1669 TRIGGER_LINE(4),
1670 TRIGGER_LINE(5),
1671 TRIGGER_LINE(6),
1672 TRIGGER_LINE(7),
1673 NI_CtrSource(1),
1674 NI_CtrSource(2),
1675 NI_CtrSource(3),
1676 NI_CtrGate(1),
1677 NI_CtrGate(2),
1678 NI_CtrGate(3),
1679 NI_CtrArmStartTrigger(1),
1680 NI_CtrArmStartTrigger(2),
1681 NI_CtrArmStartTrigger(3),
1682 NI_CtrInternalOutput(0),
1683 NI_CtrInternalOutput(1),
1684 NI_CtrInternalOutput(2),
1685 NI_CtrInternalOutput(3),
1686 NI_CtrSampleClock(1),
1687 NI_CtrSampleClock(2),
1688 NI_CtrSampleClock(3),
1689 NI_AO_SampleClock,
1690 NI_AO_StartTrigger,
1691 NI_AO_PauseTrigger,
1692 NI_DI_SampleClock,
1693 NI_DI_StartTrigger,
1694 NI_DI_ReferenceTrigger,
1695 NI_DI_PauseTrigger,
1696 NI_DO_SampleClock,
1697 NI_DO_StartTrigger,
1698 NI_DO_PauseTrigger,
1699 NI_10MHzRefClock,
1700 NI_ChangeDetectionEvent,
1701 NI_WatchdogExpiredEvent,
1702 0, /* Termination */
1703 }
1704 },
1705 {
1706 .dest = NI_CtrB(1),
1707 .src = (int[]){
1708 NI_PFI(0),
1709 NI_PFI(1),
1710 NI_PFI(2),
1711 NI_PFI(3),
1712 NI_PFI(4),
1713 NI_PFI(5),
1714 NI_PFI(6),
1715 NI_PFI(7),
1716 TRIGGER_LINE(0),
1717 TRIGGER_LINE(1),
1718 TRIGGER_LINE(2),
1719 TRIGGER_LINE(3),
1720 TRIGGER_LINE(4),
1721 TRIGGER_LINE(5),
1722 TRIGGER_LINE(6),
1723 TRIGGER_LINE(7),
1724 NI_CtrSource(0),
1725 NI_CtrSource(2),
1726 NI_CtrSource(3),
1727 NI_CtrGate(0),
1728 NI_CtrGate(2),
1729 NI_CtrGate(3),
1730 NI_CtrArmStartTrigger(0),
1731 NI_CtrArmStartTrigger(2),
1732 NI_CtrArmStartTrigger(3),
1733 NI_CtrInternalOutput(0),
1734 NI_CtrInternalOutput(1),
1735 NI_CtrInternalOutput(2),
1736 NI_CtrInternalOutput(3),
1737 NI_CtrSampleClock(0),
1738 NI_CtrSampleClock(2),
1739 NI_CtrSampleClock(3),
1740 NI_AO_SampleClock,
1741 NI_AO_StartTrigger,
1742 NI_AO_PauseTrigger,
1743 NI_DI_SampleClock,
1744 NI_DI_StartTrigger,
1745 NI_DI_ReferenceTrigger,
1746 NI_DI_PauseTrigger,
1747 NI_DO_SampleClock,
1748 NI_DO_StartTrigger,
1749 NI_DO_PauseTrigger,
1750 NI_10MHzRefClock,
1751 NI_ChangeDetectionEvent,
1752 NI_WatchdogExpiredEvent,
1753 0, /* Termination */
1754 }
1755 },
1756 {
1757 .dest = NI_CtrB(2),
1758 .src = (int[]){
1759 NI_PFI(0),
1760 NI_PFI(1),
1761 NI_PFI(2),
1762 NI_PFI(3),
1763 NI_PFI(4),
1764 NI_PFI(5),
1765 NI_PFI(6),
1766 NI_PFI(7),
1767 TRIGGER_LINE(0),
1768 TRIGGER_LINE(1),
1769 TRIGGER_LINE(2),
1770 TRIGGER_LINE(3),
1771 TRIGGER_LINE(4),
1772 TRIGGER_LINE(5),
1773 TRIGGER_LINE(6),
1774 TRIGGER_LINE(7),
1775 NI_CtrSource(0),
1776 NI_CtrSource(1),
1777 NI_CtrSource(3),
1778 NI_CtrGate(0),
1779 NI_CtrGate(1),
1780 NI_CtrGate(3),
1781 NI_CtrArmStartTrigger(0),
1782 NI_CtrArmStartTrigger(1),
1783 NI_CtrArmStartTrigger(3),
1784 NI_CtrInternalOutput(0),
1785 NI_CtrInternalOutput(1),
1786 NI_CtrInternalOutput(2),
1787 NI_CtrInternalOutput(3),
1788 NI_CtrSampleClock(0),
1789 NI_CtrSampleClock(1),
1790 NI_CtrSampleClock(3),
1791 NI_AO_SampleClock,
1792 NI_AO_StartTrigger,
1793 NI_AO_PauseTrigger,
1794 NI_DI_SampleClock,
1795 NI_DI_StartTrigger,
1796 NI_DI_ReferenceTrigger,
1797 NI_DI_PauseTrigger,
1798 NI_DO_SampleClock,
1799 NI_DO_StartTrigger,
1800 NI_DO_PauseTrigger,
1801 NI_10MHzRefClock,
1802 NI_ChangeDetectionEvent,
1803 NI_WatchdogExpiredEvent,
1804 0, /* Termination */
1805 }
1806 },
1807 {
1808 .dest = NI_CtrB(3),
1809 .src = (int[]){
1810 NI_PFI(0),
1811 NI_PFI(1),
1812 NI_PFI(2),
1813 NI_PFI(3),
1814 NI_PFI(4),
1815 NI_PFI(5),
1816 NI_PFI(6),
1817 NI_PFI(7),
1818 TRIGGER_LINE(0),
1819 TRIGGER_LINE(1),
1820 TRIGGER_LINE(2),
1821 TRIGGER_LINE(3),
1822 TRIGGER_LINE(4),
1823 TRIGGER_LINE(5),
1824 TRIGGER_LINE(6),
1825 TRIGGER_LINE(7),
1826 NI_CtrSource(0),
1827 NI_CtrSource(1),
1828 NI_CtrSource(2),
1829 NI_CtrGate(0),
1830 NI_CtrGate(1),
1831 NI_CtrGate(2),
1832 NI_CtrArmStartTrigger(0),
1833 NI_CtrArmStartTrigger(1),
1834 NI_CtrArmStartTrigger(2),
1835 NI_CtrInternalOutput(0),
1836 NI_CtrInternalOutput(1),
1837 NI_CtrInternalOutput(2),
1838 NI_CtrInternalOutput(3),
1839 NI_CtrSampleClock(0),
1840 NI_CtrSampleClock(1),
1841 NI_CtrSampleClock(2),
1842 NI_AO_SampleClock,
1843 NI_AO_StartTrigger,
1844 NI_AO_PauseTrigger,
1845 NI_DI_SampleClock,
1846 NI_DI_StartTrigger,
1847 NI_DI_ReferenceTrigger,
1848 NI_DI_PauseTrigger,
1849 NI_DO_SampleClock,
1850 NI_DO_StartTrigger,
1851 NI_DO_PauseTrigger,
1852 NI_10MHzRefClock,
1853 NI_ChangeDetectionEvent,
1854 NI_WatchdogExpiredEvent,
1855 0, /* Termination */
1856 }
1857 },
1858 {
1859 .dest = NI_CtrZ(0),
1860 .src = (int[]){
1861 NI_PFI(0),
1862 NI_PFI(1),
1863 NI_PFI(2),
1864 NI_PFI(3),
1865 NI_PFI(4),
1866 NI_PFI(5),
1867 NI_PFI(6),
1868 NI_PFI(7),
1869 TRIGGER_LINE(0),
1870 TRIGGER_LINE(1),
1871 TRIGGER_LINE(2),
1872 TRIGGER_LINE(3),
1873 TRIGGER_LINE(4),
1874 TRIGGER_LINE(5),
1875 TRIGGER_LINE(6),
1876 TRIGGER_LINE(7),
1877 NI_CtrSource(1),
1878 NI_CtrSource(2),
1879 NI_CtrSource(3),
1880 NI_CtrGate(1),
1881 NI_CtrGate(2),
1882 NI_CtrGate(3),
1883 NI_CtrArmStartTrigger(1),
1884 NI_CtrArmStartTrigger(2),
1885 NI_CtrArmStartTrigger(3),
1886 NI_CtrInternalOutput(0),
1887 NI_CtrInternalOutput(1),
1888 NI_CtrInternalOutput(2),
1889 NI_CtrInternalOutput(3),
1890 NI_CtrSampleClock(1),
1891 NI_CtrSampleClock(2),
1892 NI_CtrSampleClock(3),
1893 NI_AO_SampleClock,
1894 NI_AO_StartTrigger,
1895 NI_AO_PauseTrigger,
1896 NI_DI_SampleClock,
1897 NI_DI_StartTrigger,
1898 NI_DI_ReferenceTrigger,
1899 NI_DI_PauseTrigger,
1900 NI_DO_SampleClock,
1901 NI_DO_StartTrigger,
1902 NI_DO_PauseTrigger,
1903 NI_10MHzRefClock,
1904 NI_ChangeDetectionEvent,
1905 NI_WatchdogExpiredEvent,
1906 0, /* Termination */
1907 }
1908 },
1909 {
1910 .dest = NI_CtrZ(1),
1911 .src = (int[]){
1912 NI_PFI(0),
1913 NI_PFI(1),
1914 NI_PFI(2),
1915 NI_PFI(3),
1916 NI_PFI(4),
1917 NI_PFI(5),
1918 NI_PFI(6),
1919 NI_PFI(7),
1920 TRIGGER_LINE(0),
1921 TRIGGER_LINE(1),
1922 TRIGGER_LINE(2),
1923 TRIGGER_LINE(3),
1924 TRIGGER_LINE(4),
1925 TRIGGER_LINE(5),
1926 TRIGGER_LINE(6),
1927 TRIGGER_LINE(7),
1928 NI_CtrSource(0),
1929 NI_CtrSource(2),
1930 NI_CtrSource(3),
1931 NI_CtrGate(0),
1932 NI_CtrGate(2),
1933 NI_CtrGate(3),
1934 NI_CtrArmStartTrigger(0),
1935 NI_CtrArmStartTrigger(2),
1936 NI_CtrArmStartTrigger(3),
1937 NI_CtrInternalOutput(0),
1938 NI_CtrInternalOutput(1),
1939 NI_CtrInternalOutput(2),
1940 NI_CtrInternalOutput(3),
1941 NI_CtrSampleClock(0),
1942 NI_CtrSampleClock(2),
1943 NI_CtrSampleClock(3),
1944 NI_AO_SampleClock,
1945 NI_AO_StartTrigger,
1946 NI_AO_PauseTrigger,
1947 NI_DI_SampleClock,
1948 NI_DI_StartTrigger,
1949 NI_DI_ReferenceTrigger,
1950 NI_DI_PauseTrigger,
1951 NI_DO_SampleClock,
1952 NI_DO_StartTrigger,
1953 NI_DO_PauseTrigger,
1954 NI_10MHzRefClock,
1955 NI_ChangeDetectionEvent,
1956 NI_WatchdogExpiredEvent,
1957 0, /* Termination */
1958 }
1959 },
1960 {
1961 .dest = NI_CtrZ(2),
1962 .src = (int[]){
1963 NI_PFI(0),
1964 NI_PFI(1),
1965 NI_PFI(2),
1966 NI_PFI(3),
1967 NI_PFI(4),
1968 NI_PFI(5),
1969 NI_PFI(6),
1970 NI_PFI(7),
1971 TRIGGER_LINE(0),
1972 TRIGGER_LINE(1),
1973 TRIGGER_LINE(2),
1974 TRIGGER_LINE(3),
1975 TRIGGER_LINE(4),
1976 TRIGGER_LINE(5),
1977 TRIGGER_LINE(6),
1978 TRIGGER_LINE(7),
1979 NI_CtrSource(0),
1980 NI_CtrSource(1),
1981 NI_CtrSource(3),
1982 NI_CtrGate(0),
1983 NI_CtrGate(1),
1984 NI_CtrGate(3),
1985 NI_CtrArmStartTrigger(0),
1986 NI_CtrArmStartTrigger(1),
1987 NI_CtrArmStartTrigger(3),
1988 NI_CtrInternalOutput(0),
1989 NI_CtrInternalOutput(1),
1990 NI_CtrInternalOutput(2),
1991 NI_CtrInternalOutput(3),
1992 NI_CtrSampleClock(0),
1993 NI_CtrSampleClock(1),
1994 NI_CtrSampleClock(3),
1995 NI_AO_SampleClock,
1996 NI_AO_StartTrigger,
1997 NI_AO_PauseTrigger,
1998 NI_DI_SampleClock,
1999 NI_DI_StartTrigger,
2000 NI_DI_ReferenceTrigger,
2001 NI_DI_PauseTrigger,
2002 NI_DO_SampleClock,
2003 NI_DO_StartTrigger,
2004 NI_DO_PauseTrigger,
2005 NI_10MHzRefClock,
2006 NI_ChangeDetectionEvent,
2007 NI_WatchdogExpiredEvent,
2008 0, /* Termination */
2009 }
2010 },
2011 {
2012 .dest = NI_CtrZ(3),
2013 .src = (int[]){
2014 NI_PFI(0),
2015 NI_PFI(1),
2016 NI_PFI(2),
2017 NI_PFI(3),
2018 NI_PFI(4),
2019 NI_PFI(5),
2020 NI_PFI(6),
2021 NI_PFI(7),
2022 TRIGGER_LINE(0),
2023 TRIGGER_LINE(1),
2024 TRIGGER_LINE(2),
2025 TRIGGER_LINE(3),
2026 TRIGGER_LINE(4),
2027 TRIGGER_LINE(5),
2028 TRIGGER_LINE(6),
2029 TRIGGER_LINE(7),
2030 NI_CtrSource(0),
2031 NI_CtrSource(1),
2032 NI_CtrSource(2),
2033 NI_CtrGate(0),
2034 NI_CtrGate(1),
2035 NI_CtrGate(2),
2036 NI_CtrArmStartTrigger(0),
2037 NI_CtrArmStartTrigger(1),
2038 NI_CtrArmStartTrigger(2),
2039 NI_CtrInternalOutput(0),
2040 NI_CtrInternalOutput(1),
2041 NI_CtrInternalOutput(2),
2042 NI_CtrInternalOutput(3),
2043 NI_CtrSampleClock(0),
2044 NI_CtrSampleClock(1),
2045 NI_CtrSampleClock(2),
2046 NI_AO_SampleClock,
2047 NI_AO_StartTrigger,
2048 NI_AO_PauseTrigger,
2049 NI_DI_SampleClock,
2050 NI_DI_StartTrigger,
2051 NI_DI_ReferenceTrigger,
2052 NI_DI_PauseTrigger,
2053 NI_DO_SampleClock,
2054 NI_DO_StartTrigger,
2055 NI_DO_PauseTrigger,
2056 NI_10MHzRefClock,
2057 NI_ChangeDetectionEvent,
2058 NI_WatchdogExpiredEvent,
2059 0, /* Termination */
2060 }
2061 },
2062 {
2063 .dest = NI_CtrArmStartTrigger(0),
2064 .src = (int[]){
2065 NI_PFI(0),
2066 NI_PFI(1),
2067 NI_PFI(2),
2068 NI_PFI(3),
2069 NI_PFI(4),
2070 NI_PFI(5),
2071 NI_PFI(6),
2072 NI_PFI(7),
2073 TRIGGER_LINE(0),
2074 TRIGGER_LINE(1),
2075 TRIGGER_LINE(2),
2076 TRIGGER_LINE(3),
2077 TRIGGER_LINE(4),
2078 TRIGGER_LINE(5),
2079 TRIGGER_LINE(6),
2080 TRIGGER_LINE(7),
2081 NI_CtrSource(1),
2082 NI_CtrSource(2),
2083 NI_CtrSource(3),
2084 NI_CtrGate(1),
2085 NI_CtrGate(2),
2086 NI_CtrGate(3),
2087 NI_CtrArmStartTrigger(1),
2088 NI_CtrArmStartTrigger(2),
2089 NI_CtrArmStartTrigger(3),
2090 NI_CtrInternalOutput(0),
2091 NI_CtrInternalOutput(1),
2092 NI_CtrInternalOutput(2),
2093 NI_CtrInternalOutput(3),
2094 NI_CtrSampleClock(1),
2095 NI_CtrSampleClock(2),
2096 NI_CtrSampleClock(3),
2097 NI_AO_SampleClock,
2098 NI_AO_StartTrigger,
2099 NI_AO_PauseTrigger,
2100 NI_DI_SampleClock,
2101 NI_DI_StartTrigger,
2102 NI_DI_ReferenceTrigger,
2103 NI_DI_PauseTrigger,
2104 NI_DO_SampleClock,
2105 NI_DO_StartTrigger,
2106 NI_DO_PauseTrigger,
2107 NI_10MHzRefClock,
2108 NI_ChangeDetectionEvent,
2109 NI_WatchdogExpiredEvent,
2110 0, /* Termination */
2111 }
2112 },
2113 {
2114 .dest = NI_CtrArmStartTrigger(1),
2115 .src = (int[]){
2116 NI_PFI(0),
2117 NI_PFI(1),
2118 NI_PFI(2),
2119 NI_PFI(3),
2120 NI_PFI(4),
2121 NI_PFI(5),
2122 NI_PFI(6),
2123 NI_PFI(7),
2124 TRIGGER_LINE(0),
2125 TRIGGER_LINE(1),
2126 TRIGGER_LINE(2),
2127 TRIGGER_LINE(3),
2128 TRIGGER_LINE(4),
2129 TRIGGER_LINE(5),
2130 TRIGGER_LINE(6),
2131 TRIGGER_LINE(7),
2132 NI_CtrSource(0),
2133 NI_CtrSource(2),
2134 NI_CtrSource(3),
2135 NI_CtrGate(0),
2136 NI_CtrGate(2),
2137 NI_CtrGate(3),
2138 NI_CtrArmStartTrigger(0),
2139 NI_CtrArmStartTrigger(2),
2140 NI_CtrArmStartTrigger(3),
2141 NI_CtrInternalOutput(0),
2142 NI_CtrInternalOutput(1),
2143 NI_CtrInternalOutput(2),
2144 NI_CtrInternalOutput(3),
2145 NI_CtrSampleClock(0),
2146 NI_CtrSampleClock(2),
2147 NI_CtrSampleClock(3),
2148 NI_AO_SampleClock,
2149 NI_AO_StartTrigger,
2150 NI_AO_PauseTrigger,
2151 NI_DI_SampleClock,
2152 NI_DI_StartTrigger,
2153 NI_DI_ReferenceTrigger,
2154 NI_DI_PauseTrigger,
2155 NI_DO_SampleClock,
2156 NI_DO_StartTrigger,
2157 NI_DO_PauseTrigger,
2158 NI_10MHzRefClock,
2159 NI_ChangeDetectionEvent,
2160 NI_WatchdogExpiredEvent,
2161 0, /* Termination */
2162 }
2163 },
2164 {
2165 .dest = NI_CtrArmStartTrigger(2),
2166 .src = (int[]){
2167 NI_PFI(0),
2168 NI_PFI(1),
2169 NI_PFI(2),
2170 NI_PFI(3),
2171 NI_PFI(4),
2172 NI_PFI(5),
2173 NI_PFI(6),
2174 NI_PFI(7),
2175 TRIGGER_LINE(0),
2176 TRIGGER_LINE(1),
2177 TRIGGER_LINE(2),
2178 TRIGGER_LINE(3),
2179 TRIGGER_LINE(4),
2180 TRIGGER_LINE(5),
2181 TRIGGER_LINE(6),
2182 TRIGGER_LINE(7),
2183 NI_CtrSource(0),
2184 NI_CtrSource(1),
2185 NI_CtrSource(3),
2186 NI_CtrGate(0),
2187 NI_CtrGate(1),
2188 NI_CtrGate(3),
2189 NI_CtrArmStartTrigger(0),
2190 NI_CtrArmStartTrigger(1),
2191 NI_CtrArmStartTrigger(3),
2192 NI_CtrInternalOutput(0),
2193 NI_CtrInternalOutput(1),
2194 NI_CtrInternalOutput(2),
2195 NI_CtrInternalOutput(3),
2196 NI_CtrSampleClock(0),
2197 NI_CtrSampleClock(1),
2198 NI_CtrSampleClock(3),
2199 NI_AO_SampleClock,
2200 NI_AO_StartTrigger,
2201 NI_AO_PauseTrigger,
2202 NI_DI_SampleClock,
2203 NI_DI_StartTrigger,
2204 NI_DI_ReferenceTrigger,
2205 NI_DI_PauseTrigger,
2206 NI_DO_SampleClock,
2207 NI_DO_StartTrigger,
2208 NI_DO_PauseTrigger,
2209 NI_10MHzRefClock,
2210 NI_ChangeDetectionEvent,
2211 NI_WatchdogExpiredEvent,
2212 0, /* Termination */
2213 }
2214 },
2215 {
2216 .dest = NI_CtrArmStartTrigger(3),
2217 .src = (int[]){
2218 NI_PFI(0),
2219 NI_PFI(1),
2220 NI_PFI(2),
2221 NI_PFI(3),
2222 NI_PFI(4),
2223 NI_PFI(5),
2224 NI_PFI(6),
2225 NI_PFI(7),
2226 TRIGGER_LINE(0),
2227 TRIGGER_LINE(1),
2228 TRIGGER_LINE(2),
2229 TRIGGER_LINE(3),
2230 TRIGGER_LINE(4),
2231 TRIGGER_LINE(5),
2232 TRIGGER_LINE(6),
2233 TRIGGER_LINE(7),
2234 NI_CtrSource(0),
2235 NI_CtrSource(1),
2236 NI_CtrSource(2),
2237 NI_CtrGate(0),
2238 NI_CtrGate(1),
2239 NI_CtrGate(2),
2240 NI_CtrArmStartTrigger(0),
2241 NI_CtrArmStartTrigger(1),
2242 NI_CtrArmStartTrigger(2),
2243 NI_CtrInternalOutput(0),
2244 NI_CtrInternalOutput(1),
2245 NI_CtrInternalOutput(2),
2246 NI_CtrInternalOutput(3),
2247 NI_CtrSampleClock(0),
2248 NI_CtrSampleClock(1),
2249 NI_CtrSampleClock(2),
2250 NI_AO_SampleClock,
2251 NI_AO_StartTrigger,
2252 NI_AO_PauseTrigger,
2253 NI_DI_SampleClock,
2254 NI_DI_StartTrigger,
2255 NI_DI_ReferenceTrigger,
2256 NI_DI_PauseTrigger,
2257 NI_DO_SampleClock,
2258 NI_DO_StartTrigger,
2259 NI_DO_PauseTrigger,
2260 NI_10MHzRefClock,
2261 NI_ChangeDetectionEvent,
2262 NI_WatchdogExpiredEvent,
2263 0, /* Termination */
2264 }
2265 },
2266 {
2267 .dest = NI_CtrSampleClock(0),
2268 .src = (int[]){
2269 NI_PFI(0),
2270 NI_PFI(1),
2271 NI_PFI(2),
2272 NI_PFI(3),
2273 NI_PFI(4),
2274 NI_PFI(5),
2275 NI_PFI(6),
2276 NI_PFI(7),
2277 TRIGGER_LINE(0),
2278 TRIGGER_LINE(1),
2279 TRIGGER_LINE(2),
2280 TRIGGER_LINE(3),
2281 TRIGGER_LINE(4),
2282 TRIGGER_LINE(5),
2283 TRIGGER_LINE(6),
2284 TRIGGER_LINE(7),
2285 NI_CtrSource(1),
2286 NI_CtrSource(2),
2287 NI_CtrSource(3),
2288 NI_CtrGate(1),
2289 NI_CtrGate(2),
2290 NI_CtrGate(3),
2291 NI_CtrArmStartTrigger(1),
2292 NI_CtrArmStartTrigger(2),
2293 NI_CtrArmStartTrigger(3),
2294 NI_CtrInternalOutput(0),
2295 NI_CtrInternalOutput(1),
2296 NI_CtrInternalOutput(2),
2297 NI_CtrInternalOutput(3),
2298 NI_CtrSampleClock(1),
2299 NI_CtrSampleClock(2),
2300 NI_CtrSampleClock(3),
2301 NI_AO_SampleClock,
2302 NI_AO_StartTrigger,
2303 NI_AO_PauseTrigger,
2304 NI_DI_SampleClock,
2305 NI_DI_StartTrigger,
2306 NI_DI_ReferenceTrigger,
2307 NI_DI_PauseTrigger,
2308 NI_DO_SampleClock,
2309 NI_DO_StartTrigger,
2310 NI_DO_PauseTrigger,
2311 NI_10MHzRefClock,
2312 NI_ChangeDetectionEvent,
2313 NI_WatchdogExpiredEvent,
2314 0, /* Termination */
2315 }
2316 },
2317 {
2318 .dest = NI_CtrSampleClock(1),
2319 .src = (int[]){
2320 NI_PFI(0),
2321 NI_PFI(1),
2322 NI_PFI(2),
2323 NI_PFI(3),
2324 NI_PFI(4),
2325 NI_PFI(5),
2326 NI_PFI(6),
2327 NI_PFI(7),
2328 TRIGGER_LINE(0),
2329 TRIGGER_LINE(1),
2330 TRIGGER_LINE(2),
2331 TRIGGER_LINE(3),
2332 TRIGGER_LINE(4),
2333 TRIGGER_LINE(5),
2334 TRIGGER_LINE(6),
2335 TRIGGER_LINE(7),
2336 NI_CtrSource(0),
2337 NI_CtrSource(2),
2338 NI_CtrSource(3),
2339 NI_CtrGate(0),
2340 NI_CtrGate(2),
2341 NI_CtrGate(3),
2342 NI_CtrArmStartTrigger(0),
2343 NI_CtrArmStartTrigger(2),
2344 NI_CtrArmStartTrigger(3),
2345 NI_CtrInternalOutput(0),
2346 NI_CtrInternalOutput(1),
2347 NI_CtrInternalOutput(2),
2348 NI_CtrInternalOutput(3),
2349 NI_CtrSampleClock(0),
2350 NI_CtrSampleClock(2),
2351 NI_CtrSampleClock(3),
2352 NI_AO_SampleClock,
2353 NI_AO_StartTrigger,
2354 NI_AO_PauseTrigger,
2355 NI_DI_SampleClock,
2356 NI_DI_StartTrigger,
2357 NI_DI_ReferenceTrigger,
2358 NI_DI_PauseTrigger,
2359 NI_DO_SampleClock,
2360 NI_DO_StartTrigger,
2361 NI_DO_PauseTrigger,
2362 NI_10MHzRefClock,
2363 NI_ChangeDetectionEvent,
2364 NI_WatchdogExpiredEvent,
2365 0, /* Termination */
2366 }
2367 },
2368 {
2369 .dest = NI_CtrSampleClock(2),
2370 .src = (int[]){
2371 NI_PFI(0),
2372 NI_PFI(1),
2373 NI_PFI(2),
2374 NI_PFI(3),
2375 NI_PFI(4),
2376 NI_PFI(5),
2377 NI_PFI(6),
2378 NI_PFI(7),
2379 TRIGGER_LINE(0),
2380 TRIGGER_LINE(1),
2381 TRIGGER_LINE(2),
2382 TRIGGER_LINE(3),
2383 TRIGGER_LINE(4),
2384 TRIGGER_LINE(5),
2385 TRIGGER_LINE(6),
2386 TRIGGER_LINE(7),
2387 NI_CtrSource(0),
2388 NI_CtrSource(1),
2389 NI_CtrSource(3),
2390 NI_CtrGate(0),
2391 NI_CtrGate(1),
2392 NI_CtrGate(3),
2393 NI_CtrArmStartTrigger(0),
2394 NI_CtrArmStartTrigger(1),
2395 NI_CtrArmStartTrigger(3),
2396 NI_CtrInternalOutput(0),
2397 NI_CtrInternalOutput(1),
2398 NI_CtrInternalOutput(2),
2399 NI_CtrInternalOutput(3),
2400 NI_CtrSampleClock(0),
2401 NI_CtrSampleClock(1),
2402 NI_CtrSampleClock(3),
2403 NI_AO_SampleClock,
2404 NI_AO_StartTrigger,
2405 NI_AO_PauseTrigger,
2406 NI_DI_SampleClock,
2407 NI_DI_StartTrigger,
2408 NI_DI_ReferenceTrigger,
2409 NI_DI_PauseTrigger,
2410 NI_DO_SampleClock,
2411 NI_DO_StartTrigger,
2412 NI_DO_PauseTrigger,
2413 NI_10MHzRefClock,
2414 NI_ChangeDetectionEvent,
2415 NI_WatchdogExpiredEvent,
2416 0, /* Termination */
2417 }
2418 },
2419 {
2420 .dest = NI_CtrSampleClock(3),
2421 .src = (int[]){
2422 NI_PFI(0),
2423 NI_PFI(1),
2424 NI_PFI(2),
2425 NI_PFI(3),
2426 NI_PFI(4),
2427 NI_PFI(5),
2428 NI_PFI(6),
2429 NI_PFI(7),
2430 TRIGGER_LINE(0),
2431 TRIGGER_LINE(1),
2432 TRIGGER_LINE(2),
2433 TRIGGER_LINE(3),
2434 TRIGGER_LINE(4),
2435 TRIGGER_LINE(5),
2436 TRIGGER_LINE(6),
2437 TRIGGER_LINE(7),
2438 NI_CtrSource(0),
2439 NI_CtrSource(1),
2440 NI_CtrSource(2),
2441 NI_CtrGate(0),
2442 NI_CtrGate(1),
2443 NI_CtrGate(2),
2444 NI_CtrArmStartTrigger(0),
2445 NI_CtrArmStartTrigger(1),
2446 NI_CtrArmStartTrigger(2),
2447 NI_CtrInternalOutput(0),
2448 NI_CtrInternalOutput(1),
2449 NI_CtrInternalOutput(2),
2450 NI_CtrInternalOutput(3),
2451 NI_CtrSampleClock(0),
2452 NI_CtrSampleClock(1),
2453 NI_CtrSampleClock(2),
2454 NI_AO_SampleClock,
2455 NI_AO_StartTrigger,
2456 NI_AO_PauseTrigger,
2457 NI_DI_SampleClock,
2458 NI_DI_StartTrigger,
2459 NI_DI_ReferenceTrigger,
2460 NI_DI_PauseTrigger,
2461 NI_DO_SampleClock,
2462 NI_DO_StartTrigger,
2463 NI_DO_PauseTrigger,
2464 NI_10MHzRefClock,
2465 NI_ChangeDetectionEvent,
2466 NI_WatchdogExpiredEvent,
2467 0, /* Termination */
2468 }
2469 },
2470 {
2471 .dest = NI_AO_SampleClock,
2472 .src = (int[]){
2473 NI_PFI(0),
2474 NI_PFI(1),
2475 NI_PFI(2),
2476 NI_PFI(3),
2477 NI_PFI(4),
2478 NI_PFI(5),
2479 NI_PFI(6),
2480 NI_PFI(7),
2481 TRIGGER_LINE(0),
2482 TRIGGER_LINE(1),
2483 TRIGGER_LINE(2),
2484 TRIGGER_LINE(3),
2485 TRIGGER_LINE(4),
2486 TRIGGER_LINE(5),
2487 TRIGGER_LINE(6),
2488 TRIGGER_LINE(7),
2489 NI_CtrSource(0),
2490 NI_CtrSource(1),
2491 NI_CtrSource(2),
2492 NI_CtrSource(3),
2493 NI_CtrGate(0),
2494 NI_CtrGate(1),
2495 NI_CtrGate(2),
2496 NI_CtrGate(3),
2497 NI_CtrArmStartTrigger(0),
2498 NI_CtrArmStartTrigger(1),
2499 NI_CtrArmStartTrigger(2),
2500 NI_CtrArmStartTrigger(3),
2501 NI_CtrInternalOutput(0),
2502 NI_CtrInternalOutput(1),
2503 NI_CtrInternalOutput(2),
2504 NI_CtrInternalOutput(3),
2505 NI_CtrSampleClock(0),
2506 NI_CtrSampleClock(1),
2507 NI_CtrSampleClock(2),
2508 NI_CtrSampleClock(3),
2509 NI_AO_SampleClockTimebase,
2510 NI_DI_SampleClock,
2511 NI_DI_ReferenceTrigger,
2512 NI_DI_PauseTrigger,
2513 NI_DO_SampleClock,
2514 NI_DO_StartTrigger,
2515 NI_DO_PauseTrigger,
2516 NI_10MHzRefClock,
2517 NI_ChangeDetectionEvent,
2518 NI_WatchdogExpiredEvent,
2519 0, /* Termination */
2520 }
2521 },
2522 {
2523 .dest = NI_AO_SampleClockTimebase,
2524 .src = (int[]){
2525 NI_PFI(0),
2526 NI_PFI(1),
2527 NI_PFI(2),
2528 NI_PFI(3),
2529 NI_PFI(4),
2530 NI_PFI(5),
2531 NI_PFI(6),
2532 NI_PFI(7),
2533 TRIGGER_LINE(0),
2534 TRIGGER_LINE(1),
2535 TRIGGER_LINE(2),
2536 TRIGGER_LINE(3),
2537 TRIGGER_LINE(4),
2538 TRIGGER_LINE(5),
2539 TRIGGER_LINE(6),
2540 TRIGGER_LINE(7),
2541 PXI_Clk10,
2542 NI_20MHzTimebase,
2543 NI_100MHzTimebase,
2544 NI_100kHzTimebase,
2545 0, /* Termination */
2546 }
2547 },
2548 {
2549 .dest = NI_AO_StartTrigger,
2550 .src = (int[]){
2551 NI_PFI(0),
2552 NI_PFI(1),
2553 NI_PFI(2),
2554 NI_PFI(3),
2555 NI_PFI(4),
2556 NI_PFI(5),
2557 NI_PFI(6),
2558 NI_PFI(7),
2559 TRIGGER_LINE(0),
2560 TRIGGER_LINE(1),
2561 TRIGGER_LINE(2),
2562 TRIGGER_LINE(3),
2563 TRIGGER_LINE(4),
2564 TRIGGER_LINE(5),
2565 TRIGGER_LINE(6),
2566 TRIGGER_LINE(7),
2567 NI_CtrSource(0),
2568 NI_CtrSource(1),
2569 NI_CtrSource(2),
2570 NI_CtrSource(3),
2571 NI_CtrGate(0),
2572 NI_CtrGate(1),
2573 NI_CtrGate(2),
2574 NI_CtrGate(3),
2575 NI_CtrArmStartTrigger(0),
2576 NI_CtrArmStartTrigger(1),
2577 NI_CtrArmStartTrigger(2),
2578 NI_CtrArmStartTrigger(3),
2579 NI_CtrInternalOutput(0),
2580 NI_CtrInternalOutput(1),
2581 NI_CtrInternalOutput(2),
2582 NI_CtrInternalOutput(3),
2583 NI_CtrSampleClock(0),
2584 NI_CtrSampleClock(1),
2585 NI_CtrSampleClock(2),
2586 NI_CtrSampleClock(3),
2587 NI_DI_SampleClock,
2588 NI_DI_StartTrigger,
2589 NI_DI_ReferenceTrigger,
2590 NI_DI_PauseTrigger,
2591 NI_DO_SampleClock,
2592 NI_DO_StartTrigger,
2593 NI_DO_PauseTrigger,
2594 NI_10MHzRefClock,
2595 NI_ChangeDetectionEvent,
2596 NI_WatchdogExpiredEvent,
2597 0, /* Termination */
2598 }
2599 },
2600 {
2601 .dest = NI_AO_PauseTrigger,
2602 .src = (int[]){
2603 NI_PFI(0),
2604 NI_PFI(1),
2605 NI_PFI(2),
2606 NI_PFI(3),
2607 NI_PFI(4),
2608 NI_PFI(5),
2609 NI_PFI(6),
2610 NI_PFI(7),
2611 TRIGGER_LINE(0),
2612 TRIGGER_LINE(1),
2613 TRIGGER_LINE(2),
2614 TRIGGER_LINE(3),
2615 TRIGGER_LINE(4),
2616 TRIGGER_LINE(5),
2617 TRIGGER_LINE(6),
2618 TRIGGER_LINE(7),
2619 NI_CtrSource(0),
2620 NI_CtrSource(1),
2621 NI_CtrSource(2),
2622 NI_CtrSource(3),
2623 NI_CtrGate(0),
2624 NI_CtrGate(1),
2625 NI_CtrGate(2),
2626 NI_CtrGate(3),
2627 NI_CtrArmStartTrigger(0),
2628 NI_CtrArmStartTrigger(1),
2629 NI_CtrArmStartTrigger(2),
2630 NI_CtrArmStartTrigger(3),
2631 NI_CtrInternalOutput(0),
2632 NI_CtrInternalOutput(1),
2633 NI_CtrInternalOutput(2),
2634 NI_CtrInternalOutput(3),
2635 NI_CtrSampleClock(0),
2636 NI_CtrSampleClock(1),
2637 NI_CtrSampleClock(2),
2638 NI_CtrSampleClock(3),
2639 NI_DI_SampleClock,
2640 NI_DI_StartTrigger,
2641 NI_DI_ReferenceTrigger,
2642 NI_DI_PauseTrigger,
2643 NI_DO_SampleClock,
2644 NI_DO_StartTrigger,
2645 NI_DO_PauseTrigger,
2646 NI_10MHzRefClock,
2647 NI_ChangeDetectionEvent,
2648 NI_WatchdogExpiredEvent,
2649 0, /* Termination */
2650 }
2651 },
2652 {
2653 .dest = NI_DI_SampleClock,
2654 .src = (int[]){
2655 NI_PFI(0),
2656 NI_PFI(1),
2657 NI_PFI(2),
2658 NI_PFI(3),
2659 NI_PFI(4),
2660 NI_PFI(5),
2661 NI_PFI(6),
2662 NI_PFI(7),
2663 TRIGGER_LINE(0),
2664 TRIGGER_LINE(1),
2665 TRIGGER_LINE(2),
2666 TRIGGER_LINE(3),
2667 TRIGGER_LINE(4),
2668 TRIGGER_LINE(5),
2669 TRIGGER_LINE(6),
2670 TRIGGER_LINE(7),
2671 NI_CtrSource(0),
2672 NI_CtrSource(1),
2673 NI_CtrSource(2),
2674 NI_CtrSource(3),
2675 NI_CtrGate(0),
2676 NI_CtrGate(1),
2677 NI_CtrGate(2),
2678 NI_CtrGate(3),
2679 NI_CtrArmStartTrigger(0),
2680 NI_CtrArmStartTrigger(1),
2681 NI_CtrArmStartTrigger(2),
2682 NI_CtrArmStartTrigger(3),
2683 NI_CtrInternalOutput(0),
2684 NI_CtrInternalOutput(1),
2685 NI_CtrInternalOutput(2),
2686 NI_CtrInternalOutput(3),
2687 NI_CtrSampleClock(0),
2688 NI_CtrSampleClock(1),
2689 NI_CtrSampleClock(2),
2690 NI_CtrSampleClock(3),
2691 NI_AO_SampleClock,
2692 NI_AO_StartTrigger,
2693 NI_AO_PauseTrigger,
2694 NI_DO_SampleClock,
2695 NI_DO_StartTrigger,
2696 NI_DO_PauseTrigger,
2697 NI_10MHzRefClock,
2698 NI_ChangeDetectionEvent,
2699 NI_WatchdogExpiredEvent,
2700 0, /* Termination */
2701 }
2702 },
2703 {
2704 .dest = NI_DI_SampleClockTimebase,
2705 .src = (int[]){
2706 NI_PFI(0),
2707 NI_PFI(1),
2708 NI_PFI(2),
2709 NI_PFI(3),
2710 NI_PFI(4),
2711 NI_PFI(5),
2712 NI_PFI(6),
2713 NI_PFI(7),
2714 TRIGGER_LINE(0),
2715 TRIGGER_LINE(1),
2716 TRIGGER_LINE(2),
2717 TRIGGER_LINE(3),
2718 TRIGGER_LINE(4),
2719 TRIGGER_LINE(5),
2720 TRIGGER_LINE(6),
2721 TRIGGER_LINE(7),
2722 PXI_Clk10,
2723 NI_DI_SampleClockTimebase,
2724 NI_20MHzTimebase,
2725 NI_100MHzTimebase,
2726 NI_100kHzTimebase,
2727 0, /* Termination */
2728 }
2729 },
2730 {
2731 .dest = NI_DI_StartTrigger,
2732 .src = (int[]){
2733 NI_PFI(0),
2734 NI_PFI(1),
2735 NI_PFI(2),
2736 NI_PFI(3),
2737 NI_PFI(4),
2738 NI_PFI(5),
2739 NI_PFI(6),
2740 NI_PFI(7),
2741 TRIGGER_LINE(0),
2742 TRIGGER_LINE(1),
2743 TRIGGER_LINE(2),
2744 TRIGGER_LINE(3),
2745 TRIGGER_LINE(4),
2746 TRIGGER_LINE(5),
2747 TRIGGER_LINE(6),
2748 TRIGGER_LINE(7),
2749 NI_CtrSource(0),
2750 NI_CtrSource(1),
2751 NI_CtrSource(2),
2752 NI_CtrSource(3),
2753 NI_CtrGate(0),
2754 NI_CtrGate(1),
2755 NI_CtrGate(2),
2756 NI_CtrGate(3),
2757 NI_CtrArmStartTrigger(0),
2758 NI_CtrArmStartTrigger(1),
2759 NI_CtrArmStartTrigger(2),
2760 NI_CtrArmStartTrigger(3),
2761 NI_CtrInternalOutput(0),
2762 NI_CtrInternalOutput(1),
2763 NI_CtrInternalOutput(2),
2764 NI_CtrInternalOutput(3),
2765 NI_CtrSampleClock(0),
2766 NI_CtrSampleClock(1),
2767 NI_CtrSampleClock(2),
2768 NI_CtrSampleClock(3),
2769 NI_AO_SampleClock,
2770 NI_AO_StartTrigger,
2771 NI_AO_PauseTrigger,
2772 NI_DO_SampleClock,
2773 NI_DO_StartTrigger,
2774 NI_DO_PauseTrigger,
2775 NI_10MHzRefClock,
2776 NI_ChangeDetectionEvent,
2777 NI_WatchdogExpiredEvent,
2778 0, /* Termination */
2779 }
2780 },
2781 {
2782 .dest = NI_DI_ReferenceTrigger,
2783 .src = (int[]){
2784 NI_PFI(0),
2785 NI_PFI(1),
2786 NI_PFI(2),
2787 NI_PFI(3),
2788 NI_PFI(4),
2789 NI_PFI(5),
2790 NI_PFI(6),
2791 NI_PFI(7),
2792 TRIGGER_LINE(0),
2793 TRIGGER_LINE(1),
2794 TRIGGER_LINE(2),
2795 TRIGGER_LINE(3),
2796 TRIGGER_LINE(4),
2797 TRIGGER_LINE(5),
2798 TRIGGER_LINE(6),
2799 TRIGGER_LINE(7),
2800 NI_CtrSource(0),
2801 NI_CtrSource(1),
2802 NI_CtrSource(2),
2803 NI_CtrSource(3),
2804 NI_CtrGate(0),
2805 NI_CtrGate(1),
2806 NI_CtrGate(2),
2807 NI_CtrGate(3),
2808 NI_CtrArmStartTrigger(0),
2809 NI_CtrArmStartTrigger(1),
2810 NI_CtrArmStartTrigger(2),
2811 NI_CtrArmStartTrigger(3),
2812 NI_CtrInternalOutput(0),
2813 NI_CtrInternalOutput(1),
2814 NI_CtrInternalOutput(2),
2815 NI_CtrInternalOutput(3),
2816 NI_CtrSampleClock(0),
2817 NI_CtrSampleClock(1),
2818 NI_CtrSampleClock(2),
2819 NI_CtrSampleClock(3),
2820 NI_AO_SampleClock,
2821 NI_AO_StartTrigger,
2822 NI_AO_PauseTrigger,
2823 NI_DO_SampleClock,
2824 NI_DO_StartTrigger,
2825 NI_DO_PauseTrigger,
2826 NI_10MHzRefClock,
2827 NI_ChangeDetectionEvent,
2828 NI_WatchdogExpiredEvent,
2829 0, /* Termination */
2830 }
2831 },
2832 {
2833 .dest = NI_DI_PauseTrigger,
2834 .src = (int[]){
2835 NI_PFI(0),
2836 NI_PFI(1),
2837 NI_PFI(2),
2838 NI_PFI(3),
2839 NI_PFI(4),
2840 NI_PFI(5),
2841 NI_PFI(6),
2842 NI_PFI(7),
2843 TRIGGER_LINE(0),
2844 TRIGGER_LINE(1),
2845 TRIGGER_LINE(2),
2846 TRIGGER_LINE(3),
2847 TRIGGER_LINE(4),
2848 TRIGGER_LINE(5),
2849 TRIGGER_LINE(6),
2850 TRIGGER_LINE(7),
2851 NI_CtrSource(0),
2852 NI_CtrSource(1),
2853 NI_CtrSource(2),
2854 NI_CtrSource(3),
2855 NI_CtrGate(0),
2856 NI_CtrGate(1),
2857 NI_CtrGate(2),
2858 NI_CtrGate(3),
2859 NI_CtrArmStartTrigger(0),
2860 NI_CtrArmStartTrigger(1),
2861 NI_CtrArmStartTrigger(2),
2862 NI_CtrArmStartTrigger(3),
2863 NI_CtrInternalOutput(0),
2864 NI_CtrInternalOutput(1),
2865 NI_CtrInternalOutput(2),
2866 NI_CtrInternalOutput(3),
2867 NI_CtrSampleClock(0),
2868 NI_CtrSampleClock(1),
2869 NI_CtrSampleClock(2),
2870 NI_CtrSampleClock(3),
2871 NI_AO_SampleClock,
2872 NI_AO_StartTrigger,
2873 NI_AO_PauseTrigger,
2874 NI_DO_SampleClock,
2875 NI_DO_StartTrigger,
2876 NI_DO_PauseTrigger,
2877 NI_10MHzRefClock,
2878 NI_ChangeDetectionEvent,
2879 NI_WatchdogExpiredEvent,
2880 0, /* Termination */
2881 }
2882 },
2883 {
2884 .dest = NI_DO_SampleClock,
2885 .src = (int[]){
2886 NI_PFI(0),
2887 NI_PFI(1),
2888 NI_PFI(2),
2889 NI_PFI(3),
2890 NI_PFI(4),
2891 NI_PFI(5),
2892 NI_PFI(6),
2893 NI_PFI(7),
2894 TRIGGER_LINE(0),
2895 TRIGGER_LINE(1),
2896 TRIGGER_LINE(2),
2897 TRIGGER_LINE(3),
2898 TRIGGER_LINE(4),
2899 TRIGGER_LINE(5),
2900 TRIGGER_LINE(6),
2901 TRIGGER_LINE(7),
2902 NI_CtrSource(0),
2903 NI_CtrSource(1),
2904 NI_CtrSource(2),
2905 NI_CtrSource(3),
2906 NI_CtrGate(0),
2907 NI_CtrGate(1),
2908 NI_CtrGate(2),
2909 NI_CtrGate(3),
2910 NI_CtrArmStartTrigger(0),
2911 NI_CtrArmStartTrigger(1),
2912 NI_CtrArmStartTrigger(2),
2913 NI_CtrArmStartTrigger(3),
2914 NI_CtrInternalOutput(0),
2915 NI_CtrInternalOutput(1),
2916 NI_CtrInternalOutput(2),
2917 NI_CtrInternalOutput(3),
2918 NI_CtrSampleClock(0),
2919 NI_CtrSampleClock(1),
2920 NI_CtrSampleClock(2),
2921 NI_CtrSampleClock(3),
2922 NI_AO_SampleClock,
2923 NI_AO_StartTrigger,
2924 NI_AO_PauseTrigger,
2925 NI_DI_SampleClock,
2926 NI_DI_ReferenceTrigger,
2927 NI_DI_PauseTrigger,
2928 NI_DO_SampleClockTimebase,
2929 NI_10MHzRefClock,
2930 NI_ChangeDetectionEvent,
2931 NI_WatchdogExpiredEvent,
2932 0, /* Termination */
2933 }
2934 },
2935 {
2936 .dest = NI_DO_SampleClockTimebase,
2937 .src = (int[]){
2938 NI_PFI(0),
2939 NI_PFI(1),
2940 NI_PFI(2),
2941 NI_PFI(3),
2942 NI_PFI(4),
2943 NI_PFI(5),
2944 NI_PFI(6),
2945 NI_PFI(7),
2946 TRIGGER_LINE(0),
2947 TRIGGER_LINE(1),
2948 TRIGGER_LINE(2),
2949 TRIGGER_LINE(3),
2950 TRIGGER_LINE(4),
2951 TRIGGER_LINE(5),
2952 TRIGGER_LINE(6),
2953 TRIGGER_LINE(7),
2954 PXI_Clk10,
2955 NI_20MHzTimebase,
2956 NI_100MHzTimebase,
2957 NI_100kHzTimebase,
2958 0, /* Termination */
2959 }
2960 },
2961 {
2962 .dest = NI_DO_StartTrigger,
2963 .src = (int[]){
2964 NI_PFI(0),
2965 NI_PFI(1),
2966 NI_PFI(2),
2967 NI_PFI(3),
2968 NI_PFI(4),
2969 NI_PFI(5),
2970 NI_PFI(6),
2971 NI_PFI(7),
2972 TRIGGER_LINE(0),
2973 TRIGGER_LINE(1),
2974 TRIGGER_LINE(2),
2975 TRIGGER_LINE(3),
2976 TRIGGER_LINE(4),
2977 TRIGGER_LINE(5),
2978 TRIGGER_LINE(6),
2979 TRIGGER_LINE(7),
2980 NI_CtrSource(0),
2981 NI_CtrSource(1),
2982 NI_CtrSource(2),
2983 NI_CtrSource(3),
2984 NI_CtrGate(0),
2985 NI_CtrGate(1),
2986 NI_CtrGate(2),
2987 NI_CtrGate(3),
2988 NI_CtrArmStartTrigger(0),
2989 NI_CtrArmStartTrigger(1),
2990 NI_CtrArmStartTrigger(2),
2991 NI_CtrArmStartTrigger(3),
2992 NI_CtrInternalOutput(0),
2993 NI_CtrInternalOutput(1),
2994 NI_CtrInternalOutput(2),
2995 NI_CtrInternalOutput(3),
2996 NI_CtrSampleClock(0),
2997 NI_CtrSampleClock(1),
2998 NI_CtrSampleClock(2),
2999 NI_CtrSampleClock(3),
3000 NI_AO_SampleClock,
3001 NI_AO_StartTrigger,
3002 NI_AO_PauseTrigger,
3003 NI_DI_SampleClock,
3004 NI_DI_StartTrigger,
3005 NI_DI_ReferenceTrigger,
3006 NI_DI_PauseTrigger,
3007 NI_10MHzRefClock,
3008 NI_ChangeDetectionEvent,
3009 NI_WatchdogExpiredEvent,
3010 0, /* Termination */
3011 }
3012 },
3013 {
3014 .dest = NI_DO_PauseTrigger,
3015 .src = (int[]){
3016 NI_PFI(0),
3017 NI_PFI(1),
3018 NI_PFI(2),
3019 NI_PFI(3),
3020 NI_PFI(4),
3021 NI_PFI(5),
3022 NI_PFI(6),
3023 NI_PFI(7),
3024 TRIGGER_LINE(0),
3025 TRIGGER_LINE(1),
3026 TRIGGER_LINE(2),
3027 TRIGGER_LINE(3),
3028 TRIGGER_LINE(4),
3029 TRIGGER_LINE(5),
3030 TRIGGER_LINE(6),
3031 TRIGGER_LINE(7),
3032 NI_CtrSource(0),
3033 NI_CtrSource(1),
3034 NI_CtrSource(2),
3035 NI_CtrSource(3),
3036 NI_CtrGate(0),
3037 NI_CtrGate(1),
3038 NI_CtrGate(2),
3039 NI_CtrGate(3),
3040 NI_CtrArmStartTrigger(0),
3041 NI_CtrArmStartTrigger(1),
3042 NI_CtrArmStartTrigger(2),
3043 NI_CtrArmStartTrigger(3),
3044 NI_CtrInternalOutput(0),
3045 NI_CtrInternalOutput(1),
3046 NI_CtrInternalOutput(2),
3047 NI_CtrInternalOutput(3),
3048 NI_CtrSampleClock(0),
3049 NI_CtrSampleClock(1),
3050 NI_CtrSampleClock(2),
3051 NI_CtrSampleClock(3),
3052 NI_AO_SampleClock,
3053 NI_AO_StartTrigger,
3054 NI_AO_PauseTrigger,
3055 NI_DI_SampleClock,
3056 NI_DI_StartTrigger,
3057 NI_DI_ReferenceTrigger,
3058 NI_DI_PauseTrigger,
3059 NI_10MHzRefClock,
3060 NI_ChangeDetectionEvent,
3061 NI_WatchdogExpiredEvent,
3062 0, /* Termination */
3063 }
3064 },
3065 {
3066 .dest = NI_WatchdogExpirationTrigger,
3067 .src = (int[]){
3068 TRIGGER_LINE(0),
3069 TRIGGER_LINE(1),
3070 TRIGGER_LINE(2),
3071 TRIGGER_LINE(3),
3072 TRIGGER_LINE(4),
3073 TRIGGER_LINE(5),
3074 TRIGGER_LINE(6),
3075 TRIGGER_LINE(7),
3076 0, /* Termination */
3077 }
3078 },
3079 { /* Termination of list */
3080 .dest = 0,
3081 },
3082 },
3083 };