1 // SPDX-License-Identifier: GPL-2.0+
2 /* vim: set ts=8 sw=8 noet tw=80 nowrap: */
3 /*
4 * comedi/drivers/ni_routing/ni_device_routes/pci-6723.c
5 * List of valid routes for specific NI boards.
6 *
7 * COMEDI - Linux Control and Measurement Device Interface
8 * Copyright (C) 2016 Spencer E. Olson <olsonse@umich.edu>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 /*
22 * The contents of this file are generated using the tools in
23 * comedi/drivers/ni_routing/tools
24 *
25 * Please use those tools to help maintain the contents of this file.
26 */
27
28 #include "../ni_device_routes.h"
29 #include "all.h"
30
31 struct ni_device_routes ni_pci_6723_device_routes = {
32 .device = "pci-6723",
33 .routes = (struct ni_route_set[]){
34 {
35 .dest = NI_PFI(3),
36 .src = (int[]){
37 NI_CtrSource(1),
38 0, /* Termination */
39 }
40 },
41 {
42 .dest = NI_PFI(4),
43 .src = (int[]){
44 NI_CtrGate(1),
45 0, /* Termination */
46 }
47 },
48 {
49 .dest = NI_PFI(5),
50 .src = (int[]){
51 NI_AO_SampleClock,
52 0, /* Termination */
53 }
54 },
55 {
56 .dest = NI_PFI(6),
57 .src = (int[]){
58 NI_AO_StartTrigger,
59 0, /* Termination */
60 }
61 },
62 {
63 .dest = NI_PFI(8),
64 .src = (int[]){
65 NI_CtrSource(0),
66 0, /* Termination */
67 }
68 },
69 {
70 .dest = NI_PFI(9),
71 .src = (int[]){
72 NI_CtrGate(0),
73 0, /* Termination */
74 }
75 },
76 {
77 .dest = TRIGGER_LINE(0),
78 .src = (int[]){
79 NI_CtrSource(0),
80 NI_CtrGate(0),
81 NI_CtrInternalOutput(0),
82 NI_CtrOut(0),
83 NI_AO_SampleClock,
84 NI_AO_StartTrigger,
85 0, /* Termination */
86 }
87 },
88 {
89 .dest = TRIGGER_LINE(1),
90 .src = (int[]){
91 NI_CtrSource(0),
92 NI_CtrGate(0),
93 NI_CtrInternalOutput(0),
94 NI_CtrOut(0),
95 NI_AO_SampleClock,
96 NI_AO_StartTrigger,
97 0, /* Termination */
98 }
99 },
100 {
101 .dest = TRIGGER_LINE(2),
102 .src = (int[]){
103 NI_CtrSource(0),
104 NI_CtrGate(0),
105 NI_CtrInternalOutput(0),
106 NI_CtrOut(0),
107 NI_AO_SampleClock,
108 NI_AO_StartTrigger,
109 0, /* Termination */
110 }
111 },
112 {
113 .dest = TRIGGER_LINE(3),
114 .src = (int[]){
115 NI_CtrSource(0),
116 NI_CtrGate(0),
117 NI_CtrInternalOutput(0),
118 NI_CtrOut(0),
119 NI_AO_SampleClock,
120 NI_AO_StartTrigger,
121 0, /* Termination */
122 }
123 },
124 {
125 .dest = TRIGGER_LINE(4),
126 .src = (int[]){
127 NI_CtrSource(0),
128 NI_CtrGate(0),
129 NI_CtrInternalOutput(0),
130 NI_CtrOut(0),
131 NI_AO_SampleClock,
132 NI_AO_StartTrigger,
133 0, /* Termination */
134 }
135 },
136 {
137 .dest = TRIGGER_LINE(5),
138 .src = (int[]){
139 NI_CtrSource(0),
140 NI_CtrGate(0),
141 NI_CtrInternalOutput(0),
142 NI_CtrOut(0),
143 NI_AO_SampleClock,
144 NI_AO_StartTrigger,
145 0, /* Termination */
146 }
147 },
148 {
149 .dest = TRIGGER_LINE(6),
150 .src = (int[]){
151 NI_CtrSource(0),
152 NI_CtrGate(0),
153 NI_CtrInternalOutput(0),
154 NI_CtrOut(0),
155 NI_AO_SampleClock,
156 NI_AO_StartTrigger,
157 0, /* Termination */
158 }
159 },
160 {
161 .dest = TRIGGER_LINE(7),
162 .src = (int[]){
163 NI_20MHzTimebase,
164 0, /* Termination */
165 }
166 },
167 {
168 .dest = NI_CtrSource(0),
169 .src = (int[]){
170 NI_PFI(0),
171 NI_PFI(1),
172 NI_PFI(2),
173 NI_PFI(3),
174 NI_PFI(4),
175 NI_PFI(5),
176 NI_PFI(6),
177 NI_PFI(7),
178 NI_PFI(8),
179 NI_PFI(9),
180 TRIGGER_LINE(0),
181 TRIGGER_LINE(1),
182 TRIGGER_LINE(2),
183 TRIGGER_LINE(3),
184 TRIGGER_LINE(4),
185 TRIGGER_LINE(5),
186 TRIGGER_LINE(6),
187 TRIGGER_LINE(7),
188 NI_MasterTimebase,
189 NI_20MHzTimebase,
190 NI_100kHzTimebase,
191 0, /* Termination */
192 }
193 },
194 {
195 .dest = NI_CtrSource(1),
196 .src = (int[]){
197 NI_PFI(0),
198 NI_PFI(1),
199 NI_PFI(2),
200 NI_PFI(3),
201 NI_PFI(4),
202 NI_PFI(5),
203 NI_PFI(6),
204 NI_PFI(7),
205 NI_PFI(8),
206 NI_PFI(9),
207 TRIGGER_LINE(0),
208 TRIGGER_LINE(1),
209 TRIGGER_LINE(2),
210 TRIGGER_LINE(3),
211 TRIGGER_LINE(4),
212 TRIGGER_LINE(5),
213 TRIGGER_LINE(6),
214 TRIGGER_LINE(7),
215 NI_MasterTimebase,
216 NI_20MHzTimebase,
217 NI_100kHzTimebase,
218 0, /* Termination */
219 }
220 },
221 {
222 .dest = NI_CtrGate(0),
223 .src = (int[]){
224 NI_PFI(0),
225 NI_PFI(1),
226 NI_PFI(2),
227 NI_PFI(3),
228 NI_PFI(4),
229 NI_PFI(5),
230 NI_PFI(6),
231 NI_PFI(7),
232 NI_PFI(8),
233 NI_PFI(9),
234 TRIGGER_LINE(0),
235 TRIGGER_LINE(1),
236 TRIGGER_LINE(2),
237 TRIGGER_LINE(3),
238 TRIGGER_LINE(4),
239 TRIGGER_LINE(5),
240 TRIGGER_LINE(6),
241 NI_CtrInternalOutput(1),
242 0, /* Termination */
243 }
244 },
245 {
246 .dest = NI_CtrGate(1),
247 .src = (int[]){
248 NI_PFI(0),
249 NI_PFI(1),
250 NI_PFI(2),
251 NI_PFI(3),
252 NI_PFI(4),
253 NI_PFI(5),
254 NI_PFI(6),
255 NI_PFI(7),
256 NI_PFI(8),
257 NI_PFI(9),
258 TRIGGER_LINE(0),
259 TRIGGER_LINE(1),
260 TRIGGER_LINE(2),
261 TRIGGER_LINE(3),
262 TRIGGER_LINE(4),
263 TRIGGER_LINE(5),
264 TRIGGER_LINE(6),
265 NI_CtrInternalOutput(0),
266 0, /* Termination */
267 }
268 },
269 {
270 .dest = NI_CtrOut(0),
271 .src = (int[]){
272 TRIGGER_LINE(0),
273 TRIGGER_LINE(1),
274 TRIGGER_LINE(2),
275 TRIGGER_LINE(3),
276 TRIGGER_LINE(4),
277 TRIGGER_LINE(5),
278 TRIGGER_LINE(6),
279 NI_CtrInternalOutput(0),
280 0, /* Termination */
281 }
282 },
283 {
284 .dest = NI_CtrOut(1),
285 .src = (int[]){
286 NI_CtrInternalOutput(1),
287 0, /* Termination */
288 }
289 },
290 {
291 .dest = NI_AO_SampleClock,
292 .src = (int[]){
293 NI_PFI(0),
294 NI_PFI(1),
295 NI_PFI(2),
296 NI_PFI(3),
297 NI_PFI(4),
298 NI_PFI(5),
299 NI_PFI(6),
300 NI_PFI(7),
301 NI_PFI(8),
302 NI_PFI(9),
303 TRIGGER_LINE(0),
304 TRIGGER_LINE(1),
305 TRIGGER_LINE(2),
306 TRIGGER_LINE(3),
307 TRIGGER_LINE(4),
308 TRIGGER_LINE(5),
309 TRIGGER_LINE(6),
310 NI_CtrInternalOutput(1),
311 NI_AO_SampleClockTimebase,
312 0, /* Termination */
313 }
314 },
315 {
316 .dest = NI_AO_SampleClockTimebase,
317 .src = (int[]){
318 NI_PFI(0),
319 NI_PFI(1),
320 NI_PFI(2),
321 NI_PFI(3),
322 NI_PFI(4),
323 NI_PFI(5),
324 NI_PFI(6),
325 NI_PFI(7),
326 NI_PFI(8),
327 NI_PFI(9),
328 TRIGGER_LINE(0),
329 TRIGGER_LINE(1),
330 TRIGGER_LINE(2),
331 TRIGGER_LINE(3),
332 TRIGGER_LINE(4),
333 TRIGGER_LINE(5),
334 TRIGGER_LINE(6),
335 TRIGGER_LINE(7),
336 NI_MasterTimebase,
337 NI_20MHzTimebase,
338 NI_100kHzTimebase,
339 0, /* Termination */
340 }
341 },
342 {
343 .dest = NI_AO_StartTrigger,
344 .src = (int[]){
345 NI_PFI(0),
346 NI_PFI(1),
347 NI_PFI(2),
348 NI_PFI(3),
349 NI_PFI(4),
350 NI_PFI(5),
351 NI_PFI(6),
352 NI_PFI(7),
353 NI_PFI(8),
354 NI_PFI(9),
355 TRIGGER_LINE(0),
356 TRIGGER_LINE(1),
357 TRIGGER_LINE(2),
358 TRIGGER_LINE(3),
359 TRIGGER_LINE(4),
360 TRIGGER_LINE(5),
361 TRIGGER_LINE(6),
362 0, /* Termination */
363 }
364 },
365 {
366 .dest = NI_AO_PauseTrigger,
367 .src = (int[]){
368 NI_PFI(0),
369 NI_PFI(1),
370 NI_PFI(2),
371 NI_PFI(3),
372 NI_PFI(4),
373 NI_PFI(5),
374 NI_PFI(6),
375 NI_PFI(7),
376 NI_PFI(8),
377 NI_PFI(9),
378 TRIGGER_LINE(0),
379 TRIGGER_LINE(1),
380 TRIGGER_LINE(2),
381 TRIGGER_LINE(3),
382 TRIGGER_LINE(4),
383 TRIGGER_LINE(5),
384 TRIGGER_LINE(6),
385 0, /* Termination */
386 }
387 },
388 {
389 .dest = NI_MasterTimebase,
390 .src = (int[]){
391 TRIGGER_LINE(7),
392 NI_20MHzTimebase,
393 0, /* Termination */
394 }
395 },
396 { /* Termination of list */
397 .dest = 0,
398 },
399 },
400 };