This source file includes following definitions.
- pcimio_ai_change
- pcimio_ao_change
- pcimio_gpct0_change
- pcimio_gpct1_change
- pcimio_dio_change
- m_series_init_eeprom_buffer
- init_6143
- pcimio_detach
- pcimio_auto_attach
- ni_pcimio_pci_probe
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95 #include <linux/module.h>
96 #include <linux/delay.h>
97
98 #include "../comedi_pci.h"
99
100 #include <asm/byteorder.h>
101
102 #include "ni_stc.h"
103 #include "mite.h"
104
105 #define PCIDMA
106
107
108
109
110
111
112
113
114
115 static const struct comedi_lrange range_ni_M_628x_ao = {
116 8, {
117 BIP_RANGE(10),
118 BIP_RANGE(5),
119 BIP_RANGE(2),
120 BIP_RANGE(1),
121 RANGE(-5, 15),
122 UNI_RANGE(10),
123 RANGE(3, 7),
124 RANGE(4, 6),
125 RANGE_ext(-1, 1)
126 }
127 };
128
129 static const struct comedi_lrange range_ni_M_625x_ao = {
130 3, {
131 BIP_RANGE(10),
132 BIP_RANGE(5),
133 RANGE_ext(-1, 1)
134 }
135 };
136
137 enum ni_pcimio_boardid {
138 BOARD_PCIMIO_16XE_50,
139 BOARD_PCIMIO_16XE_10,
140 BOARD_PCI6014,
141 BOARD_PXI6030E,
142 BOARD_PCIMIO_16E_1,
143 BOARD_PCIMIO_16E_4,
144 BOARD_PXI6040E,
145 BOARD_PCI6031E,
146 BOARD_PCI6032E,
147 BOARD_PCI6033E,
148 BOARD_PCI6071E,
149 BOARD_PCI6023E,
150 BOARD_PCI6024E,
151 BOARD_PCI6025E,
152 BOARD_PXI6025E,
153 BOARD_PCI6034E,
154 BOARD_PCI6035E,
155 BOARD_PCI6052E,
156 BOARD_PCI6110,
157 BOARD_PCI6111,
158
159
160 BOARD_PCI6711,
161 BOARD_PXI6711,
162 BOARD_PCI6713,
163 BOARD_PXI6713,
164 BOARD_PCI6731,
165
166 BOARD_PCI6733,
167 BOARD_PXI6733,
168 BOARD_PXI6071E,
169 BOARD_PXI6070E,
170 BOARD_PXI6052E,
171 BOARD_PXI6031E,
172 BOARD_PCI6036E,
173 BOARD_PCI6220,
174 BOARD_PXI6220,
175 BOARD_PCI6221,
176 BOARD_PCI6221_37PIN,
177 BOARD_PXI6221,
178 BOARD_PCI6224,
179 BOARD_PXI6224,
180 BOARD_PCI6225,
181 BOARD_PXI6225,
182 BOARD_PCI6229,
183 BOARD_PXI6229,
184 BOARD_PCI6250,
185 BOARD_PXI6250,
186 BOARD_PCI6251,
187 BOARD_PXI6251,
188 BOARD_PCIE6251,
189 BOARD_PXIE6251,
190 BOARD_PCI6254,
191 BOARD_PXI6254,
192 BOARD_PCI6259,
193 BOARD_PXI6259,
194 BOARD_PCIE6259,
195 BOARD_PXIE6259,
196 BOARD_PCI6280,
197 BOARD_PXI6280,
198 BOARD_PCI6281,
199 BOARD_PXI6281,
200 BOARD_PCI6284,
201 BOARD_PXI6284,
202 BOARD_PCI6289,
203 BOARD_PXI6289,
204 BOARD_PCI6143,
205 BOARD_PXI6143,
206 };
207
208 static const struct ni_board_struct ni_boards[] = {
209 [BOARD_PCIMIO_16XE_50] = {
210 .name = "pci-mio-16xe-50",
211 .n_adchan = 16,
212 .ai_maxdata = 0xffff,
213 .ai_fifo_depth = 2048,
214 .alwaysdither = 1,
215 .gainlkup = ai_gain_8,
216 .ai_speed = 50000,
217 .n_aochan = 2,
218 .ao_maxdata = 0x0fff,
219 .ao_range_table = &range_bipolar10,
220 .ao_speed = 50000,
221 .caldac = { dac8800, dac8043 },
222 },
223 [BOARD_PCIMIO_16XE_10] = {
224 .name = "pci-mio-16xe-10",
225 .n_adchan = 16,
226 .ai_maxdata = 0xffff,
227 .ai_fifo_depth = 512,
228 .alwaysdither = 1,
229 .gainlkup = ai_gain_14,
230 .ai_speed = 10000,
231 .n_aochan = 2,
232 .ao_maxdata = 0xffff,
233 .ao_fifo_depth = 2048,
234 .ao_range_table = &range_ni_E_ao_ext,
235 .ao_speed = 10000,
236 .caldac = { dac8800, dac8043, ad8522 },
237 },
238 [BOARD_PCI6014] = {
239 .name = "pci-6014",
240 .n_adchan = 16,
241 .ai_maxdata = 0xffff,
242 .ai_fifo_depth = 512,
243 .alwaysdither = 1,
244 .gainlkup = ai_gain_4,
245 .ai_speed = 5000,
246 .n_aochan = 2,
247 .ao_maxdata = 0xffff,
248 .ao_range_table = &range_bipolar10,
249 .ao_speed = 100000,
250 .caldac = { ad8804_debug },
251 },
252 [BOARD_PXI6030E] = {
253 .name = "pxi-6030e",
254 .n_adchan = 16,
255 .ai_maxdata = 0xffff,
256 .ai_fifo_depth = 512,
257 .alwaysdither = 1,
258 .gainlkup = ai_gain_14,
259 .ai_speed = 10000,
260 .n_aochan = 2,
261 .ao_maxdata = 0xffff,
262 .ao_fifo_depth = 2048,
263 .ao_range_table = &range_ni_E_ao_ext,
264 .ao_speed = 10000,
265 .caldac = { dac8800, dac8043, ad8522 },
266 },
267 [BOARD_PCIMIO_16E_1] = {
268 .name = "pci-mio-16e-1",
269 .n_adchan = 16,
270 .ai_maxdata = 0x0fff,
271 .ai_fifo_depth = 512,
272 .gainlkup = ai_gain_16,
273 .ai_speed = 800,
274 .n_aochan = 2,
275 .ao_maxdata = 0x0fff,
276 .ao_fifo_depth = 2048,
277 .ao_range_table = &range_ni_E_ao_ext,
278 .ao_speed = 1000,
279 .caldac = { mb88341 },
280 },
281 [BOARD_PCIMIO_16E_4] = {
282 .name = "pci-mio-16e-4",
283 .n_adchan = 16,
284 .ai_maxdata = 0x0fff,
285 .ai_fifo_depth = 512,
286 .gainlkup = ai_gain_16,
287
288
289
290
291 .ai_speed = 2000,
292 .n_aochan = 2,
293 .ao_maxdata = 0x0fff,
294 .ao_fifo_depth = 512,
295 .ao_range_table = &range_ni_E_ao_ext,
296 .ao_speed = 1000,
297 .caldac = { ad8804_debug },
298 },
299 [BOARD_PXI6040E] = {
300 .name = "pxi-6040e",
301 .n_adchan = 16,
302 .ai_maxdata = 0x0fff,
303 .ai_fifo_depth = 512,
304 .gainlkup = ai_gain_16,
305 .ai_speed = 2000,
306 .n_aochan = 2,
307 .ao_maxdata = 0x0fff,
308 .ao_fifo_depth = 512,
309 .ao_range_table = &range_ni_E_ao_ext,
310 .ao_speed = 1000,
311 .caldac = { mb88341 },
312 },
313 [BOARD_PCI6031E] = {
314 .name = "pci-6031e",
315 .n_adchan = 64,
316 .ai_maxdata = 0xffff,
317 .ai_fifo_depth = 512,
318 .alwaysdither = 1,
319 .gainlkup = ai_gain_14,
320 .ai_speed = 10000,
321 .n_aochan = 2,
322 .ao_maxdata = 0xffff,
323 .ao_fifo_depth = 2048,
324 .ao_range_table = &range_ni_E_ao_ext,
325 .ao_speed = 10000,
326 .caldac = { dac8800, dac8043, ad8522 },
327 },
328 [BOARD_PCI6032E] = {
329 .name = "pci-6032e",
330 .n_adchan = 16,
331 .ai_maxdata = 0xffff,
332 .ai_fifo_depth = 512,
333 .alwaysdither = 1,
334 .gainlkup = ai_gain_14,
335 .ai_speed = 10000,
336 .caldac = { dac8800, dac8043, ad8522 },
337 },
338 [BOARD_PCI6033E] = {
339 .name = "pci-6033e",
340 .n_adchan = 64,
341 .ai_maxdata = 0xffff,
342 .ai_fifo_depth = 512,
343 .alwaysdither = 1,
344 .gainlkup = ai_gain_14,
345 .ai_speed = 10000,
346 .caldac = { dac8800, dac8043, ad8522 },
347 },
348 [BOARD_PCI6071E] = {
349 .name = "pci-6071e",
350 .n_adchan = 64,
351 .ai_maxdata = 0x0fff,
352 .ai_fifo_depth = 512,
353 .alwaysdither = 1,
354 .gainlkup = ai_gain_16,
355 .ai_speed = 800,
356 .n_aochan = 2,
357 .ao_maxdata = 0x0fff,
358 .ao_fifo_depth = 2048,
359 .ao_range_table = &range_ni_E_ao_ext,
360 .ao_speed = 1000,
361 .caldac = { ad8804_debug },
362 },
363 [BOARD_PCI6023E] = {
364 .name = "pci-6023e",
365 .n_adchan = 16,
366 .ai_maxdata = 0x0fff,
367 .ai_fifo_depth = 512,
368 .gainlkup = ai_gain_4,
369 .ai_speed = 5000,
370 .caldac = { ad8804_debug },
371 },
372 [BOARD_PCI6024E] = {
373 .name = "pci-6024e",
374 .n_adchan = 16,
375 .ai_maxdata = 0x0fff,
376 .ai_fifo_depth = 512,
377 .gainlkup = ai_gain_4,
378 .ai_speed = 5000,
379 .n_aochan = 2,
380 .ao_maxdata = 0x0fff,
381 .ao_range_table = &range_bipolar10,
382 .ao_speed = 100000,
383 .caldac = { ad8804_debug },
384 },
385 [BOARD_PCI6025E] = {
386 .name = "pci-6025e",
387 .n_adchan = 16,
388 .ai_maxdata = 0x0fff,
389 .ai_fifo_depth = 512,
390 .gainlkup = ai_gain_4,
391 .ai_speed = 5000,
392 .n_aochan = 2,
393 .ao_maxdata = 0x0fff,
394 .ao_range_table = &range_bipolar10,
395 .ao_speed = 100000,
396 .caldac = { ad8804_debug },
397 .has_8255 = 1,
398 },
399 [BOARD_PXI6025E] = {
400 .name = "pxi-6025e",
401 .n_adchan = 16,
402 .ai_maxdata = 0x0fff,
403 .ai_fifo_depth = 512,
404 .gainlkup = ai_gain_4,
405 .ai_speed = 5000,
406 .n_aochan = 2,
407 .ao_maxdata = 0x0fff,
408 .ao_range_table = &range_ni_E_ao_ext,
409 .ao_speed = 100000,
410 .caldac = { ad8804_debug },
411 .has_8255 = 1,
412 },
413 [BOARD_PCI6034E] = {
414 .name = "pci-6034e",
415 .n_adchan = 16,
416 .ai_maxdata = 0xffff,
417 .ai_fifo_depth = 512,
418 .alwaysdither = 1,
419 .gainlkup = ai_gain_4,
420 .ai_speed = 5000,
421 .caldac = { ad8804_debug },
422 },
423 [BOARD_PCI6035E] = {
424 .name = "pci-6035e",
425 .n_adchan = 16,
426 .ai_maxdata = 0xffff,
427 .ai_fifo_depth = 512,
428 .alwaysdither = 1,
429 .gainlkup = ai_gain_4,
430 .ai_speed = 5000,
431 .n_aochan = 2,
432 .ao_maxdata = 0x0fff,
433 .ao_range_table = &range_bipolar10,
434 .ao_speed = 100000,
435 .caldac = { ad8804_debug },
436 },
437 [BOARD_PCI6052E] = {
438 .name = "pci-6052e",
439 .n_adchan = 16,
440 .ai_maxdata = 0xffff,
441 .ai_fifo_depth = 512,
442 .alwaysdither = 1,
443 .gainlkup = ai_gain_16,
444 .ai_speed = 3000,
445 .n_aochan = 2,
446 .ao_maxdata = 0xffff,
447 .ao_fifo_depth = 2048,
448 .ao_range_table = &range_ni_E_ao_ext,
449 .ao_speed = 3000,
450
451 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
452 },
453 [BOARD_PCI6110] = {
454 .name = "pci-6110",
455 .n_adchan = 4,
456 .ai_maxdata = 0x0fff,
457 .ai_fifo_depth = 8192,
458 .alwaysdither = 0,
459 .gainlkup = ai_gain_611x,
460 .ai_speed = 200,
461 .n_aochan = 2,
462 .ao_maxdata = 0xffff,
463 .reg_type = ni_reg_611x,
464 .ao_range_table = &range_bipolar10,
465 .ao_fifo_depth = 2048,
466 .ao_speed = 250,
467 .caldac = { ad8804, ad8804 },
468 },
469 [BOARD_PCI6111] = {
470 .name = "pci-6111",
471 .n_adchan = 2,
472 .ai_maxdata = 0x0fff,
473 .ai_fifo_depth = 8192,
474 .gainlkup = ai_gain_611x,
475 .ai_speed = 200,
476 .n_aochan = 2,
477 .ao_maxdata = 0xffff,
478 .reg_type = ni_reg_611x,
479 .ao_range_table = &range_bipolar10,
480 .ao_fifo_depth = 2048,
481 .ao_speed = 250,
482 .caldac = { ad8804, ad8804 },
483 },
484 #if 0
485
486 [BOARD_PCI6115] = {
487 .name = "pci-6115",
488 .n_adchan = 4,
489 .ai_maxdata = 0x0fff,
490 .ai_fifo_depth = 8192,
491 .gainlkup = ai_gain_611x,
492 .ai_speed = 100,
493 .n_aochan = 2,
494 .ao_maxdata = 0xffff,
495 .ao_671x = 1,
496 .ao_fifo_depth = 2048,
497 .ao_speed = 250,
498 .reg_611x = 1,
499
500 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
501 },
502 #endif
503 #if 0
504 [BOARD_PXI6115] = {
505 .name = "pxi-6115",
506 .n_adchan = 4,
507 .ai_maxdata = 0x0fff,
508 .ai_fifo_depth = 8192,
509 .gainlkup = ai_gain_611x,
510 .ai_speed = 100,
511 .n_aochan = 2,
512 .ao_maxdata = 0xffff,
513 .ao_671x = 1,
514 .ao_fifo_depth = 2048,
515 .ao_speed = 250,
516 .reg_611x = 1,
517
518 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
519 },
520 #endif
521 [BOARD_PCI6711] = {
522 .name = "pci-6711",
523 .n_aochan = 4,
524 .ao_maxdata = 0x0fff,
525
526 .ao_fifo_depth = 16384,
527 .ao_range_table = &range_bipolar10,
528 .ao_speed = 1000,
529 .reg_type = ni_reg_6711,
530 .caldac = { ad8804_debug },
531 },
532 [BOARD_PXI6711] = {
533 .name = "pxi-6711",
534 .n_aochan = 4,
535 .ao_maxdata = 0x0fff,
536 .ao_fifo_depth = 16384,
537 .ao_range_table = &range_bipolar10,
538 .ao_speed = 1000,
539 .reg_type = ni_reg_6711,
540 .caldac = { ad8804_debug },
541 },
542 [BOARD_PCI6713] = {
543 .name = "pci-6713",
544 .n_aochan = 8,
545 .ao_maxdata = 0x0fff,
546 .ao_fifo_depth = 16384,
547 .ao_range_table = &range_bipolar10,
548 .ao_speed = 1000,
549 .reg_type = ni_reg_6713,
550 .caldac = { ad8804_debug, ad8804_debug },
551 },
552 [BOARD_PXI6713] = {
553 .name = "pxi-6713",
554 .n_aochan = 8,
555 .ao_maxdata = 0x0fff,
556 .ao_fifo_depth = 16384,
557 .ao_range_table = &range_bipolar10,
558 .ao_speed = 1000,
559 .reg_type = ni_reg_6713,
560 .caldac = { ad8804_debug, ad8804_debug },
561 },
562 [BOARD_PCI6731] = {
563 .name = "pci-6731",
564 .n_aochan = 4,
565 .ao_maxdata = 0xffff,
566 .ao_fifo_depth = 8192,
567 .ao_range_table = &range_bipolar10,
568 .ao_speed = 1000,
569 .reg_type = ni_reg_6711,
570 .caldac = { ad8804_debug },
571 },
572 #if 0
573 [BOARD_PXI6731] = {
574 .name = "pxi-6731",
575 .n_aochan = 4,
576 .ao_maxdata = 0xffff,
577 .ao_fifo_depth = 8192,
578 .ao_range_table = &range_bipolar10,
579 .reg_type = ni_reg_6711,
580 .caldac = { ad8804_debug },
581 },
582 #endif
583 [BOARD_PCI6733] = {
584 .name = "pci-6733",
585 .n_aochan = 8,
586 .ao_maxdata = 0xffff,
587 .ao_fifo_depth = 16384,
588 .ao_range_table = &range_bipolar10,
589 .ao_speed = 1000,
590 .reg_type = ni_reg_6713,
591 .caldac = { ad8804_debug, ad8804_debug },
592 },
593 [BOARD_PXI6733] = {
594 .name = "pxi-6733",
595 .n_aochan = 8,
596 .ao_maxdata = 0xffff,
597 .ao_fifo_depth = 16384,
598 .ao_range_table = &range_bipolar10,
599 .ao_speed = 1000,
600 .reg_type = ni_reg_6713,
601 .caldac = { ad8804_debug, ad8804_debug },
602 },
603 [BOARD_PXI6071E] = {
604 .name = "pxi-6071e",
605 .n_adchan = 64,
606 .ai_maxdata = 0x0fff,
607 .ai_fifo_depth = 512,
608 .alwaysdither = 1,
609 .gainlkup = ai_gain_16,
610 .ai_speed = 800,
611 .n_aochan = 2,
612 .ao_maxdata = 0x0fff,
613 .ao_fifo_depth = 2048,
614 .ao_range_table = &range_ni_E_ao_ext,
615 .ao_speed = 1000,
616 .caldac = { ad8804_debug },
617 },
618 [BOARD_PXI6070E] = {
619 .name = "pxi-6070e",
620 .n_adchan = 16,
621 .ai_maxdata = 0x0fff,
622 .ai_fifo_depth = 512,
623 .alwaysdither = 1,
624 .gainlkup = ai_gain_16,
625 .ai_speed = 800,
626 .n_aochan = 2,
627 .ao_maxdata = 0x0fff,
628 .ao_fifo_depth = 2048,
629 .ao_range_table = &range_ni_E_ao_ext,
630 .ao_speed = 1000,
631 .caldac = { ad8804_debug },
632 },
633 [BOARD_PXI6052E] = {
634 .name = "pxi-6052e",
635 .n_adchan = 16,
636 .ai_maxdata = 0xffff,
637 .ai_fifo_depth = 512,
638 .alwaysdither = 1,
639 .gainlkup = ai_gain_16,
640 .ai_speed = 3000,
641 .n_aochan = 2,
642 .ao_maxdata = 0xffff,
643 .ao_fifo_depth = 2048,
644 .ao_range_table = &range_ni_E_ao_ext,
645 .ao_speed = 3000,
646 .caldac = { mb88341, mb88341, ad8522 },
647 },
648 [BOARD_PXI6031E] = {
649 .name = "pxi-6031e",
650 .n_adchan = 64,
651 .ai_maxdata = 0xffff,
652 .ai_fifo_depth = 512,
653 .alwaysdither = 1,
654 .gainlkup = ai_gain_14,
655 .ai_speed = 10000,
656 .n_aochan = 2,
657 .ao_maxdata = 0xffff,
658 .ao_fifo_depth = 2048,
659 .ao_range_table = &range_ni_E_ao_ext,
660 .ao_speed = 10000,
661 .caldac = { dac8800, dac8043, ad8522 },
662 },
663 [BOARD_PCI6036E] = {
664 .name = "pci-6036e",
665 .n_adchan = 16,
666 .ai_maxdata = 0xffff,
667 .ai_fifo_depth = 512,
668 .alwaysdither = 1,
669 .gainlkup = ai_gain_4,
670 .ai_speed = 5000,
671 .n_aochan = 2,
672 .ao_maxdata = 0xffff,
673 .ao_range_table = &range_bipolar10,
674 .ao_speed = 100000,
675 .caldac = { ad8804_debug },
676 },
677 [BOARD_PCI6220] = {
678 .name = "pci-6220",
679 .n_adchan = 16,
680 .ai_maxdata = 0xffff,
681 .ai_fifo_depth = 512,
682 .gainlkup = ai_gain_622x,
683 .ai_speed = 4000,
684 .reg_type = ni_reg_622x,
685 .caldac = { caldac_none },
686 },
687 [BOARD_PXI6220] = {
688 .name = "pxi-6220",
689 .n_adchan = 16,
690 .ai_maxdata = 0xffff,
691 .ai_fifo_depth = 512,
692 .gainlkup = ai_gain_622x,
693 .ai_speed = 4000,
694 .reg_type = ni_reg_622x,
695 .caldac = { caldac_none },
696 .dio_speed = 1000,
697 },
698 [BOARD_PCI6221] = {
699 .name = "pci-6221",
700 .n_adchan = 16,
701 .ai_maxdata = 0xffff,
702 .ai_fifo_depth = 4095,
703 .gainlkup = ai_gain_622x,
704 .ai_speed = 4000,
705 .n_aochan = 2,
706 .ao_maxdata = 0xffff,
707 .ao_fifo_depth = 8191,
708 .ao_range_table = &range_bipolar10,
709 .reg_type = ni_reg_622x,
710 .ao_speed = 1200,
711 .caldac = { caldac_none },
712 .dio_speed = 1000,
713 },
714 [BOARD_PCI6221_37PIN] = {
715 .name = "pci-6221_37pin",
716 .n_adchan = 16,
717 .ai_maxdata = 0xffff,
718 .ai_fifo_depth = 4095,
719 .gainlkup = ai_gain_622x,
720 .ai_speed = 4000,
721 .n_aochan = 2,
722 .ao_maxdata = 0xffff,
723 .ao_fifo_depth = 8191,
724 .ao_range_table = &range_bipolar10,
725 .reg_type = ni_reg_622x,
726 .ao_speed = 1200,
727 .caldac = { caldac_none },
728 },
729 [BOARD_PXI6221] = {
730 .name = "pxi-6221",
731 .n_adchan = 16,
732 .ai_maxdata = 0xffff,
733 .ai_fifo_depth = 4095,
734 .gainlkup = ai_gain_622x,
735 .ai_speed = 4000,
736 .n_aochan = 2,
737 .ao_maxdata = 0xffff,
738 .ao_fifo_depth = 8191,
739 .ao_range_table = &range_bipolar10,
740 .reg_type = ni_reg_622x,
741 .ao_speed = 1200,
742 .caldac = { caldac_none },
743 .dio_speed = 1000,
744 },
745 [BOARD_PCI6224] = {
746 .name = "pci-6224",
747 .n_adchan = 32,
748 .ai_maxdata = 0xffff,
749 .ai_fifo_depth = 4095,
750 .gainlkup = ai_gain_622x,
751 .ai_speed = 4000,
752 .reg_type = ni_reg_622x,
753 .has_32dio_chan = 1,
754 .caldac = { caldac_none },
755 .dio_speed = 1000,
756 },
757 [BOARD_PXI6224] = {
758 .name = "pxi-6224",
759 .n_adchan = 32,
760 .ai_maxdata = 0xffff,
761 .ai_fifo_depth = 4095,
762 .gainlkup = ai_gain_622x,
763 .ai_speed = 4000,
764 .reg_type = ni_reg_622x,
765 .has_32dio_chan = 1,
766 .caldac = { caldac_none },
767 .dio_speed = 1000,
768 },
769 [BOARD_PCI6225] = {
770 .name = "pci-6225",
771 .n_adchan = 80,
772 .ai_maxdata = 0xffff,
773 .ai_fifo_depth = 4095,
774 .gainlkup = ai_gain_622x,
775 .ai_speed = 4000,
776 .n_aochan = 2,
777 .ao_maxdata = 0xffff,
778 .ao_fifo_depth = 8191,
779 .ao_range_table = &range_bipolar10,
780 .reg_type = ni_reg_622x,
781 .ao_speed = 1200,
782 .has_32dio_chan = 1,
783 .caldac = { caldac_none },
784 .dio_speed = 1000,
785 },
786 [BOARD_PXI6225] = {
787 .name = "pxi-6225",
788 .n_adchan = 80,
789 .ai_maxdata = 0xffff,
790 .ai_fifo_depth = 4095,
791 .gainlkup = ai_gain_622x,
792 .ai_speed = 4000,
793 .n_aochan = 2,
794 .ao_maxdata = 0xffff,
795 .ao_fifo_depth = 8191,
796 .ao_range_table = &range_bipolar10,
797 .reg_type = ni_reg_622x,
798 .ao_speed = 1200,
799 .has_32dio_chan = 1,
800 .caldac = { caldac_none },
801 .dio_speed = 1000,
802 },
803 [BOARD_PCI6229] = {
804 .name = "pci-6229",
805 .n_adchan = 32,
806 .ai_maxdata = 0xffff,
807 .ai_fifo_depth = 4095,
808 .gainlkup = ai_gain_622x,
809 .ai_speed = 4000,
810 .n_aochan = 4,
811 .ao_maxdata = 0xffff,
812 .ao_fifo_depth = 8191,
813 .ao_range_table = &range_bipolar10,
814 .reg_type = ni_reg_622x,
815 .ao_speed = 1200,
816 .has_32dio_chan = 1,
817 .caldac = { caldac_none },
818 },
819 [BOARD_PXI6229] = {
820 .name = "pxi-6229",
821 .n_adchan = 32,
822 .ai_maxdata = 0xffff,
823 .ai_fifo_depth = 4095,
824 .gainlkup = ai_gain_622x,
825 .ai_speed = 4000,
826 .n_aochan = 4,
827 .ao_maxdata = 0xffff,
828 .ao_fifo_depth = 8191,
829 .ao_range_table = &range_bipolar10,
830 .reg_type = ni_reg_622x,
831 .ao_speed = 1200,
832 .has_32dio_chan = 1,
833 .caldac = { caldac_none },
834 .dio_speed = 1000,
835 },
836 [BOARD_PCI6250] = {
837 .name = "pci-6250",
838 .n_adchan = 16,
839 .ai_maxdata = 0xffff,
840 .ai_fifo_depth = 4095,
841 .gainlkup = ai_gain_628x,
842 .ai_speed = 800,
843 .reg_type = ni_reg_625x,
844 .caldac = { caldac_none },
845 },
846 [BOARD_PXI6250] = {
847 .name = "pxi-6250",
848 .n_adchan = 16,
849 .ai_maxdata = 0xffff,
850 .ai_fifo_depth = 4095,
851 .gainlkup = ai_gain_628x,
852 .ai_speed = 800,
853 .reg_type = ni_reg_625x,
854 .caldac = { caldac_none },
855 .dio_speed = 100,
856 },
857 [BOARD_PCI6251] = {
858 .name = "pci-6251",
859 .n_adchan = 16,
860 .ai_maxdata = 0xffff,
861 .ai_fifo_depth = 4095,
862 .gainlkup = ai_gain_628x,
863 .ai_speed = 800,
864 .n_aochan = 2,
865 .ao_maxdata = 0xffff,
866 .ao_fifo_depth = 8191,
867 .ao_range_table = &range_ni_M_625x_ao,
868 .reg_type = ni_reg_625x,
869 .ao_speed = 350,
870 .caldac = { caldac_none },
871 .dio_speed = 100,
872 },
873 [BOARD_PXI6251] = {
874 .name = "pxi-6251",
875 .n_adchan = 16,
876 .ai_maxdata = 0xffff,
877 .ai_fifo_depth = 4095,
878 .gainlkup = ai_gain_628x,
879 .ai_speed = 800,
880 .n_aochan = 2,
881 .ao_maxdata = 0xffff,
882 .ao_fifo_depth = 8191,
883 .ao_range_table = &range_ni_M_625x_ao,
884 .reg_type = ni_reg_625x,
885 .ao_speed = 350,
886 .caldac = { caldac_none },
887 .dio_speed = 100,
888 },
889 [BOARD_PCIE6251] = {
890 .name = "pcie-6251",
891 .n_adchan = 16,
892 .ai_maxdata = 0xffff,
893 .ai_fifo_depth = 4095,
894 .gainlkup = ai_gain_628x,
895 .ai_speed = 800,
896 .n_aochan = 2,
897 .ao_maxdata = 0xffff,
898 .ao_fifo_depth = 8191,
899 .ao_range_table = &range_ni_M_625x_ao,
900 .reg_type = ni_reg_625x,
901 .ao_speed = 350,
902 .caldac = { caldac_none },
903 .dio_speed = 100,
904 },
905 [BOARD_PXIE6251] = {
906 .name = "pxie-6251",
907 .n_adchan = 16,
908 .ai_maxdata = 0xffff,
909 .ai_fifo_depth = 4095,
910 .gainlkup = ai_gain_628x,
911 .ai_speed = 800,
912 .n_aochan = 2,
913 .ao_maxdata = 0xffff,
914 .ao_fifo_depth = 8191,
915 .ao_range_table = &range_ni_M_625x_ao,
916 .reg_type = ni_reg_625x,
917 .ao_speed = 350,
918 .caldac = { caldac_none },
919 .dio_speed = 100,
920 },
921 [BOARD_PCI6254] = {
922 .name = "pci-6254",
923 .n_adchan = 32,
924 .ai_maxdata = 0xffff,
925 .ai_fifo_depth = 4095,
926 .gainlkup = ai_gain_628x,
927 .ai_speed = 800,
928 .reg_type = ni_reg_625x,
929 .has_32dio_chan = 1,
930 .caldac = { caldac_none },
931 },
932 [BOARD_PXI6254] = {
933 .name = "pxi-6254",
934 .n_adchan = 32,
935 .ai_maxdata = 0xffff,
936 .ai_fifo_depth = 4095,
937 .gainlkup = ai_gain_628x,
938 .ai_speed = 800,
939 .reg_type = ni_reg_625x,
940 .has_32dio_chan = 1,
941 .caldac = { caldac_none },
942 .dio_speed = 100,
943 },
944 [BOARD_PCI6259] = {
945 .name = "pci-6259",
946 .n_adchan = 32,
947 .ai_maxdata = 0xffff,
948 .ai_fifo_depth = 4095,
949 .gainlkup = ai_gain_628x,
950 .ai_speed = 800,
951 .n_aochan = 4,
952 .ao_maxdata = 0xffff,
953 .ao_fifo_depth = 8191,
954 .ao_range_table = &range_ni_M_625x_ao,
955 .reg_type = ni_reg_625x,
956 .ao_speed = 350,
957 .has_32dio_chan = 1,
958 .caldac = { caldac_none },
959 },
960 [BOARD_PXI6259] = {
961 .name = "pxi-6259",
962 .n_adchan = 32,
963 .ai_maxdata = 0xffff,
964 .ai_fifo_depth = 4095,
965 .gainlkup = ai_gain_628x,
966 .ai_speed = 800,
967 .n_aochan = 4,
968 .ao_maxdata = 0xffff,
969 .ao_fifo_depth = 8191,
970 .ao_range_table = &range_ni_M_625x_ao,
971 .reg_type = ni_reg_625x,
972 .ao_speed = 350,
973 .has_32dio_chan = 1,
974 .caldac = { caldac_none },
975 .dio_speed = 100,
976 },
977 [BOARD_PCIE6259] = {
978 .name = "pcie-6259",
979 .n_adchan = 32,
980 .ai_maxdata = 0xffff,
981 .ai_fifo_depth = 4095,
982 .gainlkup = ai_gain_628x,
983 .ai_speed = 800,
984 .n_aochan = 4,
985 .ao_maxdata = 0xffff,
986 .ao_fifo_depth = 8191,
987 .ao_range_table = &range_ni_M_625x_ao,
988 .reg_type = ni_reg_625x,
989 .ao_speed = 350,
990 .has_32dio_chan = 1,
991 .caldac = { caldac_none },
992 },
993 [BOARD_PXIE6259] = {
994 .name = "pxie-6259",
995 .n_adchan = 32,
996 .ai_maxdata = 0xffff,
997 .ai_fifo_depth = 4095,
998 .gainlkup = ai_gain_628x,
999 .ai_speed = 800,
1000 .n_aochan = 4,
1001 .ao_maxdata = 0xffff,
1002 .ao_fifo_depth = 8191,
1003 .ao_range_table = &range_ni_M_625x_ao,
1004 .reg_type = ni_reg_625x,
1005 .ao_speed = 350,
1006 .has_32dio_chan = 1,
1007 .caldac = { caldac_none },
1008 .dio_speed = 100,
1009 },
1010 [BOARD_PCI6280] = {
1011 .name = "pci-6280",
1012 .n_adchan = 16,
1013 .ai_maxdata = 0x3ffff,
1014 .ai_fifo_depth = 2047,
1015 .gainlkup = ai_gain_628x,
1016 .ai_speed = 1600,
1017 .ao_fifo_depth = 8191,
1018 .reg_type = ni_reg_628x,
1019 .caldac = { caldac_none },
1020 },
1021 [BOARD_PXI6280] = {
1022 .name = "pxi-6280",
1023 .n_adchan = 16,
1024 .ai_maxdata = 0x3ffff,
1025 .ai_fifo_depth = 2047,
1026 .gainlkup = ai_gain_628x,
1027 .ai_speed = 1600,
1028 .ao_fifo_depth = 8191,
1029 .reg_type = ni_reg_628x,
1030 .caldac = { caldac_none },
1031 .dio_speed = 100,
1032 },
1033 [BOARD_PCI6281] = {
1034 .name = "pci-6281",
1035 .n_adchan = 16,
1036 .ai_maxdata = 0x3ffff,
1037 .ai_fifo_depth = 2047,
1038 .gainlkup = ai_gain_628x,
1039 .ai_speed = 1600,
1040 .n_aochan = 2,
1041 .ao_maxdata = 0xffff,
1042 .ao_fifo_depth = 8191,
1043 .ao_range_table = &range_ni_M_628x_ao,
1044 .reg_type = ni_reg_628x,
1045 .ao_speed = 350,
1046 .caldac = { caldac_none },
1047 .dio_speed = 100,
1048 },
1049 [BOARD_PXI6281] = {
1050 .name = "pxi-6281",
1051 .n_adchan = 16,
1052 .ai_maxdata = 0x3ffff,
1053 .ai_fifo_depth = 2047,
1054 .gainlkup = ai_gain_628x,
1055 .ai_speed = 1600,
1056 .n_aochan = 2,
1057 .ao_maxdata = 0xffff,
1058 .ao_fifo_depth = 8191,
1059 .ao_range_table = &range_ni_M_628x_ao,
1060 .reg_type = ni_reg_628x,
1061 .ao_speed = 350,
1062 .caldac = { caldac_none },
1063 .dio_speed = 100,
1064 },
1065 [BOARD_PCI6284] = {
1066 .name = "pci-6284",
1067 .n_adchan = 32,
1068 .ai_maxdata = 0x3ffff,
1069 .ai_fifo_depth = 2047,
1070 .gainlkup = ai_gain_628x,
1071 .ai_speed = 1600,
1072 .reg_type = ni_reg_628x,
1073 .has_32dio_chan = 1,
1074 .caldac = { caldac_none },
1075 },
1076 [BOARD_PXI6284] = {
1077 .name = "pxi-6284",
1078 .n_adchan = 32,
1079 .ai_maxdata = 0x3ffff,
1080 .ai_fifo_depth = 2047,
1081 .gainlkup = ai_gain_628x,
1082 .ai_speed = 1600,
1083 .reg_type = ni_reg_628x,
1084 .has_32dio_chan = 1,
1085 .caldac = { caldac_none },
1086 .dio_speed = 100,
1087 },
1088 [BOARD_PCI6289] = {
1089 .name = "pci-6289",
1090 .n_adchan = 32,
1091 .ai_maxdata = 0x3ffff,
1092 .ai_fifo_depth = 2047,
1093 .gainlkup = ai_gain_628x,
1094 .ai_speed = 1600,
1095 .n_aochan = 4,
1096 .ao_maxdata = 0xffff,
1097 .ao_fifo_depth = 8191,
1098 .ao_range_table = &range_ni_M_628x_ao,
1099 .reg_type = ni_reg_628x,
1100 .ao_speed = 350,
1101 .has_32dio_chan = 1,
1102 .caldac = { caldac_none },
1103 },
1104 [BOARD_PXI6289] = {
1105 .name = "pxi-6289",
1106 .n_adchan = 32,
1107 .ai_maxdata = 0x3ffff,
1108 .ai_fifo_depth = 2047,
1109 .gainlkup = ai_gain_628x,
1110 .ai_speed = 1600,
1111 .n_aochan = 4,
1112 .ao_maxdata = 0xffff,
1113 .ao_fifo_depth = 8191,
1114 .ao_range_table = &range_ni_M_628x_ao,
1115 .reg_type = ni_reg_628x,
1116 .ao_speed = 350,
1117 .has_32dio_chan = 1,
1118 .caldac = { caldac_none },
1119 .dio_speed = 100,
1120 },
1121 [BOARD_PCI6143] = {
1122 .name = "pci-6143",
1123 .n_adchan = 8,
1124 .ai_maxdata = 0xffff,
1125 .ai_fifo_depth = 1024,
1126 .gainlkup = ai_gain_6143,
1127 .ai_speed = 4000,
1128 .reg_type = ni_reg_6143,
1129 .caldac = { ad8804_debug, ad8804_debug },
1130 },
1131 [BOARD_PXI6143] = {
1132 .name = "pxi-6143",
1133 .n_adchan = 8,
1134 .ai_maxdata = 0xffff,
1135 .ai_fifo_depth = 1024,
1136 .gainlkup = ai_gain_6143,
1137 .ai_speed = 4000,
1138 .reg_type = ni_reg_6143,
1139 .caldac = { ad8804_debug, ad8804_debug },
1140 },
1141 };
1142
1143 #include "ni_mio_common.c"
1144
1145 static int pcimio_ai_change(struct comedi_device *dev,
1146 struct comedi_subdevice *s)
1147 {
1148 struct ni_private *devpriv = dev->private;
1149 int ret;
1150
1151 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1152 if (ret < 0)
1153 return ret;
1154
1155 return 0;
1156 }
1157
1158 static int pcimio_ao_change(struct comedi_device *dev,
1159 struct comedi_subdevice *s)
1160 {
1161 struct ni_private *devpriv = dev->private;
1162 int ret;
1163
1164 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1165 if (ret < 0)
1166 return ret;
1167
1168 return 0;
1169 }
1170
1171 static int pcimio_gpct0_change(struct comedi_device *dev,
1172 struct comedi_subdevice *s)
1173 {
1174 struct ni_private *devpriv = dev->private;
1175 int ret;
1176
1177 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1178 if (ret < 0)
1179 return ret;
1180
1181 return 0;
1182 }
1183
1184 static int pcimio_gpct1_change(struct comedi_device *dev,
1185 struct comedi_subdevice *s)
1186 {
1187 struct ni_private *devpriv = dev->private;
1188 int ret;
1189
1190 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1191 if (ret < 0)
1192 return ret;
1193
1194 return 0;
1195 }
1196
1197 static int pcimio_dio_change(struct comedi_device *dev,
1198 struct comedi_subdevice *s)
1199 {
1200 struct ni_private *devpriv = dev->private;
1201 int ret;
1202
1203 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1204 if (ret < 0)
1205 return ret;
1206
1207 return 0;
1208 }
1209
1210 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1211 {
1212 struct ni_private *devpriv = dev->private;
1213 struct mite *mite = devpriv->mite;
1214 resource_size_t daq_phys_addr;
1215 static const int Start_Cal_EEPROM = 0x400;
1216 static const unsigned int window_size = 10;
1217 unsigned int old_iodwbsr_bits;
1218 unsigned int old_iodwbsr1_bits;
1219 unsigned int old_iodwcr1_bits;
1220 int i;
1221
1222
1223 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1224
1225 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1226 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1227 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1228 writel(0x0, mite->mmio + MITE_IODWBSR);
1229 writel(((0x80 | window_size) | daq_phys_addr),
1230 mite->mmio + MITE_IODWBSR_1);
1231 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1232 writel(0xf, mite->mmio + 0x30);
1233
1234 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1235 devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i);
1236
1237 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1238 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1239 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1240 writel(0x0, mite->mmio + 0x30);
1241 }
1242
1243 static void init_6143(struct comedi_device *dev)
1244 {
1245 const struct ni_board_struct *board = dev->board_ptr;
1246 struct ni_private *devpriv = dev->private;
1247
1248
1249 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1250
1251
1252
1253
1254 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1255
1256 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1257
1258 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1259
1260
1261 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1262
1263
1264 devpriv->ai_calib_source_enabled = 0;
1265 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1266 NI6143_CALIB_CHAN_REG);
1267 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1268 }
1269
1270 static void pcimio_detach(struct comedi_device *dev)
1271 {
1272 struct ni_private *devpriv = dev->private;
1273
1274 mio_common_detach(dev);
1275 if (dev->irq)
1276 free_irq(dev->irq, dev);
1277 if (devpriv) {
1278 mite_free_ring(devpriv->ai_mite_ring);
1279 mite_free_ring(devpriv->ao_mite_ring);
1280 mite_free_ring(devpriv->cdo_mite_ring);
1281 mite_free_ring(devpriv->gpct_mite_ring[0]);
1282 mite_free_ring(devpriv->gpct_mite_ring[1]);
1283 mite_detach(devpriv->mite);
1284 }
1285 if (dev->mmio)
1286 iounmap(dev->mmio);
1287 comedi_pci_disable(dev);
1288 }
1289
1290 static int pcimio_auto_attach(struct comedi_device *dev,
1291 unsigned long context)
1292 {
1293 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1294 const struct ni_board_struct *board = NULL;
1295 struct ni_private *devpriv;
1296 unsigned int irq;
1297 int ret;
1298
1299 if (context < ARRAY_SIZE(ni_boards))
1300 board = &ni_boards[context];
1301 if (!board)
1302 return -ENODEV;
1303 dev->board_ptr = board;
1304 dev->board_name = board->name;
1305
1306 ret = comedi_pci_enable(dev);
1307 if (ret)
1308 return ret;
1309
1310 ret = ni_alloc_private(dev);
1311 if (ret)
1312 return ret;
1313 devpriv = dev->private;
1314
1315 devpriv->mite = mite_attach(dev, false);
1316 if (!devpriv->mite)
1317 return -ENOMEM;
1318
1319 if (board->reg_type & ni_reg_m_series_mask)
1320 devpriv->is_m_series = 1;
1321 if (board->reg_type & ni_reg_6xxx_mask)
1322 devpriv->is_6xxx = 1;
1323 if (board->reg_type == ni_reg_611x)
1324 devpriv->is_611x = 1;
1325 if (board->reg_type == ni_reg_6143)
1326 devpriv->is_6143 = 1;
1327 if (board->reg_type == ni_reg_622x)
1328 devpriv->is_622x = 1;
1329 if (board->reg_type == ni_reg_625x)
1330 devpriv->is_625x = 1;
1331 if (board->reg_type == ni_reg_628x)
1332 devpriv->is_628x = 1;
1333 if (board->reg_type & ni_reg_67xx_mask)
1334 devpriv->is_67xx = 1;
1335 if (board->reg_type == ni_reg_6711)
1336 devpriv->is_6711 = 1;
1337 if (board->reg_type == ni_reg_6713)
1338 devpriv->is_6713 = 1;
1339
1340 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1341 if (!devpriv->ai_mite_ring)
1342 return -ENOMEM;
1343 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1344 if (!devpriv->ao_mite_ring)
1345 return -ENOMEM;
1346 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1347 if (!devpriv->cdo_mite_ring)
1348 return -ENOMEM;
1349 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1350 if (!devpriv->gpct_mite_ring[0])
1351 return -ENOMEM;
1352 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1353 if (!devpriv->gpct_mite_ring[1])
1354 return -ENOMEM;
1355
1356 if (devpriv->is_m_series)
1357 m_series_init_eeprom_buffer(dev);
1358 if (devpriv->is_6143)
1359 init_6143(dev);
1360
1361 irq = pcidev->irq;
1362 if (irq) {
1363 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1364 dev->board_name, dev);
1365 if (ret == 0)
1366 dev->irq = irq;
1367 }
1368
1369 ret = ni_E_init(dev, 0, 1);
1370 if (ret < 0)
1371 return ret;
1372
1373 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1374 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1375 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1376 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1377 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1378
1379 return 0;
1380 }
1381
1382 static struct comedi_driver ni_pcimio_driver = {
1383 .driver_name = "ni_pcimio",
1384 .module = THIS_MODULE,
1385 .auto_attach = pcimio_auto_attach,
1386 .detach = pcimio_detach,
1387 };
1388
1389 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1390 const struct pci_device_id *id)
1391 {
1392 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1393 }
1394
1395 static const struct pci_device_id ni_pcimio_pci_table[] = {
1396 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 },
1397 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1398 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1399 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1400 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1401 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1402 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1403 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1404 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1405 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1406 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1407 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1408 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1409 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1410 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1411 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1412 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1413 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1414 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1415 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1416 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1417 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1418 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1419 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1420 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1421 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1422 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1423 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1424 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1425 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1426 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1427 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1428 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1429 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1430 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1431 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1432 { PCI_VDEVICE(NI, 0x70ae), BOARD_PXI6220 },
1433 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1434 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1435 { PCI_VDEVICE(NI, 0x70b1), BOARD_PXI6229 },
1436 { PCI_VDEVICE(NI, 0x70b2), BOARD_PXI6259 },
1437 { PCI_VDEVICE(NI, 0x70b3), BOARD_PXI6289 },
1438 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1439 { PCI_VDEVICE(NI, 0x70b5), BOARD_PXI6221 },
1440 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1441 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1442 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1443 { PCI_VDEVICE(NI, 0x70b9), BOARD_PXI6250 },
1444 { PCI_VDEVICE(NI, 0x70ba), BOARD_PXI6254 },
1445 { PCI_VDEVICE(NI, 0x70bb), BOARD_PXI6280 },
1446 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1447 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1448 { PCI_VDEVICE(NI, 0x70be), BOARD_PXI6284 },
1449 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1450 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1451 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1452 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1453 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1454 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1455 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1456 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1457 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1458 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1459 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1460 { PCI_VDEVICE(NI, 0x72e9), BOARD_PXIE6259 },
1461 { 0 }
1462 };
1463 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1464
1465 static struct pci_driver ni_pcimio_pci_driver = {
1466 .name = "ni_pcimio",
1467 .id_table = ni_pcimio_pci_table,
1468 .probe = ni_pcimio_pci_probe,
1469 .remove = comedi_pci_auto_unconfig,
1470 };
1471 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1472
1473 MODULE_AUTHOR("Comedi http://www.comedi.org");
1474 MODULE_DESCRIPTION("Comedi low-level driver");
1475 MODULE_LICENSE("GPL");