drivers/staging/comedi/drivers/addi_apci

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This source file includes following definitions.
z8536_read
z8536_write
z8536_reset
apci1500_port_enable
apci1500_timer_enable
apci1500_ack_irq
apci1500_interrupt
apci1500_di_cancel
apci1500_di_inttrig_start
apci1500_di_cmd
apci1500_di_cmdtest
apci1500_di_cfg_trig
apci1500_di_insn_config
apci1500_di_insn_bits
apci1500_do_insn_bits
apci1500_timer_insn_config
apci1500_timer_insn_write
apci1500_timer_insn_read
apci1500_auto_attach
apci1500_detach
apci1500_pci_probe
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * addi_apci_1500.c
   4  * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
   5  *
   6  *      ADDI-DATA GmbH
   7  *      Dieselstrasse 3
   8  *      D-77833 Ottersweier
   9  *      Tel: +19(0)7223/9493-0
  10  *      Fax: +49(0)7223/9493-92
  11  *      http://www.addi-data.com
  12  *      info@addi-data.com
  13  */
  14 
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 
  18 #include "../comedi_pci.h"
  19 #include "amcc_s5933.h"
  20 #include "z8536.h"
  21 
  22 /*
  23  * PCI Bar 0 Register map (devpriv->amcc)
  24  * see amcc_s5933.h for register and bit defines
  25  */
  26 
  27 /*
  28  * PCI Bar 1 Register map (dev->iobase)
  29  * see z8536.h for Z8536 internal registers and bit defines
  30  */
  31 #define APCI1500_Z8536_PORTC_REG        0x00
  32 #define APCI1500_Z8536_PORTB_REG        0x01
  33 #define APCI1500_Z8536_PORTA_REG        0x02
  34 #define APCI1500_Z8536_CTRL_REG         0x03
  35 
  36 /*
  37  * PCI Bar 2 Register map (devpriv->addon)
  38  */
  39 #define APCI1500_CLK_SEL_REG            0x00
  40 #define APCI1500_DI_REG                 0x00
  41 #define APCI1500_DO_REG                 0x02
  42 
  43 struct apci1500_private {
  44         unsigned long amcc;
  45         unsigned long addon;
  46 
  47         unsigned int clk_src;
  48 
  49         /* Digital trigger configuration [0]=AND [1]=OR */
  50         unsigned int pm[2];     /* Pattern Mask */
  51         unsigned int pt[2];     /* Pattern Transition */
  52         unsigned int pp[2];     /* Pattern Polarity */
  53 };
  54 
  55 static unsigned int z8536_read(struct comedi_device *dev, unsigned int reg)
  56 {
  57         unsigned long flags;
  58         unsigned int val;
  59 
  60         spin_lock_irqsave(&dev->spinlock, flags);
  61         outb(reg, dev->iobase + APCI1500_Z8536_CTRL_REG);
  62         val = inb(dev->iobase + APCI1500_Z8536_CTRL_REG);
  63         spin_unlock_irqrestore(&dev->spinlock, flags);
  64 
  65         return val;
  66 }
  67 
  68 static void z8536_write(struct comedi_device *dev,
  69                         unsigned int val, unsigned int reg)
  70 {
  71         unsigned long flags;
  72 
  73         spin_lock_irqsave(&dev->spinlock, flags);
  74         outb(reg, dev->iobase + APCI1500_Z8536_CTRL_REG);
  75         outb(val, dev->iobase + APCI1500_Z8536_CTRL_REG);
  76         spin_unlock_irqrestore(&dev->spinlock, flags);
  77 }
  78 
  79 static void z8536_reset(struct comedi_device *dev)
  80 {
  81         unsigned long flags;
  82 
  83         /*
  84          * Even if the state of the Z8536 is not known, the following
  85          * sequence will reset it and put it in State 0.
  86          */
  87         spin_lock_irqsave(&dev->spinlock, flags);
  88         inb(dev->iobase + APCI1500_Z8536_CTRL_REG);
  89         outb(0, dev->iobase + APCI1500_Z8536_CTRL_REG);
  90         inb(dev->iobase + APCI1500_Z8536_CTRL_REG);
  91         outb(0, dev->iobase + APCI1500_Z8536_CTRL_REG);
  92         outb(1, dev->iobase + APCI1500_Z8536_CTRL_REG);
  93         outb(0, dev->iobase + APCI1500_Z8536_CTRL_REG);
  94         spin_unlock_irqrestore(&dev->spinlock, flags);
  95 
  96         /* Disable all Ports and Counter/Timers */
  97         z8536_write(dev, 0x00, Z8536_CFG_CTRL_REG);
  98 
  99         /*
 100          * Port A is connected to Ditial Input channels 0-7.
 101          * Configure the port to allow interrupt detection.
 102          */
 103         z8536_write(dev, Z8536_PAB_MODE_PTS_BIT |
 104                          Z8536_PAB_MODE_SB |
 105                          Z8536_PAB_MODE_PMS_DISABLE,
 106                     Z8536_PA_MODE_REG);
 107         z8536_write(dev, 0xff, Z8536_PB_DPP_REG);
 108         z8536_write(dev, 0xff, Z8536_PA_DD_REG);
 109 
 110         /*
 111          * Port B is connected to Ditial Input channels 8-13.
 112          * Configure the port to allow interrupt detection.
 113          *
 114          * NOTE: Bits 7 and 6 of Port B are connected to internal
 115          * diagnostic signals and bit 7 is inverted.
 116          */
 117         z8536_write(dev, Z8536_PAB_MODE_PTS_BIT |
 118                          Z8536_PAB_MODE_SB |
 119                          Z8536_PAB_MODE_PMS_DISABLE,
 120                     Z8536_PB_MODE_REG);
 121         z8536_write(dev, 0x7f, Z8536_PB_DPP_REG);
 122         z8536_write(dev, 0xff, Z8536_PB_DD_REG);
 123 
 124         /*
 125          * Not sure what Port C is connected to...
 126          */
 127         z8536_write(dev, 0x09, Z8536_PC_DPP_REG);
 128         z8536_write(dev, 0x0e, Z8536_PC_DD_REG);
 129 
 130         /*
 131          * Clear and disable all interrupt sources.
 132          *
 133          * Just in case, the reset of the Z8536 should have already
 134          * done this.
 135          */
 136         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_PA_CMDSTAT_REG);
 137         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_PA_CMDSTAT_REG);
 138 
 139         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_PB_CMDSTAT_REG);
 140         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_PB_CMDSTAT_REG);
 141 
 142         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_CT_CMDSTAT_REG(0));
 143         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_CT_CMDSTAT_REG(0));
 144 
 145         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_CT_CMDSTAT_REG(1));
 146         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_CT_CMDSTAT_REG(1));
 147 
 148         z8536_write(dev, Z8536_CMD_CLR_IP_IUS, Z8536_CT_CMDSTAT_REG(2));
 149         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_CT_CMDSTAT_REG(2));
 150 
 151         /* Disable all interrupts */
 152         z8536_write(dev, 0x00, Z8536_INT_CTRL_REG);
 153 }
 154 
 155 static void apci1500_port_enable(struct comedi_device *dev, bool enable)
 156 {
 157         unsigned int cfg;
 158 
 159         cfg = z8536_read(dev, Z8536_CFG_CTRL_REG);
 160         if (enable)
 161                 cfg |= (Z8536_CFG_CTRL_PAE | Z8536_CFG_CTRL_PBE);
 162         else
 163                 cfg &= ~(Z8536_CFG_CTRL_PAE | Z8536_CFG_CTRL_PBE);
 164         z8536_write(dev, cfg, Z8536_CFG_CTRL_REG);
 165 }
 166 
 167 static void apci1500_timer_enable(struct comedi_device *dev,
 168                                   unsigned int chan, bool enable)
 169 {
 170         unsigned int bit;
 171         unsigned int cfg;
 172 
 173         if (chan == 0)
 174                 bit = Z8536_CFG_CTRL_CT1E;
 175         else if (chan == 1)
 176                 bit = Z8536_CFG_CTRL_CT2E;
 177         else
 178                 bit = Z8536_CFG_CTRL_PCE_CT3E;
 179 
 180         cfg = z8536_read(dev, Z8536_CFG_CTRL_REG);
 181         if (enable) {
 182                 cfg |= bit;
 183         } else {
 184                 cfg &= ~bit;
 185                 z8536_write(dev, 0x00, Z8536_CT_CMDSTAT_REG(chan));
 186         }
 187         z8536_write(dev, cfg, Z8536_CFG_CTRL_REG);
 188 }
 189 
 190 static bool apci1500_ack_irq(struct comedi_device *dev,
 191                              unsigned int reg)
 192 {
 193         unsigned int val;
 194 
 195         val = z8536_read(dev, reg);
 196         if ((val & Z8536_STAT_IE_IP) == Z8536_STAT_IE_IP) {
 197                 val &= 0x0f;                    /* preserve any write bits */
 198                 val |= Z8536_CMD_CLR_IP_IUS;
 199                 z8536_write(dev, val, reg);
 200 
 201                 return true;
 202         }
 203         return false;
 204 }
 205 
 206 static irqreturn_t apci1500_interrupt(int irq, void *d)
 207 {
 208         struct comedi_device *dev = d;
 209         struct apci1500_private *devpriv = dev->private;
 210         struct comedi_subdevice *s = dev->read_subdev;
 211         unsigned int status = 0;
 212         unsigned int val;
 213 
 214         val = inl(devpriv->amcc + AMCC_OP_REG_INTCSR);
 215         if (!(val & INTCSR_INTR_ASSERTED))
 216                 return IRQ_NONE;
 217 
 218         if (apci1500_ack_irq(dev, Z8536_PA_CMDSTAT_REG))
 219                 status |= 0x01; /* port a event (inputs 0-7) */
 220 
 221         if (apci1500_ack_irq(dev, Z8536_PB_CMDSTAT_REG)) {
 222                 /* Tests if this is an external error */
 223                 val = inb(dev->iobase + APCI1500_Z8536_PORTB_REG);
 224                 val &= 0xc0;
 225                 if (val) {
 226                         if (val & 0x80) /* voltage error */
 227                                 status |= 0x40;
 228                         if (val & 0x40) /* short circuit error */
 229                                 status |= 0x80;
 230                 } else {
 231                         status |= 0x02; /* port b event (inputs 8-13) */
 232                 }
 233         }
 234 
 235         /*
 236          * NOTE: The 'status' returned by the sample matches the
 237          * interrupt mask information from the APCI-1500 Users Manual.
 238          *
 239          *    Mask     Meaning
 240          * ----------  ------------------------------------------
 241          * 0x00000001  Event 1 has occurred
 242          * 0x00000010  Event 2 has occurred
 243          * 0x00000100  Counter/timer 1 has run down (not implemented)
 244          * 0x00001000  Counter/timer 2 has run down (not implemented)
 245          * 0x00010000  Counter 3 has run down (not implemented)
 246          * 0x00100000  Watchdog has run down (not implemented)
 247          * 0x01000000  Voltage error
 248          * 0x10000000  Short-circuit error
 249          */
 250         comedi_buf_write_samples(s, &status, 1);
 251         comedi_handle_events(dev, s);
 252 
 253         return IRQ_HANDLED;
 254 }
 255 
 256 static int apci1500_di_cancel(struct comedi_device *dev,
 257                               struct comedi_subdevice *s)
 258 {
 259         /* Disables the main interrupt on the board */
 260         z8536_write(dev, 0x00, Z8536_INT_CTRL_REG);
 261 
 262         /* Disable Ports A & B */
 263         apci1500_port_enable(dev, false);
 264 
 265         /* Ack any pending interrupts */
 266         apci1500_ack_irq(dev, Z8536_PA_CMDSTAT_REG);
 267         apci1500_ack_irq(dev, Z8536_PB_CMDSTAT_REG);
 268 
 269         /* Disable pattern interrupts */
 270         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_PA_CMDSTAT_REG);
 271         z8536_write(dev, Z8536_CMD_CLR_IE, Z8536_PB_CMDSTAT_REG);
 272 
 273         /* Enable Ports A & B */
 274         apci1500_port_enable(dev, true);
 275 
 276         return 0;
 277 }
 278 
 279 static int apci1500_di_inttrig_start(struct comedi_device *dev,
 280                                      struct comedi_subdevice *s,
 281                                      unsigned int trig_num)
 282 {
 283         struct apci1500_private *devpriv = dev->private;
 284         struct comedi_cmd *cmd = &s->async->cmd;
 285         unsigned int pa_mode = Z8536_PAB_MODE_PMS_DISABLE;
 286         unsigned int pb_mode = Z8536_PAB_MODE_PMS_DISABLE;
 287         unsigned int pa_trig = trig_num & 0x01;
 288         unsigned int pb_trig = (trig_num >> 1) & 0x01;
 289         bool valid_trig = false;
 290         unsigned int val;
 291 
 292         if (trig_num != cmd->start_arg)
 293                 return -EINVAL;
 294 
 295         /* Disable Ports A & B */
 296         apci1500_port_enable(dev, false);
 297 
 298         /* Set Port A for selected trigger pattern */
 299         z8536_write(dev, devpriv->pm[pa_trig] & 0xff, Z8536_PA_PM_REG);
 300         z8536_write(dev, devpriv->pt[pa_trig] & 0xff, Z8536_PA_PT_REG);
 301         z8536_write(dev, devpriv->pp[pa_trig] & 0xff, Z8536_PA_PP_REG);
 302 
 303         /* Set Port B for selected trigger pattern */
 304         z8536_write(dev, (devpriv->pm[pb_trig] >> 8) & 0xff, Z8536_PB_PM_REG);
 305         z8536_write(dev, (devpriv->pt[pb_trig] >> 8) & 0xff, Z8536_PB_PT_REG);
 306         z8536_write(dev, (devpriv->pp[pb_trig] >> 8) & 0xff, Z8536_PB_PP_REG);
 307 
 308         /* Set Port A trigger mode (if enabled) and enable interrupt */
 309         if (devpriv->pm[pa_trig] & 0xff) {
 310                 pa_mode = pa_trig ? Z8536_PAB_MODE_PMS_AND
 311                                   : Z8536_PAB_MODE_PMS_OR;
 312 
 313                 val = z8536_read(dev, Z8536_PA_MODE_REG);
 314                 val &= ~Z8536_PAB_MODE_PMS_MASK;
 315                 val |= (pa_mode | Z8536_PAB_MODE_IMO);
 316                 z8536_write(dev, val, Z8536_PA_MODE_REG);
 317 
 318                 z8536_write(dev, Z8536_CMD_SET_IE, Z8536_PA_CMDSTAT_REG);
 319 
 320                 valid_trig = true;
 321 
 322                 dev_dbg(dev->class_dev,
 323                         "Port A configured for %s mode pattern detection\n",
 324                         pa_trig ? "AND" : "OR");
 325         }
 326 
 327         /* Set Port B trigger mode (if enabled) and enable interrupt */
 328         if (devpriv->pm[pb_trig] & 0xff00) {
 329                 pb_mode = pb_trig ? Z8536_PAB_MODE_PMS_AND
 330                                   : Z8536_PAB_MODE_PMS_OR;
 331 
 332                 val = z8536_read(dev, Z8536_PB_MODE_REG);
 333                 val &= ~Z8536_PAB_MODE_PMS_MASK;
 334                 val |= (pb_mode | Z8536_PAB_MODE_IMO);
 335                 z8536_write(dev, val, Z8536_PB_MODE_REG);
 336 
 337                 z8536_write(dev, Z8536_CMD_SET_IE, Z8536_PB_CMDSTAT_REG);
 338 
 339                 valid_trig = true;
 340 
 341                 dev_dbg(dev->class_dev,
 342                         "Port B configured for %s mode pattern detection\n",
 343                         pb_trig ? "AND" : "OR");
 344         }
 345 
 346         /* Enable Ports A & B */
 347         apci1500_port_enable(dev, true);
 348 
 349         if (!valid_trig) {
 350                 dev_dbg(dev->class_dev,
 351                         "digital trigger %d is not configured\n", trig_num);
 352                 return -EINVAL;
 353         }
 354 
 355         /* Authorizes the main interrupt on the board */
 356         z8536_write(dev, Z8536_INT_CTRL_MIE | Z8536_INT_CTRL_DLC,
 357                     Z8536_INT_CTRL_REG);
 358 
 359         return 0;
 360 }
 361 
 362 static int apci1500_di_cmd(struct comedi_device *dev,
 363                            struct comedi_subdevice *s)
 364 {
 365         s->async->inttrig = apci1500_di_inttrig_start;
 366 
 367         return 0;
 368 }
 369 
 370 static int apci1500_di_cmdtest(struct comedi_device *dev,
 371                                struct comedi_subdevice *s,
 372                                struct comedi_cmd *cmd)
 373 {
 374         int err = 0;
 375 
 376         /* Step 1 : check if triggers are trivially valid */
 377 
 378         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
 379         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
 380         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
 381         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 382         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
 383 
 384         if (err)
 385                 return 1;
 386 
 387         /* Step 2a : make sure trigger sources are unique */
 388         /* Step 2b : and mutually compatible */
 389 
 390         /* Step 3: check if arguments are trivially valid */
 391 
 392         /*
 393          * Internal start source triggers:
 394          *
 395          *   0  AND mode for Port A (digital inputs 0-7)
 396          *      AND mode for Port B (digital inputs 8-13 and internal signals)
 397          *
 398          *   1  OR mode for Port A (digital inputs 0-7)
 399          *      AND mode for Port B (digital inputs 8-13 and internal signals)
 400          *
 401          *   2  AND mode for Port A (digital inputs 0-7)
 402          *      OR mode for Port B (digital inputs 8-13 and internal signals)
 403          *
 404          *   3  OR mode for Port A (digital inputs 0-7)
 405          *      OR mode for Port B (digital inputs 8-13 and internal signals)
 406          */
 407         err |= comedi_check_trigger_arg_max(&cmd->start_arg, 3);
 408 
 409         err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
 410         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 411         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 412                                            cmd->chanlist_len);
 413         err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 414 
 415         if (err)
 416                 return 3;
 417 
 418         /* Step 4: fix up any arguments */
 419 
 420         /* Step 5: check channel list if it exists */
 421 
 422         return 0;
 423 }
 424 
 425 /*
 426  * The pattern-recognition logic must be configured before the digital
 427  * input async command is started.
 428  *
 429  * Digital input channels 0 to 13 can generate interrupts. Channels 14
 430  * and 15 are connected to internal board status/diagnostic signals.
 431  *
 432  * Channel 14 - Voltage error (the external supply is < 5V)
 433  * Channel 15 - Short-circuit/overtemperature error
 434  *
 435  *      data[0] : INSN_CONFIG_DIGITAL_TRIG
 436  *      data[1] : trigger number
 437  *                0 = AND mode
 438  *                1 = OR mode
 439  *      data[2] : configuration operation:
 440  *                COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
 441  *                COMEDI_DIGITAL_TRIG_ENABLE_EDGES = edge interrupts
 442  *                COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = level interrupts
 443  *      data[3] : left-shift for data[4] and data[5]
 444  *      data[4] : rising-edge/high level channels
 445  *      data[5] : falling-edge/low level channels
 446  */
 447 static int apci1500_di_cfg_trig(struct comedi_device *dev,
 448                                 struct comedi_subdevice *s,
 449                                 struct comedi_insn *insn,
 450                                 unsigned int *data)
 451 {
 452         struct apci1500_private *devpriv = dev->private;
 453         unsigned int trig = data[1];
 454         unsigned int shift = data[3];
 455         unsigned int hi_mask = data[4] << shift;
 456         unsigned int lo_mask = data[5] << shift;
 457         unsigned int chan_mask = hi_mask | lo_mask;
 458         unsigned int old_mask = (1 << shift) - 1;
 459         unsigned int pm = devpriv->pm[trig] & old_mask;
 460         unsigned int pt = devpriv->pt[trig] & old_mask;
 461         unsigned int pp = devpriv->pp[trig] & old_mask;
 462 
 463         if (trig > 1) {
 464                 dev_dbg(dev->class_dev,
 465                         "invalid digital trigger number (0=AND, 1=OR)\n");
 466                 return -EINVAL;
 467         }
 468 
 469         if (chan_mask > 0xffff) {
 470                 dev_dbg(dev->class_dev, "invalid digital trigger channel\n");
 471                 return -EINVAL;
 472         }
 473 
 474         switch (data[2]) {
 475         case COMEDI_DIGITAL_TRIG_DISABLE:
 476                 /* clear trigger configuration */
 477                 pm = 0;
 478                 pt = 0;
 479                 pp = 0;
 480                 break;
 481         case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
 482                 pm |= chan_mask;        /* enable channels */
 483                 pt |= chan_mask;        /* enable edge detection */
 484                 pp |= hi_mask;          /* rising-edge channels */
 485                 pp &= ~lo_mask;         /* falling-edge channels */
 486                 break;
 487         case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
 488                 pm |= chan_mask;        /* enable channels */
 489                 pt &= ~chan_mask;       /* enable level detection */
 490                 pp |= hi_mask;          /* high level channels */
 491                 pp &= ~lo_mask;         /* low level channels */
 492                 break;
 493         default:
 494                 return -EINVAL;
 495         }
 496 
 497         /*
 498          * The AND mode trigger can only have one channel (max) enabled
 499          * for edge detection.
 500          */
 501         if (trig == 0) {
 502                 int ret = 0;
 503                 unsigned int src;
 504 
 505                 src = pt & 0xff;
 506                 if (src)
 507                         ret |= comedi_check_trigger_is_unique(src);
 508 
 509                 src = (pt >> 8) & 0xff;
 510                 if (src)
 511                         ret |= comedi_check_trigger_is_unique(src);
 512 
 513                 if (ret) {
 514                         dev_dbg(dev->class_dev,
 515                                 "invalid AND trigger configuration\n");
 516                         return ret;
 517                 }
 518         }
 519 
 520         /* save the trigger configuration */
 521         devpriv->pm[trig] = pm;
 522         devpriv->pt[trig] = pt;
 523         devpriv->pp[trig] = pp;
 524 
 525         return insn->n;
 526 }
 527 
 528 static int apci1500_di_insn_config(struct comedi_device *dev,
 529                                    struct comedi_subdevice *s,
 530                                    struct comedi_insn *insn,
 531                                    unsigned int *data)
 532 {
 533         switch (data[0]) {
 534         case INSN_CONFIG_DIGITAL_TRIG:
 535                 return apci1500_di_cfg_trig(dev, s, insn, data);
 536         default:
 537                 return -EINVAL;
 538         }
 539 }
 540 
 541 static int apci1500_di_insn_bits(struct comedi_device *dev,
 542                                  struct comedi_subdevice *s,
 543                                  struct comedi_insn *insn,
 544                                  unsigned int *data)
 545 {
 546         struct apci1500_private *devpriv = dev->private;
 547 
 548         data[1] = inw(devpriv->addon + APCI1500_DI_REG);
 549 
 550         return insn->n;
 551 }
 552 
 553 static int apci1500_do_insn_bits(struct comedi_device *dev,
 554                                  struct comedi_subdevice *s,
 555                                  struct comedi_insn *insn,
 556                                  unsigned int *data)
 557 {
 558         struct apci1500_private *devpriv = dev->private;
 559 
 560         if (comedi_dio_update_state(s, data))
 561                 outw(s->state, devpriv->addon + APCI1500_DO_REG);
 562 
 563         data[1] = s->state;
 564 
 565         return insn->n;
 566 }
 567 
 568 static int apci1500_timer_insn_config(struct comedi_device *dev,
 569                                       struct comedi_subdevice *s,
 570                                       struct comedi_insn *insn,
 571                                       unsigned int *data)
 572 {
 573         struct apci1500_private *devpriv = dev->private;
 574         unsigned int chan = CR_CHAN(insn->chanspec);
 575         unsigned int val;
 576 
 577         switch (data[0]) {
 578         case INSN_CONFIG_ARM:
 579                 val = data[1] & s->maxdata;
 580                 z8536_write(dev, val & 0xff, Z8536_CT_RELOAD_LSB_REG(chan));
 581                 z8536_write(dev, (val >> 8) & 0xff,
 582                             Z8536_CT_RELOAD_MSB_REG(chan));
 583 
 584                 apci1500_timer_enable(dev, chan, true);
 585                 z8536_write(dev, Z8536_CT_CMDSTAT_GCB,
 586                             Z8536_CT_CMDSTAT_REG(chan));
 587                 break;
 588         case INSN_CONFIG_DISARM:
 589                 apci1500_timer_enable(dev, chan, false);
 590                 break;
 591 
 592         case INSN_CONFIG_GET_COUNTER_STATUS:
 593                 data[1] = 0;
 594                 val = z8536_read(dev, Z8536_CT_CMDSTAT_REG(chan));
 595                 if (val & Z8536_CT_STAT_CIP)
 596                         data[1] |= COMEDI_COUNTER_COUNTING;
 597                 if (val & Z8536_CT_CMDSTAT_GCB)
 598                         data[1] |= COMEDI_COUNTER_ARMED;
 599                 if (val & Z8536_STAT_IP) {
 600                         data[1] |= COMEDI_COUNTER_TERMINAL_COUNT;
 601                         apci1500_ack_irq(dev, Z8536_CT_CMDSTAT_REG(chan));
 602                 }
 603                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING |
 604                           COMEDI_COUNTER_TERMINAL_COUNT;
 605                 break;
 606 
 607         case INSN_CONFIG_SET_COUNTER_MODE:
 608                 /* Simulate the 8254 timer modes */
 609                 switch (data[1]) {
 610                 case I8254_MODE0:
 611                         /* Interrupt on Terminal Count */
 612                         val = Z8536_CT_MODE_ECE |
 613                               Z8536_CT_MODE_DCS_ONESHOT;
 614                         break;
 615                 case I8254_MODE1:
 616                         /* Hardware Retriggerable One-Shot */
 617                         val = Z8536_CT_MODE_ETE |
 618                               Z8536_CT_MODE_DCS_ONESHOT;
 619                         break;
 620                 case I8254_MODE2:
 621                         /* Rate Generator */
 622                         val = Z8536_CT_MODE_CSC |
 623                               Z8536_CT_MODE_DCS_PULSE;
 624                         break;
 625                 case I8254_MODE3:
 626                         /* Square Wave Mode */
 627                         val = Z8536_CT_MODE_CSC |
 628                               Z8536_CT_MODE_DCS_SQRWAVE;
 629                         break;
 630                 case I8254_MODE4:
 631                         /* Software Triggered Strobe */
 632                         val = Z8536_CT_MODE_REB |
 633                               Z8536_CT_MODE_DCS_PULSE;
 634                         break;
 635                 case I8254_MODE5:
 636                         /* Hardware Triggered Strobe (watchdog) */
 637                         val = Z8536_CT_MODE_EOE |
 638                               Z8536_CT_MODE_ETE |
 639                               Z8536_CT_MODE_REB |
 640                               Z8536_CT_MODE_DCS_PULSE;
 641                         break;
 642                 default:
 643                         return -EINVAL;
 644                 }
 645                 apci1500_timer_enable(dev, chan, false);
 646                 z8536_write(dev, val, Z8536_CT_MODE_REG(chan));
 647                 break;
 648 
 649         case INSN_CONFIG_SET_CLOCK_SRC:
 650                 if (data[1] > 2)
 651                         return -EINVAL;
 652                 devpriv->clk_src = data[1];
 653                 if (devpriv->clk_src == 2)
 654                         devpriv->clk_src = 3;
 655                 outw(devpriv->clk_src, devpriv->addon + APCI1500_CLK_SEL_REG);
 656                 break;
 657         case INSN_CONFIG_GET_CLOCK_SRC:
 658                 switch (devpriv->clk_src) {
 659                 case 0:
 660                         data[1] = 0;            /* 111.86 kHz / 2 */
 661                         data[2] = 17879;        /* 17879 ns (approx) */
 662                         break;
 663                 case 1:
 664                         data[1] = 1;            /* 3.49 kHz / 2 */
 665                         data[2] = 573066;       /* 573066 ns (approx) */
 666                         break;
 667                 case 3:
 668                         data[1] = 2;            /* 1.747 kHz / 2 */
 669                         data[2] = 1164822;      /* 1164822 ns (approx) */
 670                         break;
 671                 default:
 672                         return -EINVAL;
 673                 }
 674                 break;
 675 
 676         case INSN_CONFIG_SET_GATE_SRC:
 677                 if (chan == 0)
 678                         return -EINVAL;
 679 
 680                 val = z8536_read(dev, Z8536_CT_MODE_REG(chan));
 681                 val &= Z8536_CT_MODE_EGE;
 682                 if (data[1] == 1)
 683                         val |= Z8536_CT_MODE_EGE;
 684                 else if (data[1] > 1)
 685                         return -EINVAL;
 686                 z8536_write(dev, val, Z8536_CT_MODE_REG(chan));
 687                 break;
 688         case INSN_CONFIG_GET_GATE_SRC:
 689                 if (chan == 0)
 690                         return -EINVAL;
 691                 break;
 692 
 693         default:
 694                 return -EINVAL;
 695         }
 696         return insn->n;
 697 }
 698 
 699 static int apci1500_timer_insn_write(struct comedi_device *dev,
 700                                      struct comedi_subdevice *s,
 701                                      struct comedi_insn *insn,
 702                                      unsigned int *data)
 703 {
 704         unsigned int chan = CR_CHAN(insn->chanspec);
 705         unsigned int cmd;
 706 
 707         cmd = z8536_read(dev, Z8536_CT_CMDSTAT_REG(chan));
 708         cmd &= Z8536_CT_CMDSTAT_GCB;    /* preserve gate */
 709         cmd |= Z8536_CT_CMD_TCB;        /* set trigger */
 710 
 711         /* software trigger a timer, it only makes sense to do one write */
 712         if (insn->n)
 713                 z8536_write(dev, cmd, Z8536_CT_CMDSTAT_REG(chan));
 714 
 715         return insn->n;
 716 }
 717 
 718 static int apci1500_timer_insn_read(struct comedi_device *dev,
 719                                     struct comedi_subdevice *s,
 720                                     struct comedi_insn *insn,
 721                                     unsigned int *data)
 722 {
 723         unsigned int chan = CR_CHAN(insn->chanspec);
 724         unsigned int cmd;
 725         unsigned int val;
 726         int i;
 727 
 728         cmd = z8536_read(dev, Z8536_CT_CMDSTAT_REG(chan));
 729         cmd &= Z8536_CT_CMDSTAT_GCB;    /* preserve gate */
 730         cmd |= Z8536_CT_CMD_RCC;        /* set RCC */
 731 
 732         for (i = 0; i < insn->n; i++) {
 733                 z8536_write(dev, cmd, Z8536_CT_CMDSTAT_REG(chan));
 734 
 735                 val = z8536_read(dev, Z8536_CT_VAL_MSB_REG(chan)) << 8;
 736                 val |= z8536_read(dev, Z8536_CT_VAL_LSB_REG(chan));
 737 
 738                 data[i] = val;
 739         }
 740 
 741         return insn->n;
 742 }
 743 
 744 static int apci1500_auto_attach(struct comedi_device *dev,
 745                                 unsigned long context)
 746 {
 747         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 748         struct apci1500_private *devpriv;
 749         struct comedi_subdevice *s;
 750         int ret;
 751 
 752         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 753         if (!devpriv)
 754                 return -ENOMEM;
 755 
 756         ret = comedi_pci_enable(dev);
 757         if (ret)
 758                 return ret;
 759 
 760         dev->iobase = pci_resource_start(pcidev, 1);
 761         devpriv->amcc = pci_resource_start(pcidev, 0);
 762         devpriv->addon = pci_resource_start(pcidev, 2);
 763 
 764         z8536_reset(dev);
 765 
 766         if (pcidev->irq > 0) {
 767                 ret = request_irq(pcidev->irq, apci1500_interrupt, IRQF_SHARED,
 768                                   dev->board_name, dev);
 769                 if (ret == 0)
 770                         dev->irq = pcidev->irq;
 771         }
 772 
 773         ret = comedi_alloc_subdevices(dev, 3);
 774         if (ret)
 775                 return ret;
 776 
 777         /* Digital Input subdevice */
 778         s = &dev->subdevices[0];
 779         s->type         = COMEDI_SUBD_DI;
 780         s->subdev_flags = SDF_READABLE;
 781         s->n_chan       = 16;
 782         s->maxdata      = 1;
 783         s->range_table  = &range_digital;
 784         s->insn_bits    = apci1500_di_insn_bits;
 785         if (dev->irq) {
 786                 dev->read_subdev = s;
 787                 s->subdev_flags |= SDF_CMD_READ;
 788                 s->len_chanlist = 1;
 789                 s->insn_config  = apci1500_di_insn_config;
 790                 s->do_cmdtest   = apci1500_di_cmdtest;
 791                 s->do_cmd       = apci1500_di_cmd;
 792                 s->cancel       = apci1500_di_cancel;
 793         }
 794 
 795         /* Digital Output subdevice */
 796         s = &dev->subdevices[1];
 797         s->type         = COMEDI_SUBD_DO;
 798         s->subdev_flags = SDF_WRITABLE;
 799         s->n_chan       = 16;
 800         s->maxdata      = 1;
 801         s->range_table  = &range_digital;
 802         s->insn_bits    = apci1500_do_insn_bits;
 803 
 804         /* reset all the digital outputs */
 805         outw(0x0, devpriv->addon + APCI1500_DO_REG);
 806 
 807         /* Counter/Timer(Watchdog) subdevice */
 808         s = &dev->subdevices[2];
 809         s->type         = COMEDI_SUBD_TIMER;
 810         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
 811         s->n_chan       = 3;
 812         s->maxdata      = 0xffff;
 813         s->range_table  = &range_unknown;
 814         s->insn_config  = apci1500_timer_insn_config;
 815         s->insn_write   = apci1500_timer_insn_write;
 816         s->insn_read    = apci1500_timer_insn_read;
 817 
 818         /* Enable the PCI interrupt */
 819         if (dev->irq) {
 820                 outl(0x2000 | INTCSR_INBOX_FULL_INT,
 821                      devpriv->amcc + AMCC_OP_REG_INTCSR);
 822                 inl(devpriv->amcc + AMCC_OP_REG_IMB1);
 823                 inl(devpriv->amcc + AMCC_OP_REG_INTCSR);
 824                 outl(INTCSR_INBOX_INTR_STATUS | 0x2000 | INTCSR_INBOX_FULL_INT,
 825                      devpriv->amcc + AMCC_OP_REG_INTCSR);
 826         }
 827 
 828         return 0;
 829 }
 830 
 831 static void apci1500_detach(struct comedi_device *dev)
 832 {
 833         struct apci1500_private *devpriv = dev->private;
 834 
 835         if (devpriv->amcc)
 836                 outl(0x0, devpriv->amcc + AMCC_OP_REG_INTCSR);
 837         comedi_pci_detach(dev);
 838 }
 839 
 840 static struct comedi_driver apci1500_driver = {
 841         .driver_name    = "addi_apci_1500",
 842         .module         = THIS_MODULE,
 843         .auto_attach    = apci1500_auto_attach,
 844         .detach         = apci1500_detach,
 845 };
 846 
 847 static int apci1500_pci_probe(struct pci_dev *dev,
 848                               const struct pci_device_id *id)
 849 {
 850         return comedi_pci_auto_config(dev, &apci1500_driver, id->driver_data);
 851 }
 852 
 853 static const struct pci_device_id apci1500_pci_table[] = {
 854         { PCI_DEVICE(PCI_VENDOR_ID_AMCC, 0x80fc) },
 855         { 0 }
 856 };
 857 MODULE_DEVICE_TABLE(pci, apci1500_pci_table);
 858 
 859 static struct pci_driver apci1500_pci_driver = {
 860         .name           = "addi_apci_1500",
 861         .id_table       = apci1500_pci_table,
 862         .probe          = apci1500_pci_probe,
 863         .remove         = comedi_pci_auto_unconfig,
 864 };
 865 module_comedi_pci_driver(apci1500_driver, apci1500_pci_driver);
 866 
 867 MODULE_AUTHOR("Comedi http://www.comedi.org");
 868 MODULE_DESCRIPTION("ADDI-DATA APCI-1500, 16 channel DI / 16 channel DO boards");
 869 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/staging/comedi/drivers/addi_apci_1500.c

DEFINITIONS
