root/drivers/staging/comedi/drivers/ni_mio_common.c

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DEFINITIONS

This source file includes following definitions.
  1. ni_writel
  2. ni_writew
  3. ni_writeb
  4. ni_readl
  5. ni_readw
  6. ni_readb
  7. m_series_stc_write
  8. m_series_stc_read
  9. ni_stc_writew
  10. ni_stc_writel
  11. ni_stc_readw
  12. ni_stc_readl
  13. ni_set_bitfield
  14. ni_request_ai_mite_channel
  15. ni_request_ao_mite_channel
  16. ni_request_gpct_mite_channel
  17. ni_request_cdo_mite_channel
  18. ni_release_ai_mite_channel
  19. ni_release_ao_mite_channel
  20. ni_release_gpct_mite_channel
  21. ni_release_cdo_mite_channel
  22. ni_e_series_enable_second_irq
  23. ni_clear_ai_fifo
  24. ni_ao_win_outw
  25. ni_ao_win_outl
  26. ni_ao_win_inw
  27. ni_set_bits
  28. ni_sync_ai_dma
  29. ni_ai_drain_dma
  30. ni_ao_wait_for_dma_load
  31. ni_ao_fifo_load
  32. ni_ao_fifo_half_empty
  33. ni_ao_prep_fifo
  34. ni_ai_fifo_read
  35. ni_handle_fifo_half_full
  36. ni_handle_fifo_dregs
  37. get_last_sample_611x
  38. get_last_sample_6143
  39. shutdown_ai_command
  40. ni_handle_eos
  41. handle_gpct_interrupt
  42. ack_a_interrupt
  43. handle_a_interrupt
  44. ack_b_interrupt
  45. handle_b_interrupt
  46. ni_ai_munge
  47. ni_ai_setup_MITE_dma
  48. ni_ao_setup_MITE_dma
  49. ni_ai_reset
  50. ni_ai_poll
  51. ni_prime_channelgain_list
  52. ni_m_series_load_channelgain_list
  53. ni_load_channelgain_list
  54. ni_ai_insn_read
  55. ni_ns_to_timer
  56. ni_timer_to_ns
  57. ni_cmd_set_mite_transfer
  58. ni_min_ai_scan_period_ns
  59. ni_ai_cmdtest
  60. ni_ai_inttrig
  61. ni_ai_cmd
  62. ni_ai_insn_config
  63. ni_ao_munge
  64. ni_m_series_ao_config_chanlist
  65. ni_old_ao_config_chanlist
  66. ni_ao_config_chanlist
  67. ni_ao_insn_write
  68. ni_ao_arm
  69. ni_ao_insn_config
  70. ni_ao_inttrig
  71. ni_ao_cmd_personalize
  72. ni_ao_cmd_set_trigger
  73. ni_ao_cmd_set_counters
  74. ni_ao_cmd_set_update
  75. ni_ao_cmd_set_channels
  76. ni_ao_cmd_set_stop_conditions
  77. ni_ao_cmd_set_fifo_mode
  78. ni_ao_cmd_set_interrupts
  79. ni_ao_cmd
  80. ni_ao_cmdtest
  81. ni_ao_reset
  82. ni_dio_insn_config
  83. ni_dio_insn_bits
  84. ni_m_series_dio_insn_config
  85. ni_m_series_dio_insn_bits
  86. ni_cdio_check_chanlist
  87. ni_cdio_cmdtest
  88. ni_cdo_inttrig
  89. ni_cdio_cmd
  90. ni_cdio_cancel
  91. handle_cdio_interrupt
  92. ni_serial_hw_readwrite8
  93. ni_serial_sw_readwrite8
  94. ni_serial_insn_config
  95. init_ao_67xx
  96. ni_gpct_to_stc_register
  97. ni_gpct_write_register
  98. ni_gpct_read_register
  99. ni_freq_out_insn_read
  100. ni_freq_out_insn_write
  101. ni_freq_out_insn_config
  102. ni_8255_callback
  103. ni_get_pwm_config
  104. ni_m_series_pwm_config
  105. ni_6143_pwm_config
  106. pack_mb88341
  107. pack_dac8800
  108. pack_dac8043
  109. pack_ad8522
  110. pack_ad8804
  111. pack_ad8842
  112. ni_write_caldac
  113. ni_calib_insn_write
  114. ni_calib_insn_read
  115. caldac_setup
  116. ni_read_eeprom
  117. ni_eeprom_insn_read
  118. ni_m_series_eeprom_insn_read
  119. ni_old_get_pfi_routing
  120. ni_old_set_pfi_routing
  121. ni_m_series_get_pfi_routing
  122. ni_m_series_set_pfi_routing
  123. ni_get_pfi_routing
  124. ni_set_pfi_routing
  125. ni_config_pfi_filter
  126. ni_set_pfi_direction
  127. ni_get_pfi_direction
  128. ni_pfi_insn_config
  129. ni_pfi_insn_bits
  130. cs5529_wait_for_idle
  131. cs5529_command
  132. cs5529_do_conversion
  133. cs5529_ai_insn_read
  134. cs5529_config_write
  135. init_cs5529
  136. ni_mseries_get_pll_parameters
  137. ni_mseries_set_pll_master_clock
  138. ni_set_master_clock
  139. ni_valid_rtsi_output_source
  140. ni_set_rtsi_routing
  141. ni_get_rtsi_routing
  142. ni_set_rtsi_direction
  143. ni_get_rtsi_direction
  144. ni_rtsi_insn_config
  145. ni_rtsi_insn_bits
  146. set_rgout0_reg
  147. get_rgout0_reg
  148. get_rgout0_src
  149. incr_rgout0_src_use
  150. decr_rgout0_src_use
  151. set_ith_rtsi_brd_reg
  152. get_ith_rtsi_brd_reg
  153. get_rtsi_brd_src
  154. incr_rtsi_brd_src_use
  155. decr_rtsi_brd_src_use
  156. ni_rtsi_init
  157. ni_get_gout_routing
  158. ni_disable_gout_routing
  159. ni_set_gout_routing
  160. get_output_select_source
  161. test_route
  162. connect_route
  163. disconnect_route
  164. ni_global_insn_config
  165. ni_gpct_cmd
  166. ni_gpct_cancel
  167. ni_E_interrupt
  168. ni_alloc_private
  169. _ni_get_valid_routes
  170. ni_E_init
  171. mio_common_detach

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Hardware driver for DAQ-STC based boards
   4  *
   5  * COMEDI - Linux Control and Measurement Device Interface
   6  * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7  * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8  */
   9 
  10 /*
  11  * This file is meant to be included by another file, e.g.,
  12  * ni_atmio.c or ni_pcimio.c.
  13  *
  14  * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
  15  *
  16  * References (ftp://ftp.natinst.com/support/manuals):
  17  *   340747b.pdf  AT-MIO E series Register Level Programmer Manual
  18  *   341079b.pdf  PCI E Series RLPM
  19  *   340934b.pdf  DAQ-STC reference manual
  20  *
  21  * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  22  *   release_ni611x.pdf
  23  *   release_ni67xx.pdf
  24  *
  25  * Other possibly relevant info:
  26  *   320517c.pdf  User manual (obsolete)
  27  *   320517f.pdf  User manual (new)
  28  *   320889a.pdf  delete
  29  *   320906c.pdf  maximum signal ratings
  30  *   321066a.pdf  about 16x
  31  *   321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  32  *   321808a.pdf  about at-mio-16e-10 rev P
  33  *   321837a.pdf  discontinuation of at-mio-16de-10 rev d
  34  *   321838a.pdf  about at-mio-16de-10 rev N
  35  *
  36  * ISSUES:
  37  *   - the interrupt routine needs to be cleaned up
  38  *
  39  * 2006-02-07: S-Series PCI-6143: Support has been added but is not
  40  * fully tested as yet. Terry Barnaby, BEAM Ltd.
  41  */
  42 
  43 #include <linux/interrupt.h>
  44 #include <linux/sched.h>
  45 #include <linux/delay.h>
  46 #include "8255.h"
  47 #include "mite.h"
  48 
  49 /* A timeout count */
  50 #define NI_TIMEOUT 1000
  51 
  52 /* Note: this table must match the ai_gain_* definitions */
  53 static const short ni_gainlkup[][16] = {
  54         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  55                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  56         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  57         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  58                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  59         [ai_gain_4] = {0, 1, 4, 7},
  60         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  61                           0x003, 0x004, 0x005, 0x006},
  62         [ai_gain_622x] = {0, 1, 4, 5},
  63         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  64         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  65 };
  66 
  67 static const struct comedi_lrange range_ni_E_ai = {
  68         16, {
  69                 BIP_RANGE(10),
  70                 BIP_RANGE(5),
  71                 BIP_RANGE(2.5),
  72                 BIP_RANGE(1),
  73                 BIP_RANGE(0.5),
  74                 BIP_RANGE(0.25),
  75                 BIP_RANGE(0.1),
  76                 BIP_RANGE(0.05),
  77                 UNI_RANGE(20),
  78                 UNI_RANGE(10),
  79                 UNI_RANGE(5),
  80                 UNI_RANGE(2),
  81                 UNI_RANGE(1),
  82                 UNI_RANGE(0.5),
  83                 UNI_RANGE(0.2),
  84                 UNI_RANGE(0.1)
  85         }
  86 };
  87 
  88 static const struct comedi_lrange range_ni_E_ai_limited = {
  89         8, {
  90                 BIP_RANGE(10),
  91                 BIP_RANGE(5),
  92                 BIP_RANGE(1),
  93                 BIP_RANGE(0.1),
  94                 UNI_RANGE(10),
  95                 UNI_RANGE(5),
  96                 UNI_RANGE(1),
  97                 UNI_RANGE(0.1)
  98         }
  99 };
 100 
 101 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 102         14, {
 103                 BIP_RANGE(10),
 104                 BIP_RANGE(5),
 105                 BIP_RANGE(2),
 106                 BIP_RANGE(1),
 107                 BIP_RANGE(0.5),
 108                 BIP_RANGE(0.2),
 109                 BIP_RANGE(0.1),
 110                 UNI_RANGE(10),
 111                 UNI_RANGE(5),
 112                 UNI_RANGE(2),
 113                 UNI_RANGE(1),
 114                 UNI_RANGE(0.5),
 115                 UNI_RANGE(0.2),
 116                 UNI_RANGE(0.1)
 117         }
 118 };
 119 
 120 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 121         4, {
 122                 BIP_RANGE(10),
 123                 BIP_RANGE(5),
 124                 BIP_RANGE(0.5),
 125                 BIP_RANGE(0.05)
 126         }
 127 };
 128 
 129 static const struct comedi_lrange range_ni_E_ai_611x = {
 130         8, {
 131                 BIP_RANGE(50),
 132                 BIP_RANGE(20),
 133                 BIP_RANGE(10),
 134                 BIP_RANGE(5),
 135                 BIP_RANGE(2),
 136                 BIP_RANGE(1),
 137                 BIP_RANGE(0.5),
 138                 BIP_RANGE(0.2)
 139         }
 140 };
 141 
 142 static const struct comedi_lrange range_ni_M_ai_622x = {
 143         4, {
 144                 BIP_RANGE(10),
 145                 BIP_RANGE(5),
 146                 BIP_RANGE(1),
 147                 BIP_RANGE(0.2)
 148         }
 149 };
 150 
 151 static const struct comedi_lrange range_ni_M_ai_628x = {
 152         7, {
 153                 BIP_RANGE(10),
 154                 BIP_RANGE(5),
 155                 BIP_RANGE(2),
 156                 BIP_RANGE(1),
 157                 BIP_RANGE(0.5),
 158                 BIP_RANGE(0.2),
 159                 BIP_RANGE(0.1)
 160         }
 161 };
 162 
 163 static const struct comedi_lrange range_ni_E_ao_ext = {
 164         4, {
 165                 BIP_RANGE(10),
 166                 UNI_RANGE(10),
 167                 RANGE_ext(-1, 1),
 168                 RANGE_ext(0, 1)
 169         }
 170 };
 171 
 172 static const struct comedi_lrange *const ni_range_lkup[] = {
 173         [ai_gain_16] = &range_ni_E_ai,
 174         [ai_gain_8] = &range_ni_E_ai_limited,
 175         [ai_gain_14] = &range_ni_E_ai_limited14,
 176         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 177         [ai_gain_611x] = &range_ni_E_ai_611x,
 178         [ai_gain_622x] = &range_ni_M_ai_622x,
 179         [ai_gain_628x] = &range_ni_M_ai_628x,
 180         [ai_gain_6143] = &range_bipolar5
 181 };
 182 
 183 enum aimodes {
 184         AIMODE_NONE = 0,
 185         AIMODE_HALF_FULL = 1,
 186         AIMODE_SCAN = 2,
 187         AIMODE_SAMPLE = 3,
 188 };
 189 
 190 enum ni_common_subdevices {
 191         NI_AI_SUBDEV,
 192         NI_AO_SUBDEV,
 193         NI_DIO_SUBDEV,
 194         NI_8255_DIO_SUBDEV,
 195         NI_UNUSED_SUBDEV,
 196         NI_CALIBRATION_SUBDEV,
 197         NI_EEPROM_SUBDEV,
 198         NI_PFI_DIO_SUBDEV,
 199         NI_CS5529_CALIBRATION_SUBDEV,
 200         NI_SERIAL_SUBDEV,
 201         NI_RTSI_SUBDEV,
 202         NI_GPCT0_SUBDEV,
 203         NI_GPCT1_SUBDEV,
 204         NI_FREQ_OUT_SUBDEV,
 205         NI_NUM_SUBDEVICES
 206 };
 207 
 208 #define NI_GPCT_SUBDEV(x)       (NI_GPCT0_SUBDEV + (x))
 209 
 210 enum timebase_nanoseconds {
 211         TIMEBASE_1_NS = 50,
 212         TIMEBASE_2_NS = 10000
 213 };
 214 
 215 #define SERIAL_DISABLED         0
 216 #define SERIAL_600NS            600
 217 #define SERIAL_1_2US            1200
 218 #define SERIAL_10US                     10000
 219 
 220 static const int num_adc_stages_611x = 3;
 221 
 222 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
 223 {
 224         if (dev->mmio)
 225                 writel(data, dev->mmio + reg);
 226         else
 227                 outl(data, dev->iobase + reg);
 228 }
 229 
 230 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
 231 {
 232         if (dev->mmio)
 233                 writew(data, dev->mmio + reg);
 234         else
 235                 outw(data, dev->iobase + reg);
 236 }
 237 
 238 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
 239 {
 240         if (dev->mmio)
 241                 writeb(data, dev->mmio + reg);
 242         else
 243                 outb(data, dev->iobase + reg);
 244 }
 245 
 246 static unsigned int ni_readl(struct comedi_device *dev, int reg)
 247 {
 248         if (dev->mmio)
 249                 return readl(dev->mmio + reg);
 250 
 251         return inl(dev->iobase + reg);
 252 }
 253 
 254 static unsigned int ni_readw(struct comedi_device *dev, int reg)
 255 {
 256         if (dev->mmio)
 257                 return readw(dev->mmio + reg);
 258 
 259         return inw(dev->iobase + reg);
 260 }
 261 
 262 static unsigned int ni_readb(struct comedi_device *dev, int reg)
 263 {
 264         if (dev->mmio)
 265                 return readb(dev->mmio + reg);
 266 
 267         return inb(dev->iobase + reg);
 268 }
 269 
 270 /*
 271  * We automatically take advantage of STC registers that can be
 272  * read/written directly in the I/O space of the board.
 273  *
 274  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 275  * iobase+reg*2.
 276  *
 277  * Most PCIMIO devices also map the low 8 STC registers but the
 278  * 611x devices map the read registers to iobase+(addr-1)*2.
 279  * For now non-windowed STC access is disabled if a PCIMIO device
 280  * is detected (devpriv->mite has been initialized).
 281  *
 282  * The M series devices do not used windowed registers for the
 283  * STC registers. The functions below handle the mapping of the
 284  * windowed STC registers to the m series register offsets.
 285  */
 286 
 287 struct mio_regmap {
 288         unsigned int mio_reg;
 289         int size;
 290 };
 291 
 292 static const struct mio_regmap m_series_stc_write_regmap[] = {
 293         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 294         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 295         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 296         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 297         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 298         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 299         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 300         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 301         /*
 302          * NISTC_DIO_OUT_REG maps to:
 303          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 304          */
 305         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 306         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 307         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 308         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 309         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 310         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 311         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 312         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 313         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 314         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 315         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 316         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 317         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 318         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 319         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 320         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 321         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 322         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 323         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 324         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 325         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 326         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 327         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 328         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 329         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 330         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 331         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 332         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 333         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 334         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 335         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 336         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 337         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 338         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 339         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 340         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 341         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 342         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 343         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 344         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 345         [NISTC_RESET_REG]               = { 0x190, 2 },
 346         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 347         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 348         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 349         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 350         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 351         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 352         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 353         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 354         /* doc for following line: mhddk/nimseries/ChipObjects/tMSeries.h */
 355         [NISTC_RTSI_BOARD_REG]          = { 0x1a2, 2 },
 356         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 357         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 358         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 359         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 360         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 361 };
 362 
 363 static void m_series_stc_write(struct comedi_device *dev,
 364                                unsigned int data, unsigned int reg)
 365 {
 366         const struct mio_regmap *regmap;
 367 
 368         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 369                 regmap = &m_series_stc_write_regmap[reg];
 370         } else {
 371                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 372                          __func__, reg);
 373                 return;
 374         }
 375 
 376         switch (regmap->size) {
 377         case 4:
 378                 ni_writel(dev, data, regmap->mio_reg);
 379                 break;
 380         case 2:
 381                 ni_writew(dev, data, regmap->mio_reg);
 382                 break;
 383         default:
 384                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 385                          __func__, reg);
 386                 break;
 387         }
 388 }
 389 
 390 static const struct mio_regmap m_series_stc_read_regmap[] = {
 391         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 392         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 393         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 394         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 395         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 396         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 397         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 398         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 399         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 400         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 401         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 402         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 403         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 404         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 405         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 406         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 407         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 408         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 409 };
 410 
 411 static unsigned int m_series_stc_read(struct comedi_device *dev,
 412                                       unsigned int reg)
 413 {
 414         const struct mio_regmap *regmap;
 415 
 416         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 417                 regmap = &m_series_stc_read_regmap[reg];
 418         } else {
 419                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 420                          __func__, reg);
 421                 return 0;
 422         }
 423 
 424         switch (regmap->size) {
 425         case 4:
 426                 return ni_readl(dev, regmap->mio_reg);
 427         case 2:
 428                 return ni_readw(dev, regmap->mio_reg);
 429         case 1:
 430                 return ni_readb(dev, regmap->mio_reg);
 431         default:
 432                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 433                          __func__, reg);
 434                 return 0;
 435         }
 436 }
 437 
 438 static void ni_stc_writew(struct comedi_device *dev,
 439                           unsigned int data, int reg)
 440 {
 441         struct ni_private *devpriv = dev->private;
 442         unsigned long flags;
 443 
 444         if (devpriv->is_m_series) {
 445                 m_series_stc_write(dev, data, reg);
 446         } else {
 447                 spin_lock_irqsave(&devpriv->window_lock, flags);
 448                 if (!devpriv->mite && reg < 8) {
 449                         ni_writew(dev, data, reg * 2);
 450                 } else {
 451                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 452                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 453                 }
 454                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 455         }
 456 }
 457 
 458 static void ni_stc_writel(struct comedi_device *dev,
 459                           unsigned int data, int reg)
 460 {
 461         struct ni_private *devpriv = dev->private;
 462 
 463         if (devpriv->is_m_series) {
 464                 m_series_stc_write(dev, data, reg);
 465         } else {
 466                 ni_stc_writew(dev, data >> 16, reg);
 467                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 468         }
 469 }
 470 
 471 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
 472 {
 473         struct ni_private *devpriv = dev->private;
 474         unsigned long flags;
 475         unsigned int val;
 476 
 477         if (devpriv->is_m_series) {
 478                 val = m_series_stc_read(dev, reg);
 479         } else {
 480                 spin_lock_irqsave(&devpriv->window_lock, flags);
 481                 if (!devpriv->mite && reg < 8) {
 482                         val = ni_readw(dev, reg * 2);
 483                 } else {
 484                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 485                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 486                 }
 487                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 488         }
 489         return val;
 490 }
 491 
 492 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
 493 {
 494         struct ni_private *devpriv = dev->private;
 495         unsigned int val;
 496 
 497         if (devpriv->is_m_series) {
 498                 val = m_series_stc_read(dev, reg);
 499         } else {
 500                 val = ni_stc_readw(dev, reg) << 16;
 501                 val |= ni_stc_readw(dev, reg + 1);
 502         }
 503         return val;
 504 }
 505 
 506 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 507                                    unsigned int bit_mask,
 508                                    unsigned int bit_values)
 509 {
 510         struct ni_private *devpriv = dev->private;
 511         unsigned long flags;
 512 
 513         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 514         switch (reg) {
 515         case NISTC_INTA_ENA_REG:
 516                 devpriv->int_a_enable_reg &= ~bit_mask;
 517                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 518                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 519                 break;
 520         case NISTC_INTB_ENA_REG:
 521                 devpriv->int_b_enable_reg &= ~bit_mask;
 522                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 523                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 524                 break;
 525         case NISTC_IO_BIDIR_PIN_REG:
 526                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 527                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 528                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 529                 break;
 530         case NI_E_DMA_AI_AO_SEL_REG:
 531                 devpriv->ai_ao_select_reg &= ~bit_mask;
 532                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 533                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 534                 break;
 535         case NI_E_DMA_G0_G1_SEL_REG:
 536                 devpriv->g0_g1_select_reg &= ~bit_mask;
 537                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 538                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 539                 break;
 540         case NI_M_CDIO_DMA_SEL_REG:
 541                 devpriv->cdio_dma_select_reg &= ~bit_mask;
 542                 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
 543                 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
 544                 break;
 545         default:
 546                 dev_err(dev->class_dev, "called with invalid register %d\n",
 547                         reg);
 548                 break;
 549         }
 550         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 551 }
 552 
 553 #ifdef PCIDMA
 554 
 555 /* selects the MITE channel to use for DMA */
 556 #define NI_STC_DMA_CHAN_SEL(x)  (((x) < 4) ? BIT(x) :   \
 557                                  ((x) == 4) ? 0x3 :     \
 558                                  ((x) == 5) ? 0x5 : 0x0)
 559 
 560 /* DMA channel setup */
 561 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 562 {
 563         struct ni_private *devpriv = dev->private;
 564         struct mite_channel *mite_chan;
 565         unsigned long flags;
 566         unsigned int bits;
 567 
 568         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 569         mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 570         if (!mite_chan) {
 571                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 572                 dev_err(dev->class_dev,
 573                         "failed to reserve mite dma channel for analog input\n");
 574                 return -EBUSY;
 575         }
 576         mite_chan->dir = COMEDI_INPUT;
 577         devpriv->ai_mite_chan = mite_chan;
 578 
 579         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 580         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 581                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 582 
 583         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 584         return 0;
 585 }
 586 
 587 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 588 {
 589         struct ni_private *devpriv = dev->private;
 590         struct mite_channel *mite_chan;
 591         unsigned long flags;
 592         unsigned int bits;
 593 
 594         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 595         mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 596         if (!mite_chan) {
 597                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 598                 dev_err(dev->class_dev,
 599                         "failed to reserve mite dma channel for analog output\n");
 600                 return -EBUSY;
 601         }
 602         mite_chan->dir = COMEDI_OUTPUT;
 603         devpriv->ao_mite_chan = mite_chan;
 604 
 605         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 606         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 607                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 608 
 609         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 610         return 0;
 611 }
 612 
 613 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 614                                         unsigned int gpct_index,
 615                                         enum comedi_io_direction direction)
 616 {
 617         struct ni_private *devpriv = dev->private;
 618         struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
 619         struct mite_channel *mite_chan;
 620         unsigned long flags;
 621         unsigned int bits;
 622 
 623         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 624         mite_chan = mite_request_channel(devpriv->mite,
 625                                          devpriv->gpct_mite_ring[gpct_index]);
 626         if (!mite_chan) {
 627                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 628                 dev_err(dev->class_dev,
 629                         "failed to reserve mite dma channel for counter\n");
 630                 return -EBUSY;
 631         }
 632         mite_chan->dir = direction;
 633         ni_tio_set_mite_channel(counter, mite_chan);
 634 
 635         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 636         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 637                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 638                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 639 
 640         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 641         return 0;
 642 }
 643 
 644 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 645 {
 646         struct ni_private *devpriv = dev->private;
 647         struct mite_channel *mite_chan;
 648         unsigned long flags;
 649         unsigned int bits;
 650 
 651         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 652         mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 653         if (!mite_chan) {
 654                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 655                 dev_err(dev->class_dev,
 656                         "failed to reserve mite dma channel for correlated digital output\n");
 657                 return -EBUSY;
 658         }
 659         mite_chan->dir = COMEDI_OUTPUT;
 660         devpriv->cdo_mite_chan = mite_chan;
 661 
 662         /*
 663          * XXX just guessing NI_STC_DMA_CHAN_SEL()
 664          * returns the right bits, under the assumption the cdio dma
 665          * selection works just like ai/ao/gpct.
 666          * Definitely works for dma channels 0 and 1.
 667          */
 668         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 669         ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 670                         NI_M_CDIO_DMA_SEL_CDO_MASK,
 671                         NI_M_CDIO_DMA_SEL_CDO(bits));
 672 
 673         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 674         return 0;
 675 }
 676 #endif /*  PCIDMA */
 677 
 678 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 679 {
 680 #ifdef PCIDMA
 681         struct ni_private *devpriv = dev->private;
 682         unsigned long flags;
 683 
 684         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 685         if (devpriv->ai_mite_chan) {
 686                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 687                                 NI_E_DMA_AI_SEL_MASK, 0);
 688                 mite_release_channel(devpriv->ai_mite_chan);
 689                 devpriv->ai_mite_chan = NULL;
 690         }
 691         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 692 #endif /*  PCIDMA */
 693 }
 694 
 695 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 696 {
 697 #ifdef PCIDMA
 698         struct ni_private *devpriv = dev->private;
 699         unsigned long flags;
 700 
 701         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 702         if (devpriv->ao_mite_chan) {
 703                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 704                                 NI_E_DMA_AO_SEL_MASK, 0);
 705                 mite_release_channel(devpriv->ao_mite_chan);
 706                 devpriv->ao_mite_chan = NULL;
 707         }
 708         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 709 #endif /*  PCIDMA */
 710 }
 711 
 712 #ifdef PCIDMA
 713 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 714                                          unsigned int gpct_index)
 715 {
 716         struct ni_private *devpriv = dev->private;
 717         unsigned long flags;
 718 
 719         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 720         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 721                 struct mite_channel *mite_chan =
 722                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 723 
 724                 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 725                                 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
 726                 ni_tio_set_mite_channel(&devpriv->
 727                                         counter_dev->counters[gpct_index],
 728                                         NULL);
 729                 mite_release_channel(mite_chan);
 730         }
 731         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 732 }
 733 
 734 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 735 {
 736         struct ni_private *devpriv = dev->private;
 737         unsigned long flags;
 738 
 739         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 740         if (devpriv->cdo_mite_chan) {
 741                 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 742                                 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
 743                 mite_release_channel(devpriv->cdo_mite_chan);
 744                 devpriv->cdo_mite_chan = NULL;
 745         }
 746         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 747 }
 748 
 749 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 750                                           unsigned int gpct_index, short enable)
 751 {
 752         struct ni_private *devpriv = dev->private;
 753         unsigned int val = 0;
 754         int reg;
 755 
 756         if (devpriv->is_m_series || gpct_index > 1)
 757                 return;
 758 
 759         /*
 760          * e-series boards use the second irq signals to generate
 761          * dma requests for their counters
 762          */
 763         if (gpct_index == 0) {
 764                 reg = NISTC_INTA2_ENA_REG;
 765                 if (enable)
 766                         val = NISTC_INTA_ENA_G0_GATE;
 767         } else {
 768                 reg = NISTC_INTB2_ENA_REG;
 769                 if (enable)
 770                         val = NISTC_INTB_ENA_G1_GATE;
 771         }
 772         ni_stc_writew(dev, val, reg);
 773 }
 774 #endif /*  PCIDMA */
 775 
 776 static void ni_clear_ai_fifo(struct comedi_device *dev)
 777 {
 778         struct ni_private *devpriv = dev->private;
 779         static const int timeout = 10000;
 780         int i;
 781 
 782         if (devpriv->is_6143) {
 783                 /*  Flush the 6143 data FIFO */
 784                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 785                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 786                 /*  Wait for complete */
 787                 for (i = 0; i < timeout; i++) {
 788                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 789                                 break;
 790                         udelay(1);
 791                 }
 792                 if (i == timeout)
 793                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 794         } else {
 795                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 796                 if (devpriv->is_625x) {
 797                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 798                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 799 #if 0
 800                         /*
 801                          * The NI example code does 3 convert pulses for 625x
 802                          * boards, But that appears to be wrong in practice.
 803                          */
 804                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 805                                       NISTC_AI_CMD1_REG);
 806                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 807                                       NISTC_AI_CMD1_REG);
 808                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 809                                       NISTC_AI_CMD1_REG);
 810 #endif
 811                 }
 812         }
 813 }
 814 
 815 static inline void ni_ao_win_outw(struct comedi_device *dev,
 816                                   unsigned int data, int addr)
 817 {
 818         struct ni_private *devpriv = dev->private;
 819         unsigned long flags;
 820 
 821         spin_lock_irqsave(&devpriv->window_lock, flags);
 822         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 823         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 824         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 825 }
 826 
 827 static inline void ni_ao_win_outl(struct comedi_device *dev,
 828                                   unsigned int data, int addr)
 829 {
 830         struct ni_private *devpriv = dev->private;
 831         unsigned long flags;
 832 
 833         spin_lock_irqsave(&devpriv->window_lock, flags);
 834         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 835         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 836         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 837 }
 838 
 839 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 840 {
 841         struct ni_private *devpriv = dev->private;
 842         unsigned long flags;
 843         unsigned short data;
 844 
 845         spin_lock_irqsave(&devpriv->window_lock, flags);
 846         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 847         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 848         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 849         return data;
 850 }
 851 
 852 /*
 853  * ni_set_bits( ) allows different parts of the ni_mio_common driver to
 854  * share registers (such as Interrupt_A_Register) without interfering with
 855  * each other.
 856  *
 857  * NOTE: the switch/case statements are optimized out for a constant argument
 858  * so this is actually quite fast---  If you must wrap another function around
 859  * this make it inline to avoid a large speed penalty.
 860  *
 861  * value should only be 1 or 0.
 862  */
 863 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 864                                unsigned int bits, unsigned int value)
 865 {
 866         unsigned int bit_values;
 867 
 868         if (value)
 869                 bit_values = bits;
 870         else
 871                 bit_values = 0;
 872         ni_set_bitfield(dev, reg, bits, bit_values);
 873 }
 874 
 875 #ifdef PCIDMA
 876 static void ni_sync_ai_dma(struct comedi_device *dev)
 877 {
 878         struct ni_private *devpriv = dev->private;
 879         struct comedi_subdevice *s = dev->read_subdev;
 880         unsigned long flags;
 881 
 882         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 883         if (devpriv->ai_mite_chan)
 884                 mite_sync_dma(devpriv->ai_mite_chan, s);
 885         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 886 }
 887 
 888 static int ni_ai_drain_dma(struct comedi_device *dev)
 889 {
 890         struct ni_private *devpriv = dev->private;
 891         int i;
 892         static const int timeout = 10000;
 893         unsigned long flags;
 894         int retval = 0;
 895 
 896         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 897         if (devpriv->ai_mite_chan) {
 898                 for (i = 0; i < timeout; i++) {
 899                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 900                              NISTC_AI_STATUS1_FIFO_E) &&
 901                             mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
 902                                 break;
 903                         udelay(5);
 904                 }
 905                 if (i == timeout) {
 906                         dev_err(dev->class_dev, "timed out\n");
 907                         dev_err(dev->class_dev,
 908                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 909                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 910                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 911                         retval = -1;
 912                 }
 913         }
 914         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 915 
 916         ni_sync_ai_dma(dev);
 917 
 918         return retval;
 919 }
 920 
 921 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 922 {
 923         static const int timeout = 10000;
 924         int i;
 925 
 926         for (i = 0; i < timeout; i++) {
 927                 unsigned short b_status;
 928 
 929                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
 930                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
 931                         break;
 932                 /*
 933                  * If we poll too often, the pci bus activity seems
 934                  * to slow the dma transfer down.
 935                  */
 936                 usleep_range(10, 100);
 937         }
 938         if (i == timeout) {
 939                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
 940                 return -EPIPE;
 941         }
 942         return 0;
 943 }
 944 #endif /* PCIDMA */
 945 
 946 #ifndef PCIDMA
 947 
 948 static void ni_ao_fifo_load(struct comedi_device *dev,
 949                             struct comedi_subdevice *s, int n)
 950 {
 951         struct ni_private *devpriv = dev->private;
 952         int i;
 953         unsigned short d;
 954         unsigned int packed_data;
 955 
 956         for (i = 0; i < n; i++) {
 957                 comedi_buf_read_samples(s, &d, 1);
 958 
 959                 if (devpriv->is_6xxx) {
 960                         packed_data = d & 0xffff;
 961                         /* 6711 only has 16 bit wide ao fifo */
 962                         if (!devpriv->is_6711) {
 963                                 comedi_buf_read_samples(s, &d, 1);
 964                                 i++;
 965                                 packed_data |= (d << 16) & 0xffff0000;
 966                         }
 967                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
 968                 } else {
 969                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
 970                 }
 971         }
 972 }
 973 
 974 /*
 975  *  There's a small problem if the FIFO gets really low and we
 976  *  don't have the data to fill it.  Basically, if after we fill
 977  *  the FIFO with all the data available, the FIFO is _still_
 978  *  less than half full, we never clear the interrupt.  If the
 979  *  IRQ is in edge mode, we never get another interrupt, because
 980  *  this one wasn't cleared.  If in level mode, we get flooded
 981  *  with interrupts that we can't fulfill, because nothing ever
 982  *  gets put into the buffer.
 983  *
 984  *  This kind of situation is recoverable, but it is easier to
 985  *  just pretend we had a FIFO underrun, since there is a good
 986  *  chance it will happen anyway.  This is _not_ the case for
 987  *  RT code, as RT code might purposely be running close to the
 988  *  metal.  Needs to be fixed eventually.
 989  */
 990 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 991                                  struct comedi_subdevice *s)
 992 {
 993         const struct ni_board_struct *board = dev->board_ptr;
 994         unsigned int nbytes;
 995         unsigned int nsamples;
 996 
 997         nbytes = comedi_buf_read_n_available(s);
 998         if (nbytes == 0) {
 999                 s->async->events |= COMEDI_CB_OVERFLOW;
1000                 return 0;
1001         }
1002 
1003         nsamples = comedi_bytes_to_samples(s, nbytes);
1004         if (nsamples > board->ao_fifo_depth / 2)
1005                 nsamples = board->ao_fifo_depth / 2;
1006 
1007         ni_ao_fifo_load(dev, s, nsamples);
1008 
1009         return 1;
1010 }
1011 
1012 static int ni_ao_prep_fifo(struct comedi_device *dev,
1013                            struct comedi_subdevice *s)
1014 {
1015         const struct ni_board_struct *board = dev->board_ptr;
1016         struct ni_private *devpriv = dev->private;
1017         unsigned int nbytes;
1018         unsigned int nsamples;
1019 
1020         /* reset fifo */
1021         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1022         if (devpriv->is_6xxx)
1023                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1024 
1025         /* load some data */
1026         nbytes = comedi_buf_read_n_available(s);
1027         if (nbytes == 0)
1028                 return 0;
1029 
1030         nsamples = comedi_bytes_to_samples(s, nbytes);
1031         if (nsamples > board->ao_fifo_depth)
1032                 nsamples = board->ao_fifo_depth;
1033 
1034         ni_ao_fifo_load(dev, s, nsamples);
1035 
1036         return nsamples;
1037 }
1038 
1039 static void ni_ai_fifo_read(struct comedi_device *dev,
1040                             struct comedi_subdevice *s, int n)
1041 {
1042         struct ni_private *devpriv = dev->private;
1043         struct comedi_async *async = s->async;
1044         unsigned int dl;
1045         unsigned short data;
1046         int i;
1047 
1048         if (devpriv->is_611x) {
1049                 for (i = 0; i < n / 2; i++) {
1050                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1051                         /* This may get the hi/lo data in the wrong order */
1052                         data = (dl >> 16) & 0xffff;
1053                         comedi_buf_write_samples(s, &data, 1);
1054                         data = dl & 0xffff;
1055                         comedi_buf_write_samples(s, &data, 1);
1056                 }
1057                 /* Check if there's a single sample stuck in the FIFO */
1058                 if (n % 2) {
1059                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1060                         data = dl & 0xffff;
1061                         comedi_buf_write_samples(s, &data, 1);
1062                 }
1063         } else if (devpriv->is_6143) {
1064                 /*
1065                  * This just reads the FIFO assuming the data is present,
1066                  * no checks on the FIFO status are performed.
1067                  */
1068                 for (i = 0; i < n / 2; i++) {
1069                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1070 
1071                         data = (dl >> 16) & 0xffff;
1072                         comedi_buf_write_samples(s, &data, 1);
1073                         data = dl & 0xffff;
1074                         comedi_buf_write_samples(s, &data, 1);
1075                 }
1076                 if (n % 2) {
1077                         /* Assume there is a single sample stuck in the FIFO */
1078                         /* Get stranded sample into FIFO */
1079                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1080                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1081                         data = (dl >> 16) & 0xffff;
1082                         comedi_buf_write_samples(s, &data, 1);
1083                 }
1084         } else {
1085                 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1086                         dev_err(dev->class_dev,
1087                                 "bug! ai_fifo_buffer too small\n");
1088                         async->events |= COMEDI_CB_ERROR;
1089                         return;
1090                 }
1091                 for (i = 0; i < n; i++) {
1092                         devpriv->ai_fifo_buffer[i] =
1093                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1094                 }
1095                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1096         }
1097 }
1098 
1099 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1100 {
1101         const struct ni_board_struct *board = dev->board_ptr;
1102         struct comedi_subdevice *s = dev->read_subdev;
1103         int n;
1104 
1105         n = board->ai_fifo_depth / 2;
1106 
1107         ni_ai_fifo_read(dev, s, n);
1108 }
1109 #endif
1110 
1111 /* Empties the AI fifo */
1112 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1113 {
1114         struct ni_private *devpriv = dev->private;
1115         struct comedi_subdevice *s = dev->read_subdev;
1116         unsigned int dl;
1117         unsigned short data;
1118         int i;
1119 
1120         if (devpriv->is_611x) {
1121                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1122                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1123                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1124 
1125                         /* This may get the hi/lo data in the wrong order */
1126                         data = dl >> 16;
1127                         comedi_buf_write_samples(s, &data, 1);
1128                         data = dl & 0xffff;
1129                         comedi_buf_write_samples(s, &data, 1);
1130                 }
1131         } else if (devpriv->is_6143) {
1132                 i = 0;
1133                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1134                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1135 
1136                         /* This may get the hi/lo data in the wrong order */
1137                         data = dl >> 16;
1138                         comedi_buf_write_samples(s, &data, 1);
1139                         data = dl & 0xffff;
1140                         comedi_buf_write_samples(s, &data, 1);
1141                         i += 2;
1142                 }
1143                 /*  Check if stranded sample is present */
1144                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1145                         /* Get stranded sample into FIFO */
1146                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1147                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1148                         data = (dl >> 16) & 0xffff;
1149                         comedi_buf_write_samples(s, &data, 1);
1150                 }
1151 
1152         } else {
1153                 unsigned short fe;      /* fifo empty */
1154 
1155                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1156                      NISTC_AI_STATUS1_FIFO_E;
1157                 while (fe == 0) {
1158                         for (i = 0;
1159                              i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1160                                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1161                                      NISTC_AI_STATUS1_FIFO_E;
1162                                 if (fe)
1163                                         break;
1164                                 devpriv->ai_fifo_buffer[i] =
1165                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1166                         }
1167                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1168                 }
1169         }
1170 }
1171 
1172 static void get_last_sample_611x(struct comedi_device *dev)
1173 {
1174         struct ni_private *devpriv = dev->private;
1175         struct comedi_subdevice *s = dev->read_subdev;
1176         unsigned short data;
1177         unsigned int dl;
1178 
1179         if (!devpriv->is_611x)
1180                 return;
1181 
1182         /* Check if there's a single sample stuck in the FIFO */
1183         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1184                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1185                 data = dl & 0xffff;
1186                 comedi_buf_write_samples(s, &data, 1);
1187         }
1188 }
1189 
1190 static void get_last_sample_6143(struct comedi_device *dev)
1191 {
1192         struct ni_private *devpriv = dev->private;
1193         struct comedi_subdevice *s = dev->read_subdev;
1194         unsigned short data;
1195         unsigned int dl;
1196 
1197         if (!devpriv->is_6143)
1198                 return;
1199 
1200         /* Check if there's a single sample stuck in the FIFO */
1201         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1202                 /* Get stranded sample into FIFO */
1203                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1204                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1205 
1206                 /* This may get the hi/lo data in the wrong order */
1207                 data = (dl >> 16) & 0xffff;
1208                 comedi_buf_write_samples(s, &data, 1);
1209         }
1210 }
1211 
1212 static void shutdown_ai_command(struct comedi_device *dev)
1213 {
1214         struct comedi_subdevice *s = dev->read_subdev;
1215 
1216 #ifdef PCIDMA
1217         ni_ai_drain_dma(dev);
1218 #endif
1219         ni_handle_fifo_dregs(dev);
1220         get_last_sample_611x(dev);
1221         get_last_sample_6143(dev);
1222 
1223         s->async->events |= COMEDI_CB_EOA;
1224 }
1225 
1226 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1227 {
1228         struct ni_private *devpriv = dev->private;
1229 
1230         if (devpriv->aimode == AIMODE_SCAN) {
1231 #ifdef PCIDMA
1232                 static const int timeout = 10;
1233                 int i;
1234 
1235                 for (i = 0; i < timeout; i++) {
1236                         ni_sync_ai_dma(dev);
1237                         if ((s->async->events & COMEDI_CB_EOS))
1238                                 break;
1239                         udelay(1);
1240                 }
1241 #else
1242                 ni_handle_fifo_dregs(dev);
1243                 s->async->events |= COMEDI_CB_EOS;
1244 #endif
1245         }
1246         /* handle special case of single scan */
1247         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1248                 shutdown_ai_command(dev);
1249 }
1250 
1251 static void handle_gpct_interrupt(struct comedi_device *dev,
1252                                   unsigned short counter_index)
1253 {
1254 #ifdef PCIDMA
1255         struct ni_private *devpriv = dev->private;
1256         struct comedi_subdevice *s;
1257 
1258         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1259 
1260         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1261                                 s);
1262         comedi_handle_events(dev, s);
1263 #endif
1264 }
1265 
1266 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1267 {
1268         unsigned short ack = 0;
1269 
1270         if (a_status & NISTC_AI_STATUS1_SC_TC)
1271                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1272         if (a_status & NISTC_AI_STATUS1_START1)
1273                 ack |= NISTC_INTA_ACK_AI_START1;
1274         if (a_status & NISTC_AI_STATUS1_START)
1275                 ack |= NISTC_INTA_ACK_AI_START;
1276         if (a_status & NISTC_AI_STATUS1_STOP)
1277                 ack |= NISTC_INTA_ACK_AI_STOP;
1278         if (a_status & NISTC_AI_STATUS1_OVER)
1279                 ack |= NISTC_INTA_ACK_AI_ERR;
1280         if (ack)
1281                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1282 }
1283 
1284 static void handle_a_interrupt(struct comedi_device *dev,
1285                                struct comedi_subdevice *s,
1286                                unsigned short status)
1287 {
1288         struct comedi_cmd *cmd = &s->async->cmd;
1289 
1290         /* test for all uncommon interrupt events at the same time */
1291         if (status & (NISTC_AI_STATUS1_ERR |
1292                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1293                 if (status == 0xffff) {
1294                         dev_err(dev->class_dev, "Card removed?\n");
1295                         /*
1296                          * We probably aren't even running a command now,
1297                          * so it's a good idea to be careful.
1298                          */
1299                         if (comedi_is_subdevice_running(s))
1300                                 s->async->events |= COMEDI_CB_ERROR;
1301                         return;
1302                 }
1303                 if (status & NISTC_AI_STATUS1_ERR) {
1304                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1305                                 status);
1306 
1307                         shutdown_ai_command(dev);
1308 
1309                         s->async->events |= COMEDI_CB_ERROR;
1310                         if (status & NISTC_AI_STATUS1_OVER)
1311                                 s->async->events |= COMEDI_CB_OVERFLOW;
1312                         return;
1313                 }
1314                 if (status & NISTC_AI_STATUS1_SC_TC) {
1315                         if (cmd->stop_src == TRIG_COUNT)
1316                                 shutdown_ai_command(dev);
1317                 }
1318         }
1319 #ifndef PCIDMA
1320         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1321                 int i;
1322                 static const int timeout = 10;
1323                 /*
1324                  * PCMCIA cards (at least 6036) seem to stop producing
1325                  * interrupts if we fail to get the fifo less than half
1326                  * full, so loop to be sure.
1327                  */
1328                 for (i = 0; i < timeout; ++i) {
1329                         ni_handle_fifo_half_full(dev);
1330                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1331                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1332                                 break;
1333                 }
1334         }
1335 #endif /*  !PCIDMA */
1336 
1337         if (status & NISTC_AI_STATUS1_STOP)
1338                 ni_handle_eos(dev, s);
1339 }
1340 
1341 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1342 {
1343         unsigned short ack = 0;
1344 
1345         if (b_status & NISTC_AO_STATUS1_BC_TC)
1346                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1347         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1348                 ack |= NISTC_INTB_ACK_AO_ERR;
1349         if (b_status & NISTC_AO_STATUS1_START)
1350                 ack |= NISTC_INTB_ACK_AO_START;
1351         if (b_status & NISTC_AO_STATUS1_START1)
1352                 ack |= NISTC_INTB_ACK_AO_START1;
1353         if (b_status & NISTC_AO_STATUS1_UC_TC)
1354                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1355         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1356                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1357         if (b_status & NISTC_AO_STATUS1_UPDATE)
1358                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1359         if (ack)
1360                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1361 }
1362 
1363 static void handle_b_interrupt(struct comedi_device *dev,
1364                                struct comedi_subdevice *s,
1365                                unsigned short b_status)
1366 {
1367         if (b_status == 0xffff)
1368                 return;
1369         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1370                 dev_err(dev->class_dev,
1371                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1372                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1373                 s->async->events |= COMEDI_CB_OVERFLOW;
1374         }
1375 
1376         if (s->async->cmd.stop_src != TRIG_NONE &&
1377             b_status & NISTC_AO_STATUS1_BC_TC)
1378                 s->async->events |= COMEDI_CB_EOA;
1379 
1380 #ifndef PCIDMA
1381         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1382                 int ret;
1383 
1384                 ret = ni_ao_fifo_half_empty(dev, s);
1385                 if (!ret) {
1386                         dev_err(dev->class_dev, "AO buffer underrun\n");
1387                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1388                                     NISTC_INTB_ENA_AO_FIFO |
1389                                     NISTC_INTB_ENA_AO_ERR, 0);
1390                         s->async->events |= COMEDI_CB_OVERFLOW;
1391                 }
1392         }
1393 #endif
1394 }
1395 
1396 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1397                         void *data, unsigned int num_bytes,
1398                         unsigned int chan_index)
1399 {
1400         struct ni_private *devpriv = dev->private;
1401         struct comedi_async *async = s->async;
1402         struct comedi_cmd *cmd = &async->cmd;
1403         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1404         unsigned short *array = data;
1405         unsigned int *larray = data;
1406         unsigned int i;
1407 #ifdef PCIDMA
1408         __le16 *barray = data;
1409         __le32 *blarray = data;
1410 #endif
1411 
1412         for (i = 0; i < nsamples; i++) {
1413 #ifdef PCIDMA
1414                 if (s->subdev_flags & SDF_LSAMPL)
1415                         larray[i] = le32_to_cpu(blarray[i]);
1416                 else
1417                         array[i] = le16_to_cpu(barray[i]);
1418 #endif
1419                 if (s->subdev_flags & SDF_LSAMPL)
1420                         larray[i] += devpriv->ai_offset[chan_index];
1421                 else
1422                         array[i] += devpriv->ai_offset[chan_index];
1423                 chan_index++;
1424                 chan_index %= cmd->chanlist_len;
1425         }
1426 }
1427 
1428 #ifdef PCIDMA
1429 
1430 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1431 {
1432         struct ni_private *devpriv = dev->private;
1433         struct comedi_subdevice *s = dev->read_subdev;
1434         int retval;
1435         unsigned long flags;
1436 
1437         retval = ni_request_ai_mite_channel(dev);
1438         if (retval)
1439                 return retval;
1440 
1441         /* write alloc the entire buffer */
1442         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1443 
1444         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1445         if (!devpriv->ai_mite_chan) {
1446                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1447                 return -EIO;
1448         }
1449 
1450         if (devpriv->is_611x || devpriv->is_6143)
1451                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1452         else if (devpriv->is_628x)
1453                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1454         else
1455                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1456 
1457         /*start the MITE */
1458         mite_dma_arm(devpriv->ai_mite_chan);
1459         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1460 
1461         return 0;
1462 }
1463 
1464 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1465 {
1466         struct ni_private *devpriv = dev->private;
1467         struct comedi_subdevice *s = dev->write_subdev;
1468         int retval;
1469         unsigned long flags;
1470 
1471         retval = ni_request_ao_mite_channel(dev);
1472         if (retval)
1473                 return retval;
1474 
1475         /* read alloc the entire buffer */
1476         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1477 
1478         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1479         if (devpriv->ao_mite_chan) {
1480                 if (devpriv->is_611x || devpriv->is_6713) {
1481                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1482                 } else {
1483                         /*
1484                          * Doing 32 instead of 16 bit wide transfers from
1485                          * memory makes the mite do 32 bit pci transfers,
1486                          * doubling pci bandwidth.
1487                          */
1488                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1489                 }
1490                 mite_dma_arm(devpriv->ao_mite_chan);
1491         } else {
1492                 retval = -EIO;
1493         }
1494         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1495 
1496         return retval;
1497 }
1498 
1499 #endif /*  PCIDMA */
1500 
1501 /*
1502  * used for both cancel ioctl and board initialization
1503  *
1504  * this is pretty harsh for a cancel, but it works...
1505  */
1506 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1507 {
1508         struct ni_private *devpriv = dev->private;
1509         unsigned int ai_personal;
1510         unsigned int ai_out_ctrl;
1511 
1512         ni_release_ai_mite_channel(dev);
1513         /* ai configuration */
1514         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1515                       NISTC_RESET_REG);
1516 
1517         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1518 
1519         ni_clear_ai_fifo(dev);
1520 
1521         if (!devpriv->is_6143)
1522                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1523 
1524         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1525         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1526                            NISTC_AI_MODE1_RSVD
1527                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1528                       NISTC_AI_MODE1_REG);
1529         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1530         /* generate FIFO interrupts on non-empty */
1531         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1532                       NISTC_AI_MODE3_REG);
1533 
1534         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1535                       NISTC_AI_PERSONAL_SOC_POLARITY |
1536                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1537         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1538                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1539                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1540                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1541         if (devpriv->is_611x) {
1542                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1543         } else if (devpriv->is_6143) {
1544                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1545         } else {
1546                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1547                 if (devpriv->is_622x)
1548                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1549                 else
1550                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1551         }
1552         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1553         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1554 
1555         /* the following registers should not be changed, because there
1556          * are no backup registers in devpriv.  If you want to change
1557          * any of these, add a backup register and other appropriate code:
1558          *      NISTC_AI_MODE1_REG
1559          *      NISTC_AI_MODE3_REG
1560          *      NISTC_AI_PERSONAL_REG
1561          *      NISTC_AI_OUT_CTRL_REG
1562          */
1563 
1564         /* clear interrupts */
1565         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1566 
1567         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1568 
1569         return 0;
1570 }
1571 
1572 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1573 {
1574         unsigned long flags;
1575         int count;
1576 
1577         /*  lock to avoid race with interrupt handler */
1578         spin_lock_irqsave(&dev->spinlock, flags);
1579 #ifndef PCIDMA
1580         ni_handle_fifo_dregs(dev);
1581 #else
1582         ni_sync_ai_dma(dev);
1583 #endif
1584         count = comedi_buf_n_bytes_ready(s);
1585         spin_unlock_irqrestore(&dev->spinlock, flags);
1586 
1587         return count;
1588 }
1589 
1590 static void ni_prime_channelgain_list(struct comedi_device *dev)
1591 {
1592         int i;
1593 
1594         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1595         for (i = 0; i < NI_TIMEOUT; ++i) {
1596                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1597                       NISTC_AI_STATUS1_FIFO_E)) {
1598                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1599                         return;
1600                 }
1601                 udelay(1);
1602         }
1603         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1604 }
1605 
1606 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1607                                               unsigned int n_chan,
1608                                               unsigned int *list)
1609 {
1610         const struct ni_board_struct *board = dev->board_ptr;
1611         struct ni_private *devpriv = dev->private;
1612         unsigned int chan, range, aref;
1613         unsigned int i;
1614         unsigned int dither;
1615         unsigned int range_code;
1616 
1617         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1618 
1619         if ((list[0] & CR_ALT_SOURCE)) {
1620                 unsigned int bypass_bits;
1621 
1622                 chan = CR_CHAN(list[0]);
1623                 range = CR_RANGE(list[0]);
1624                 range_code = ni_gainlkup[board->gainlkup][range];
1625                 dither = (list[0] & CR_ALT_FILTER) != 0;
1626                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1627                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1628                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1629                               devpriv->ai_calib_source;
1630                 if (dither)
1631                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1632                 /*  don't use 2's complement encoding */
1633                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1634                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1635         } else {
1636                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1637         }
1638         for (i = 0; i < n_chan; i++) {
1639                 unsigned int config_bits = 0;
1640 
1641                 chan = CR_CHAN(list[i]);
1642                 aref = CR_AREF(list[i]);
1643                 range = CR_RANGE(list[i]);
1644                 dither = (list[i] & CR_ALT_FILTER) != 0;
1645 
1646                 range_code = ni_gainlkup[board->gainlkup][range];
1647                 devpriv->ai_offset[i] = 0;
1648                 switch (aref) {
1649                 case AREF_DIFF:
1650                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1651                         break;
1652                 case AREF_COMMON:
1653                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1654                         break;
1655                 case AREF_GROUND:
1656                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1657                         break;
1658                 case AREF_OTHER:
1659                         break;
1660                 }
1661                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1662                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1663                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1664                 if (i == n_chan - 1)
1665                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1666                 if (dither)
1667                         config_bits |= NI_M_AI_CFG_DITHER;
1668                 /*  don't use 2's complement encoding */
1669                 config_bits |= NI_M_AI_CFG_POLARITY;
1670                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1671         }
1672         ni_prime_channelgain_list(dev);
1673 }
1674 
1675 /*
1676  * Notes on the 6110 and 6111:
1677  * These boards a slightly different than the rest of the series, since
1678  * they have multiple A/D converters.
1679  * From the driver side, the configuration memory is a
1680  * little different.
1681  * Configuration Memory Low:
1682  *   bits 15-9: same
1683  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1684  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1685  *       1001 gain=0.1 (+/- 50)
1686  *       1010 0.2
1687  *       1011 0.1
1688  *       0001 1
1689  *       0010 2
1690  *       0011 5
1691  *       0100 10
1692  *       0101 20
1693  *       0110 50
1694  * Configuration Memory High:
1695  *   bits 12-14: Channel Type
1696  *       001 for differential
1697  *       000 for calibration
1698  *   bit 11: coupling  (this is not currently handled)
1699  *       1 AC coupling
1700  *       0 DC coupling
1701  *   bits 0-2: channel
1702  *       valid channels are 0-3
1703  */
1704 static void ni_load_channelgain_list(struct comedi_device *dev,
1705                                      struct comedi_subdevice *s,
1706                                      unsigned int n_chan, unsigned int *list)
1707 {
1708         const struct ni_board_struct *board = dev->board_ptr;
1709         struct ni_private *devpriv = dev->private;
1710         unsigned int offset = (s->maxdata + 1) >> 1;
1711         unsigned int chan, range, aref;
1712         unsigned int i;
1713         unsigned int hi, lo;
1714         unsigned int dither;
1715 
1716         if (devpriv->is_m_series) {
1717                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1718                 return;
1719         }
1720         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1721                 if (devpriv->changain_state &&
1722                     devpriv->changain_spec == list[0]) {
1723                         /*  ready to go. */
1724                         return;
1725                 }
1726                 devpriv->changain_state = 1;
1727                 devpriv->changain_spec = list[0];
1728         } else {
1729                 devpriv->changain_state = 0;
1730         }
1731 
1732         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1733 
1734         /*  Set up Calibration mode if required */
1735         if (devpriv->is_6143) {
1736                 if ((list[0] & CR_ALT_SOURCE) &&
1737                     !devpriv->ai_calib_source_enabled) {
1738                         /*  Strobe Relay enable bit */
1739                         ni_writew(dev, devpriv->ai_calib_source |
1740                                        NI6143_CALIB_CHAN_RELAY_ON,
1741                                   NI6143_CALIB_CHAN_REG);
1742                         ni_writew(dev, devpriv->ai_calib_source,
1743                                   NI6143_CALIB_CHAN_REG);
1744                         devpriv->ai_calib_source_enabled = 1;
1745                         /* Allow relays to change */
1746                         msleep_interruptible(100);
1747                 } else if (!(list[0] & CR_ALT_SOURCE) &&
1748                            devpriv->ai_calib_source_enabled) {
1749                         /*  Strobe Relay disable bit */
1750                         ni_writew(dev, devpriv->ai_calib_source |
1751                                        NI6143_CALIB_CHAN_RELAY_OFF,
1752                                   NI6143_CALIB_CHAN_REG);
1753                         ni_writew(dev, devpriv->ai_calib_source,
1754                                   NI6143_CALIB_CHAN_REG);
1755                         devpriv->ai_calib_source_enabled = 0;
1756                         /* Allow relays to change */
1757                         msleep_interruptible(100);
1758                 }
1759         }
1760 
1761         for (i = 0; i < n_chan; i++) {
1762                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1763                         chan = devpriv->ai_calib_source;
1764                 else
1765                         chan = CR_CHAN(list[i]);
1766                 aref = CR_AREF(list[i]);
1767                 range = CR_RANGE(list[i]);
1768                 dither = (list[i] & CR_ALT_FILTER) != 0;
1769 
1770                 /* fix the external/internal range differences */
1771                 range = ni_gainlkup[board->gainlkup][range];
1772                 if (devpriv->is_611x)
1773                         devpriv->ai_offset[i] = offset;
1774                 else
1775                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1776 
1777                 hi = 0;
1778                 if ((list[i] & CR_ALT_SOURCE)) {
1779                         if (devpriv->is_611x)
1780                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1781                                           NI611X_CALIB_CHAN_SEL_REG);
1782                 } else {
1783                         if (devpriv->is_611x)
1784                                 aref = AREF_DIFF;
1785                         else if (devpriv->is_6143)
1786                                 aref = AREF_OTHER;
1787                         switch (aref) {
1788                         case AREF_DIFF:
1789                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1790                                 break;
1791                         case AREF_COMMON:
1792                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1793                                 break;
1794                         case AREF_GROUND:
1795                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1796                                 break;
1797                         case AREF_OTHER:
1798                                 break;
1799                         }
1800                 }
1801                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1802 
1803                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1804 
1805                 if (!devpriv->is_6143) {
1806                         lo = NI_E_AI_CFG_LO_GAIN(range);
1807 
1808                         if (i == n_chan - 1)
1809                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1810                         if (dither)
1811                                 lo |= NI_E_AI_CFG_LO_DITHER;
1812 
1813                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1814                 }
1815         }
1816 
1817         /* prime the channel/gain list */
1818         if (!devpriv->is_611x && !devpriv->is_6143)
1819                 ni_prime_channelgain_list(dev);
1820 }
1821 
1822 static int ni_ai_insn_read(struct comedi_device *dev,
1823                            struct comedi_subdevice *s,
1824                            struct comedi_insn *insn,
1825                            unsigned int *data)
1826 {
1827         struct ni_private *devpriv = dev->private;
1828         unsigned int mask = s->maxdata;
1829         int i, n;
1830         unsigned int signbits;
1831         unsigned int d;
1832 
1833         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1834 
1835         ni_clear_ai_fifo(dev);
1836 
1837         signbits = devpriv->ai_offset[0];
1838         if (devpriv->is_611x) {
1839                 for (n = 0; n < num_adc_stages_611x; n++) {
1840                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1841                                       NISTC_AI_CMD1_REG);
1842                         udelay(1);
1843                 }
1844                 for (n = 0; n < insn->n; n++) {
1845                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1846                                       NISTC_AI_CMD1_REG);
1847                         /* The 611x has screwy 32-bit FIFOs. */
1848                         d = 0;
1849                         for (i = 0; i < NI_TIMEOUT; i++) {
1850                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1851                                         d = ni_readl(dev,
1852                                                      NI611X_AI_FIFO_DATA_REG);
1853                                         d >>= 16;
1854                                         d &= 0xffff;
1855                                         break;
1856                                 }
1857                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1858                                       NISTC_AI_STATUS1_FIFO_E)) {
1859                                         d = ni_readl(dev,
1860                                                      NI611X_AI_FIFO_DATA_REG);
1861                                         d &= 0xffff;
1862                                         break;
1863                                 }
1864                         }
1865                         if (i == NI_TIMEOUT) {
1866                                 dev_err(dev->class_dev, "timeout\n");
1867                                 return -ETIME;
1868                         }
1869                         d += signbits;
1870                         data[n] = d & 0xffff;
1871                 }
1872         } else if (devpriv->is_6143) {
1873                 for (n = 0; n < insn->n; n++) {
1874                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1875                                       NISTC_AI_CMD1_REG);
1876 
1877                         /*
1878                          * The 6143 has 32-bit FIFOs. You need to strobe a
1879                          * bit to move a single 16bit stranded sample into
1880                          * the FIFO.
1881                          */
1882                         d = 0;
1883                         for (i = 0; i < NI_TIMEOUT; i++) {
1884                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1885                                     0x01) {
1886                                         /* Get stranded sample into FIFO */
1887                                         ni_writel(dev, 0x01,
1888                                                   NI6143_AI_FIFO_CTRL_REG);
1889                                         d = ni_readl(dev,
1890                                                      NI6143_AI_FIFO_DATA_REG);
1891                                         break;
1892                                 }
1893                         }
1894                         if (i == NI_TIMEOUT) {
1895                                 dev_err(dev->class_dev, "timeout\n");
1896                                 return -ETIME;
1897                         }
1898                         data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1899                 }
1900         } else {
1901                 for (n = 0; n < insn->n; n++) {
1902                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1903                                       NISTC_AI_CMD1_REG);
1904                         for (i = 0; i < NI_TIMEOUT; i++) {
1905                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1906                                       NISTC_AI_STATUS1_FIFO_E))
1907                                         break;
1908                         }
1909                         if (i == NI_TIMEOUT) {
1910                                 dev_err(dev->class_dev, "timeout\n");
1911                                 return -ETIME;
1912                         }
1913                         if (devpriv->is_m_series) {
1914                                 d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1915                                 d &= mask;
1916                                 data[n] = d;
1917                         } else {
1918                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1919                                 d += signbits;
1920                                 data[n] = d & 0xffff;
1921                         }
1922                 }
1923         }
1924         return insn->n;
1925 }
1926 
1927 static int ni_ns_to_timer(const struct comedi_device *dev,
1928                           unsigned int nanosec, unsigned int flags)
1929 {
1930         struct ni_private *devpriv = dev->private;
1931         int divider;
1932 
1933         switch (flags & CMDF_ROUND_MASK) {
1934         case CMDF_ROUND_NEAREST:
1935         default:
1936                 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1937                 break;
1938         case CMDF_ROUND_DOWN:
1939                 divider = (nanosec) / devpriv->clock_ns;
1940                 break;
1941         case CMDF_ROUND_UP:
1942                 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1943                 break;
1944         }
1945         return divider - 1;
1946 }
1947 
1948 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1949 {
1950         struct ni_private *devpriv = dev->private;
1951 
1952         return devpriv->clock_ns * (timer + 1);
1953 }
1954 
1955 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1956                                      struct comedi_subdevice *sdev,
1957                                      const struct comedi_cmd *cmd,
1958                                      unsigned int max_count)
1959 {
1960 #ifdef PCIDMA
1961         unsigned int nbytes = max_count;
1962 
1963         if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1964                 nbytes = cmd->stop_arg;
1965         nbytes *= comedi_bytes_per_scan(sdev);
1966 
1967         if (nbytes > sdev->async->prealloc_bufsz) {
1968                 if (cmd->stop_arg > 0)
1969                         dev_err(sdev->device->class_dev,
1970                                 "%s: tried exact data transfer limits greater than buffer size\n",
1971                                 __func__);
1972 
1973                 /*
1974                  * we can only transfer up to the size of the buffer.  In this
1975                  * case, the user is expected to continue to write into the
1976                  * comedi buffer (already implemented as a ring buffer).
1977                  */
1978                 nbytes = sdev->async->prealloc_bufsz;
1979         }
1980 
1981         mite_init_ring_descriptors(ring, sdev, nbytes);
1982 #else
1983         dev_err(sdev->device->class_dev,
1984                 "%s: exact data transfer limits not implemented yet without DMA\n",
1985                 __func__);
1986 #endif
1987 }
1988 
1989 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1990                                              unsigned int num_channels)
1991 {
1992         const struct ni_board_struct *board = dev->board_ptr;
1993         struct ni_private *devpriv = dev->private;
1994 
1995         /* simultaneously-sampled inputs */
1996         if (devpriv->is_611x || devpriv->is_6143)
1997                 return board->ai_speed;
1998 
1999         /* multiplexed inputs */
2000         return board->ai_speed * num_channels;
2001 }
2002 
2003 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2004                          struct comedi_cmd *cmd)
2005 {
2006         const struct ni_board_struct *board = dev->board_ptr;
2007         struct ni_private *devpriv = dev->private;
2008         int err = 0;
2009         unsigned int sources;
2010 
2011         /* Step 1 : check if triggers are trivially valid */
2012 
2013         err |= comedi_check_trigger_src(&cmd->start_src,
2014                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2015         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2016                                         TRIG_TIMER | TRIG_EXT);
2017 
2018         sources = TRIG_TIMER | TRIG_EXT;
2019         if (devpriv->is_611x || devpriv->is_6143)
2020                 sources |= TRIG_NOW;
2021         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2022 
2023         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2024         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2025 
2026         if (err)
2027                 return 1;
2028 
2029         /* Step 2a : make sure trigger sources are unique */
2030 
2031         err |= comedi_check_trigger_is_unique(cmd->start_src);
2032         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2033         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2034         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2035 
2036         /* Step 2b : and mutually compatible */
2037 
2038         if (err)
2039                 return 2;
2040 
2041         /* Step 3: check if arguments are trivially valid */
2042 
2043         switch (cmd->start_src) {
2044         case TRIG_NOW:
2045         case TRIG_INT:
2046                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2047                 break;
2048         case TRIG_EXT:
2049                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
2050                                                   NI_AI_StartTrigger,
2051                                                   &devpriv->routing_tables, 1);
2052                 break;
2053         }
2054 
2055         if (cmd->scan_begin_src == TRIG_TIMER) {
2056                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2057                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2058                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2059                                                     devpriv->clock_ns *
2060                                                     0xffffff);
2061         } else if (cmd->scan_begin_src == TRIG_EXT) {
2062                 /* external trigger */
2063                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->scan_begin_arg),
2064                                                   NI_AI_SampleClock,
2065                                                   &devpriv->routing_tables, 1);
2066         } else {                /* TRIG_OTHER */
2067                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2068         }
2069 
2070         if (cmd->convert_src == TRIG_TIMER) {
2071                 if (devpriv->is_611x || devpriv->is_6143) {
2072                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2073                                                            0);
2074                 } else {
2075                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2076                                                             board->ai_speed);
2077                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2078                                                             devpriv->clock_ns *
2079                                                             0xffff);
2080                 }
2081         } else if (cmd->convert_src == TRIG_EXT) {
2082                 /* external trigger */
2083                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->convert_arg),
2084                                                   NI_AI_ConvertClock,
2085                                                   &devpriv->routing_tables, 1);
2086         } else if (cmd->convert_src == TRIG_NOW) {
2087                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2088         }
2089 
2090         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2091                                            cmd->chanlist_len);
2092 
2093         if (cmd->stop_src == TRIG_COUNT) {
2094                 unsigned int max_count = 0x01000000;
2095 
2096                 if (devpriv->is_611x)
2097                         max_count -= num_adc_stages_611x;
2098                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2099                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2100         } else {
2101                 /* TRIG_NONE */
2102                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2103         }
2104 
2105         if (err)
2106                 return 3;
2107 
2108         /* step 4: fix up any arguments */
2109 
2110         if (cmd->scan_begin_src == TRIG_TIMER) {
2111                 unsigned int tmp = cmd->scan_begin_arg;
2112 
2113                 cmd->scan_begin_arg =
2114                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2115                                                        cmd->scan_begin_arg,
2116                                                        cmd->flags));
2117                 if (tmp != cmd->scan_begin_arg)
2118                         err++;
2119         }
2120         if (cmd->convert_src == TRIG_TIMER) {
2121                 if (!devpriv->is_611x && !devpriv->is_6143) {
2122                         unsigned int tmp = cmd->convert_arg;
2123 
2124                         cmd->convert_arg =
2125                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2126                                                                cmd->convert_arg,
2127                                                                cmd->flags));
2128                         if (tmp != cmd->convert_arg)
2129                                 err++;
2130                         if (cmd->scan_begin_src == TRIG_TIMER &&
2131                             cmd->scan_begin_arg <
2132                             cmd->convert_arg * cmd->scan_end_arg) {
2133                                 cmd->scan_begin_arg =
2134                                     cmd->convert_arg * cmd->scan_end_arg;
2135                                 err++;
2136                         }
2137                 }
2138         }
2139 
2140         if (err)
2141                 return 4;
2142 
2143         return 0;
2144 }
2145 
2146 static int ni_ai_inttrig(struct comedi_device *dev,
2147                          struct comedi_subdevice *s,
2148                          unsigned int trig_num)
2149 {
2150         struct ni_private *devpriv = dev->private;
2151         struct comedi_cmd *cmd = &s->async->cmd;
2152 
2153         if (trig_num != cmd->start_arg)
2154                 return -EINVAL;
2155 
2156         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2157                       NISTC_AI_CMD2_REG);
2158         s->async->inttrig = NULL;
2159 
2160         return 1;
2161 }
2162 
2163 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2164 {
2165         struct ni_private *devpriv = dev->private;
2166         const struct comedi_cmd *cmd = &s->async->cmd;
2167         int timer;
2168         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2169         int mode2 = 0;
2170         int start_stop_select = 0;
2171         unsigned int stop_count;
2172         int interrupt_a_enable = 0;
2173         unsigned int ai_trig;
2174 
2175         if (dev->irq == 0) {
2176                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2177                 return -EIO;
2178         }
2179         ni_clear_ai_fifo(dev);
2180 
2181         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2182 
2183         /* start configuration */
2184         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2185 
2186         /*
2187          * Disable analog triggering for now, since it interferes
2188          * with the use of pfi0.
2189          */
2190         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2191         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2192 
2193         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2194         switch (cmd->start_src) {
2195         case TRIG_INT:
2196         case TRIG_NOW:
2197                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2198                            NISTC_AI_TRIG_START1_SEL(0);
2199                 break;
2200         case TRIG_EXT:
2201                 ai_trig |= NISTC_AI_TRIG_START1_SEL(
2202                         ni_get_reg_value_roffs(CR_CHAN(cmd->start_arg),
2203                                                NI_AI_StartTrigger,
2204                                                &devpriv->routing_tables, 1));
2205 
2206                 if (cmd->start_arg & CR_INVERT)
2207                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2208                 if (cmd->start_arg & CR_EDGE)
2209                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2210                 break;
2211         }
2212         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2213 
2214         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2215         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2216         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2217         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2218 
2219         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2220                 /* logic low */
2221                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2222                                      NISTC_AI_STOP_SEL(31) |
2223                                      NISTC_AI_STOP_SYNC;
2224         } else {
2225                 /*  ai configuration memory */
2226                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2227         }
2228         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2229 
2230         devpriv->ai_cmd2 = 0;
2231         switch (cmd->stop_src) {
2232         case TRIG_COUNT:
2233                 stop_count = cmd->stop_arg - 1;
2234 
2235                 if (devpriv->is_611x) {
2236                         /*  have to take 3 stage adc pipeline into account */
2237                         stop_count += num_adc_stages_611x;
2238                 }
2239                 /* stage number of scans */
2240                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2241 
2242                 mode1 |= NISTC_AI_MODE1_START_STOP |
2243                          NISTC_AI_MODE1_RSVD |
2244                          NISTC_AI_MODE1_TRIGGER_ONCE;
2245                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2246                 /* load SC (Scan Count) */
2247                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2248 
2249                 if (stop_count == 0) {
2250                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2251                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2252                         /*
2253                          * This is required to get the last sample for
2254                          * chanlist_len > 1, not sure why.
2255                          */
2256                         if (cmd->chanlist_len > 1)
2257                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2258                                                      NISTC_AI_STOP_EDGE;
2259                 }
2260                 break;
2261         case TRIG_NONE:
2262                 /* stage number of scans */
2263                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2264 
2265                 mode1 |= NISTC_AI_MODE1_START_STOP |
2266                          NISTC_AI_MODE1_RSVD |
2267                          NISTC_AI_MODE1_CONTINUOUS;
2268                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2269 
2270                 /* load SC (Scan Count) */
2271                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2272                 break;
2273         }
2274 
2275         switch (cmd->scan_begin_src) {
2276         case TRIG_TIMER:
2277                 /*
2278                  * stop bits for non 611x boards
2279                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2280                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2281                  * NISTC_AI_START_STOP_REG:
2282                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2283                  * NISTC_AI_START_EDGE=1        edge triggered
2284                  * NISTC_AI_START_SYNC=1        (?)
2285                  * NISTC_AI_START_SEL=0         SI_TC
2286                  * NISTC_AI_STOP_POLARITY=0     rising edge
2287                  * NISTC_AI_STOP_EDGE=0         level
2288                  * NISTC_AI_STOP_SYNC=1
2289                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2290                  */
2291                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2292                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2293 
2294                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2295                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2296                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2297                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2298 
2299                 /* load SI */
2300                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2301                                        CMDF_ROUND_NEAREST);
2302                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2303                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2304                 break;
2305         case TRIG_EXT:
2306                 if (cmd->scan_begin_arg & CR_EDGE)
2307                         start_stop_select |= NISTC_AI_START_EDGE;
2308                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2309                         start_stop_select |= NISTC_AI_START_POLARITY;
2310                 if (cmd->scan_begin_src != cmd->convert_src ||
2311                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2312                     (cmd->convert_arg & ~CR_EDGE))
2313                         start_stop_select |= NISTC_AI_START_SYNC;
2314                 start_stop_select |= NISTC_AI_START_SEL(
2315                         ni_get_reg_value_roffs(CR_CHAN(cmd->scan_begin_arg),
2316                                                NI_AI_SampleClock,
2317                                                &devpriv->routing_tables, 1));
2318                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2319                 break;
2320         }
2321 
2322         switch (cmd->convert_src) {
2323         case TRIG_TIMER:
2324         case TRIG_NOW:
2325                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2326                         timer = 1;
2327                 else
2328                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2329                                                CMDF_ROUND_NEAREST);
2330                 /* 0,0 does not work */
2331                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2332                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2333 
2334                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2335                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2336                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2337 
2338                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2339 
2340                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2341                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2342                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2343                 break;
2344         case TRIG_EXT:
2345                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(
2346                         ni_get_reg_value_roffs(CR_CHAN(cmd->convert_arg),
2347                                                NI_AI_ConvertClock,
2348                                                &devpriv->routing_tables, 1));
2349                 if ((cmd->convert_arg & CR_INVERT) == 0)
2350                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2351                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2352 
2353                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2354                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2355                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2356 
2357                 break;
2358         }
2359 
2360         if (dev->irq) {
2361                 /* interrupt on FIFO, errors, SC_TC */
2362                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2363                                       NISTC_INTA_ENA_AI_SC_TC;
2364 
2365 #ifndef PCIDMA
2366                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2367 #endif
2368 
2369                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2370                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2371                         /* wake on end-of-scan */
2372                         devpriv->aimode = AIMODE_SCAN;
2373                 } else {
2374                         devpriv->aimode = AIMODE_HALF_FULL;
2375                 }
2376 
2377                 switch (devpriv->aimode) {
2378                 case AIMODE_HALF_FULL:
2379                         /* FIFO interrupts and DMA requests on half-full */
2380 #ifdef PCIDMA
2381                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2382                                       NISTC_AI_MODE3_REG);
2383 #else
2384                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2385                                       NISTC_AI_MODE3_REG);
2386 #endif
2387                         break;
2388                 case AIMODE_SAMPLE:
2389                         /*generate FIFO interrupts on non-empty */
2390                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2391                                       NISTC_AI_MODE3_REG);
2392                         break;
2393                 case AIMODE_SCAN:
2394 #ifdef PCIDMA
2395                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2396                                       NISTC_AI_MODE3_REG);
2397 #else
2398                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2399                                       NISTC_AI_MODE3_REG);
2400 #endif
2401                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2402                         break;
2403                 default:
2404                         break;
2405                 }
2406 
2407                 /* clear interrupts */
2408                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2409 
2410                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2411         } else {
2412                 /* interrupt on nothing */
2413                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2414 
2415                 /* XXX start polling if necessary */
2416         }
2417 
2418         /* end configuration */
2419         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2420 
2421         switch (cmd->scan_begin_src) {
2422         case TRIG_TIMER:
2423                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2424                                    NISTC_AI_CMD1_SI_ARM |
2425                                    NISTC_AI_CMD1_DIV_ARM |
2426                                    NISTC_AI_CMD1_SC_ARM,
2427                               NISTC_AI_CMD1_REG);
2428                 break;
2429         case TRIG_EXT:
2430                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2431                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2432                                    NISTC_AI_CMD1_DIV_ARM |
2433                                    NISTC_AI_CMD1_SC_ARM,
2434                               NISTC_AI_CMD1_REG);
2435                 break;
2436         }
2437 
2438 #ifdef PCIDMA
2439         {
2440                 int retval = ni_ai_setup_MITE_dma(dev);
2441 
2442                 if (retval)
2443                         return retval;
2444         }
2445 #endif
2446 
2447         if (cmd->start_src == TRIG_NOW) {
2448                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2449                                    devpriv->ai_cmd2,
2450                               NISTC_AI_CMD2_REG);
2451                 s->async->inttrig = NULL;
2452         } else if (cmd->start_src == TRIG_EXT) {
2453                 s->async->inttrig = NULL;
2454         } else {        /* TRIG_INT */
2455                 s->async->inttrig = ni_ai_inttrig;
2456         }
2457 
2458         return 0;
2459 }
2460 
2461 static int ni_ai_insn_config(struct comedi_device *dev,
2462                              struct comedi_subdevice *s,
2463                              struct comedi_insn *insn, unsigned int *data)
2464 {
2465         const struct ni_board_struct *board = dev->board_ptr;
2466         struct ni_private *devpriv = dev->private;
2467 
2468         if (insn->n < 1)
2469                 return -EINVAL;
2470 
2471         switch (data[0]) {
2472         case INSN_CONFIG_ALT_SOURCE:
2473                 if (devpriv->is_m_series) {
2474                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2475                                 return -EINVAL;
2476                         devpriv->ai_calib_source = data[1];
2477                 } else if (devpriv->is_6143) {
2478                         unsigned int calib_source;
2479 
2480                         calib_source = data[1] & 0xf;
2481 
2482                         devpriv->ai_calib_source = calib_source;
2483                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2484                 } else {
2485                         unsigned int calib_source;
2486                         unsigned int calib_source_adjust;
2487 
2488                         calib_source = data[1] & 0xf;
2489                         calib_source_adjust = (data[1] >> 4) & 0xff;
2490 
2491                         if (calib_source >= 8)
2492                                 return -EINVAL;
2493                         devpriv->ai_calib_source = calib_source;
2494                         if (devpriv->is_611x) {
2495                                 ni_writeb(dev, calib_source_adjust,
2496                                           NI611X_CAL_GAIN_SEL_REG);
2497                         }
2498                 }
2499                 return 2;
2500         case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2501                 /* we don't care about actual channels */
2502                 /* data[3] : chanlist_len */
2503                 data[1] = ni_min_ai_scan_period_ns(dev, data[3]);
2504                 if (devpriv->is_611x || devpriv->is_6143)
2505                         data[2] = 0; /* simultaneous output */
2506                 else
2507                         data[2] = board->ai_speed;
2508                 return 0;
2509         default:
2510                 break;
2511         }
2512 
2513         return -EINVAL;
2514 }
2515 
2516 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2517                         void *data, unsigned int num_bytes,
2518                         unsigned int chan_index)
2519 {
2520         struct comedi_cmd *cmd = &s->async->cmd;
2521         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2522         unsigned short *array = data;
2523         unsigned int i;
2524 #ifdef PCIDMA
2525         __le16 buf, *barray = data;
2526 #endif
2527 
2528         for (i = 0; i < nsamples; i++) {
2529                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2530                 unsigned short val = array[i];
2531 
2532                 /*
2533                  * Munge data from unsigned to two's complement for
2534                  * bipolar ranges.
2535                  */
2536                 if (comedi_range_is_bipolar(s, range))
2537                         val = comedi_offset_munge(s, val);
2538 #ifdef PCIDMA
2539                 buf = cpu_to_le16(val);
2540                 barray[i] = buf;
2541 #else
2542                 array[i] = val;
2543 #endif
2544                 chan_index++;
2545                 chan_index %= cmd->chanlist_len;
2546         }
2547 }
2548 
2549 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2550                                           struct comedi_subdevice *s,
2551                                           unsigned int chanspec[],
2552                                           unsigned int n_chans, int timed)
2553 {
2554         struct ni_private *devpriv = dev->private;
2555         unsigned int range;
2556         unsigned int chan;
2557         unsigned int conf;
2558         int i;
2559         int invert = 0;
2560 
2561         if (timed) {
2562                 for (i = 0; i < s->n_chan; ++i) {
2563                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2564                         ni_writeb(dev, devpriv->ao_conf[i],
2565                                   NI_M_AO_CFG_BANK_REG(i));
2566                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2567                 }
2568         }
2569         for (i = 0; i < n_chans; i++) {
2570                 const struct comedi_krange *krange;
2571 
2572                 chan = CR_CHAN(chanspec[i]);
2573                 range = CR_RANGE(chanspec[i]);
2574                 krange = s->range_table->range + range;
2575                 invert = 0;
2576                 conf = 0;
2577                 switch (krange->max - krange->min) {
2578                 case 20000000:
2579                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2580                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2581                         break;
2582                 case 10000000:
2583                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2584                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2585                         break;
2586                 case 4000000:
2587                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2588                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2589                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2590                         break;
2591                 case 2000000:
2592                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2593                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2594                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2595                         break;
2596                 default:
2597                         dev_err(dev->class_dev,
2598                                 "bug! unhandled ao reference voltage\n");
2599                         break;
2600                 }
2601                 switch (krange->max + krange->min) {
2602                 case 0:
2603                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2604                         break;
2605                 case 10000000:
2606                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2607                         break;
2608                 default:
2609                         dev_err(dev->class_dev,
2610                                 "bug! unhandled ao offset voltage\n");
2611                         break;
2612                 }
2613                 if (timed)
2614                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2615                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2616                 devpriv->ao_conf[chan] = conf;
2617                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2618         }
2619         return invert;
2620 }
2621 
2622 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2623                                      struct comedi_subdevice *s,
2624                                      unsigned int chanspec[],
2625                                      unsigned int n_chans)
2626 {
2627         struct ni_private *devpriv = dev->private;
2628         unsigned int range;
2629         unsigned int chan;
2630         unsigned int conf;
2631         int i;
2632         int invert = 0;
2633 
2634         for (i = 0; i < n_chans; i++) {
2635                 chan = CR_CHAN(chanspec[i]);
2636                 range = CR_RANGE(chanspec[i]);
2637                 conf = NI_E_AO_DACSEL(chan);
2638 
2639                 if (comedi_range_is_bipolar(s, range)) {
2640                         conf |= NI_E_AO_CFG_BIP;
2641                         invert = (s->maxdata + 1) >> 1;
2642                 } else {
2643                         invert = 0;
2644                 }
2645                 if (comedi_range_is_external(s, range))
2646                         conf |= NI_E_AO_EXT_REF;
2647 
2648                 /* not all boards can deglitch, but this shouldn't hurt */
2649                 if (chanspec[i] & CR_DEGLITCH)
2650                         conf |= NI_E_AO_DEGLITCH;
2651 
2652                 /* analog reference */
2653                 /* AREF_OTHER connects AO ground to AI ground, i think */
2654                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2655                         conf |= NI_E_AO_GROUND_REF;
2656 
2657                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2658                 devpriv->ao_conf[chan] = conf;
2659         }
2660         return invert;
2661 }
2662 
2663 static int ni_ao_config_chanlist(struct comedi_device *dev,
2664                                  struct comedi_subdevice *s,
2665                                  unsigned int chanspec[], unsigned int n_chans,
2666                                  int timed)
2667 {
2668         struct ni_private *devpriv = dev->private;
2669 
2670         if (devpriv->is_m_series)
2671                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2672                                                       timed);
2673         else
2674                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2675 }
2676 
2677 static int ni_ao_insn_write(struct comedi_device *dev,
2678                             struct comedi_subdevice *s,
2679                             struct comedi_insn *insn,
2680                             unsigned int *data)
2681 {
2682         struct ni_private *devpriv = dev->private;
2683         unsigned int chan = CR_CHAN(insn->chanspec);
2684         unsigned int range = CR_RANGE(insn->chanspec);
2685         int reg;
2686         int i;
2687 
2688         if (devpriv->is_6xxx) {
2689                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2690 
2691                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2692         } else if (devpriv->is_m_series) {
2693                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2694         } else {
2695                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2696         }
2697 
2698         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2699 
2700         for (i = 0; i < insn->n; i++) {
2701                 unsigned int val = data[i];
2702 
2703                 s->readback[chan] = val;
2704 
2705                 if (devpriv->is_6xxx) {
2706                         /*
2707                          * 6xxx boards have bipolar outputs, munge the
2708                          * unsigned comedi values to 2's complement
2709                          */
2710                         val = comedi_offset_munge(s, val);
2711 
2712                         ni_ao_win_outw(dev, val, reg);
2713                 } else if (devpriv->is_m_series) {
2714                         /*
2715                          * M-series boards use offset binary values for
2716                          * bipolar and uinpolar outputs
2717                          */
2718                         ni_writew(dev, val, reg);
2719                 } else {
2720                         /*
2721                          * Non-M series boards need two's complement values
2722                          * for bipolar ranges.
2723                          */
2724                         if (comedi_range_is_bipolar(s, range))
2725                                 val = comedi_offset_munge(s, val);
2726 
2727                         ni_writew(dev, val, reg);
2728                 }
2729         }
2730 
2731         return insn->n;
2732 }
2733 
2734 /*
2735  * Arms the AO device in preparation for a trigger event.
2736  * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2737  * not used).  As a part of this preparation, this function preloads the DAC
2738  * registers with the first values of the output stream.  This ensures that the
2739  * first clock cycle after the trigger can be used for output.
2740  *
2741  * Note that this function _must_ happen after a user has written data to the
2742  * output buffers via either mmap or write(fileno,...).
2743  */
2744 static int ni_ao_arm(struct comedi_device *dev,
2745                      struct comedi_subdevice *s)
2746 {
2747         struct ni_private *devpriv = dev->private;
2748         int ret;
2749         int interrupt_b_bits;
2750         int i;
2751         static const int timeout = 1000;
2752 
2753         /*
2754          * Prevent ao from doing things like trying to allocate the ao dma
2755          * channel multiple times.
2756          */
2757         if (!devpriv->ao_needs_arming) {
2758                 dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2759                         __func__);
2760                 return -EINVAL;
2761         }
2762 
2763         devpriv->ao_needs_arming = 0;
2764 
2765         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2766                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2767         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2768 #ifdef PCIDMA
2769         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2770         if (devpriv->is_6xxx)
2771                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2772         ret = ni_ao_setup_MITE_dma(dev);
2773         if (ret)
2774                 return ret;
2775         ret = ni_ao_wait_for_dma_load(dev);
2776         if (ret < 0)
2777                 return ret;
2778 #else
2779         ret = ni_ao_prep_fifo(dev, s);
2780         if (ret == 0)
2781                 return -EPIPE;
2782 
2783         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2784 #endif
2785 
2786         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2787                       NISTC_AO_MODE3_REG);
2788         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2789         /* wait for DACs to be loaded */
2790         for (i = 0; i < timeout; i++) {
2791                 udelay(1);
2792                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2793                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2794                         break;
2795         }
2796         if (i == timeout) {
2797                 dev_err(dev->class_dev,
2798                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2799                 return -EIO;
2800         }
2801         /*
2802          * stc manual says we are need to clear error interrupt after
2803          * AO_TMRDACWRs_In_Progress_St clears
2804          */
2805         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2806 
2807         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2808 
2809         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2810                            NISTC_AO_CMD1_UC_ARM |
2811                            NISTC_AO_CMD1_BC_ARM |
2812                            devpriv->ao_cmd1,
2813                       NISTC_AO_CMD1_REG);
2814 
2815         return 0;
2816 }
2817 
2818 static int ni_ao_insn_config(struct comedi_device *dev,
2819                              struct comedi_subdevice *s,
2820                              struct comedi_insn *insn, unsigned int *data)
2821 {
2822         const struct ni_board_struct *board = dev->board_ptr;
2823         struct ni_private *devpriv = dev->private;
2824         unsigned int nbytes;
2825 
2826         switch (data[0]) {
2827         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2828                 switch (data[1]) {
2829                 case COMEDI_OUTPUT:
2830                         nbytes = comedi_samples_to_bytes(s,
2831                                                          board->ao_fifo_depth);
2832                         data[2] = 1 + nbytes;
2833                         if (devpriv->mite)
2834                                 data[2] += devpriv->mite->fifo_size;
2835                         break;
2836                 case COMEDI_INPUT:
2837                         data[2] = 0;
2838                         break;
2839                 default:
2840                         return -EINVAL;
2841                 }
2842                 return 0;
2843         case INSN_CONFIG_ARM:
2844                 return ni_ao_arm(dev, s);
2845         case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2846                 /* we don't care about actual channels */
2847                 /* data[3] : chanlist_len */
2848                 data[1] = board->ao_speed * data[3];
2849                 data[2] = 0;
2850                 return 0;
2851         default:
2852                 break;
2853         }
2854 
2855         return -EINVAL;
2856 }
2857 
2858 static int ni_ao_inttrig(struct comedi_device *dev,
2859                          struct comedi_subdevice *s,
2860                          unsigned int trig_num)
2861 {
2862         struct ni_private *devpriv = dev->private;
2863         struct comedi_cmd *cmd = &s->async->cmd;
2864         int ret;
2865 
2866         /*
2867          * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2868          * For backwards compatibility, also allow trig_num == 0 when
2869          * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2870          * in that case, the internal trigger is being used as a pre-trigger
2871          * before the external trigger.
2872          */
2873         if (!(trig_num == cmd->start_arg ||
2874               (trig_num == 0 && cmd->start_src != TRIG_INT)))
2875                 return -EINVAL;
2876 
2877         /*
2878          * Null trig at beginning prevent ao start trigger from executing more
2879          * than once per command.
2880          */
2881         s->async->inttrig = NULL;
2882 
2883         if (devpriv->ao_needs_arming) {
2884                 /* only arm this device if it still needs arming */
2885                 ret = ni_ao_arm(dev, s);
2886                 if (ret)
2887                         return ret;
2888         }
2889 
2890         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2891                       NISTC_AO_CMD2_REG);
2892 
2893         return 0;
2894 }
2895 
2896 /*
2897  * begin ni_ao_cmd.
2898  * Organized similar to NI-STC and MHDDK examples.
2899  * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2900  */
2901 
2902 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2903                                   const struct comedi_cmd *cmd)
2904 {
2905         const struct ni_board_struct *board = dev->board_ptr;
2906         unsigned int bits;
2907 
2908         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2909 
2910         bits =
2911           /* fast CPU interface--only eseries */
2912           /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2913           NISTC_AO_PERSONAL_BC_SRC_SEL  |
2914           0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2915           /*
2916            * FIXME:  start setting following bit when appropriate.  Need to
2917            * determine whether board is E4 or E1.
2918            * FROM MHHDK:
2919            * if board is E4 or E1
2920            *   Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2921            * else
2922            *   set it to 1
2923            */
2924           NISTC_AO_PERSONAL_UPDATE_PW   |
2925           /* FIXME:  when should we set following bit to zero? */
2926           NISTC_AO_PERSONAL_TMRDACWR_PW |
2927           (board->ao_fifo_depth ?
2928             NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2929           ;
2930 #if 0
2931         /*
2932          * FIXME:
2933          * add something like ".has_individual_dacs = 0" to ni_board_struct
2934          * since, as F Hess pointed out, not all in m series have singles.  not
2935          * sure if e-series all have duals...
2936          */
2937 
2938         /*
2939          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2940          * 6281, verified with bus analyzer.
2941          */
2942         if (devpriv->is_m_series)
2943                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2944 #endif
2945         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2946 
2947         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2948 }
2949 
2950 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2951                                   const struct comedi_cmd *cmd)
2952 {
2953         struct ni_private *devpriv = dev->private;
2954         unsigned int trigsel;
2955 
2956         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2957 
2958         /* sync */
2959         if (cmd->stop_src == TRIG_NONE) {
2960                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2961                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2962         } else {
2963                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2964                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2965         }
2966         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2967 
2968         if (cmd->start_src == TRIG_INT) {
2969                 trigsel = NISTC_AO_TRIG_START1_EDGE |
2970                           NISTC_AO_TRIG_START1_SYNC;
2971         } else { /* TRIG_EXT */
2972                 trigsel = NISTC_AO_TRIG_START1_SEL(
2973                         ni_get_reg_value_roffs(CR_CHAN(cmd->start_arg),
2974                                                NI_AO_StartTrigger,
2975                                                &devpriv->routing_tables, 1));
2976                 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2977                 if (cmd->start_arg & CR_INVERT)
2978                         trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2979                 /* 0=edge detection disabled, 1=enabled */
2980                 if (cmd->start_arg & CR_EDGE)
2981                         trigsel |= NISTC_AO_TRIG_START1_EDGE;
2982         }
2983         ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2984 
2985         /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2986 
2987         /* sync */
2988         /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2989         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2990         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2991 
2992         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2993 }
2994 
2995 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
2996                                    const struct comedi_cmd *cmd)
2997 {
2998         struct ni_private *devpriv = dev->private;
2999         /* Not supporting 'waveform staging' or 'local buffer with pauses' */
3000 
3001         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3002         /*
3003          * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
3004          * set_trigger above.  It is unclear whether we really need to re-write
3005          * this register with these values.  The mhddk examples for e-series
3006          * show writing this in both places, but the examples for m-series show
3007          * a single write in the set_counters function (here).
3008          */
3009         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3010 
3011         /* sync (upload number of buffer iterations -1) */
3012         /* indicate that we want to use BC_Load_A_Register as the source */
3013         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3014         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3015 
3016         /*
3017          * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3018          * ignoring BC_TC, then we will need to find a way to ignore that
3019          * interrupt in continuous mode.
3020          */
3021         ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3022 
3023         /* sync (issue command to load number of buffer iterations -1) */
3024         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3025 
3026         /* sync (upload number of updates in buffer) */
3027         /* indicate that we want to use UC_Load_A_Register as the source */
3028         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3029         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3030 
3031         /*
3032          * if a user specifies '0', this automatically assumes the entire 24bit
3033          * address space is available for the (multiple iterations of single
3034          * buffer) MISB.  Otherwise, stop_arg specifies the MISB length that
3035          * will be used, regardless of whether we are in continuous mode or not.
3036          * In continuous mode, the output will just iterate indefinitely over
3037          * the MISB.
3038          */
3039         {
3040                 unsigned int stop_arg = cmd->stop_arg > 0 ?
3041                         (cmd->stop_arg & 0xffffff) : 0xffffff;
3042 
3043                 if (devpriv->is_m_series) {
3044                         /*
3045                          * this is how the NI example code does it for m-series
3046                          * boards, verified correct with 6259
3047                          */
3048                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3049 
3050                         /* sync (issue cmd to load number of updates in MISB) */
3051                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3052                                       NISTC_AO_CMD1_REG);
3053                 } else {
3054                         ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3055 
3056                         /* sync (issue cmd to load number of updates in MISB) */
3057                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3058                                       NISTC_AO_CMD1_REG);
3059 
3060                         /*
3061                          * sync (upload number of updates-1 in MISB)
3062                          * --eseries only?
3063                          */
3064                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3065                 }
3066         }
3067 
3068         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3069 }
3070 
3071 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3072                                  const struct comedi_cmd *cmd)
3073 {
3074         struct ni_private *devpriv = dev->private;
3075 
3076         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3077 
3078         /*
3079          * zero out these bit fields to be set below. Does an ao-reset do this
3080          * automatically?
3081          */
3082         devpriv->ao_mode1 &= ~(
3083           NISTC_AO_MODE1_UI_SRC_MASK         |
3084           NISTC_AO_MODE1_UI_SRC_POLARITY     |
3085           NISTC_AO_MODE1_UPDATE_SRC_MASK     |
3086           NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3087         );
3088 
3089         if (cmd->scan_begin_src == TRIG_TIMER) {
3090                 unsigned int trigvar;
3091 
3092                 devpriv->ao_cmd2  &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3093 
3094                 /*
3095                  * NOTE: there are several other ways of configuring internal
3096                  * updates, but we'll only support one for now:  using
3097                  * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3098                  * START1 and first update, and also w/o local buffer mode w/
3099                  * pauses.
3100                  */
3101 
3102                 /*
3103                  * This is already done above:
3104                  * devpriv->ao_mode1 &= ~(
3105                  *   // set UPDATE_Source to UI_TC:
3106                  *   NISTC_AO_MODE1_UPDATE_SRC_MASK |
3107                  *   // set UPDATE_Source_Polarity to rising (required?)
3108                  *   NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3109                  *   // set UI_Source to AO_IN_TIMEBASE1:
3110                  *   NISTC_AO_MODE1_UI_SRC_MASK     |
3111                  *   // set UI_Source_Polarity to rising (required?)
3112                  *   NISTC_AO_MODE1_UI_SRC_POLARITY
3113                  * );
3114                  */
3115 
3116                 /*
3117                  * TODO:  use ao_ui_clock_source to allow all possible signals
3118                  * to be routed to UI_Source_Select.  See tSTC.h for
3119                  * eseries/ni67xx and tMSeries.h for mseries.
3120                  */
3121 
3122                 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3123                                          CMDF_ROUND_NEAREST);
3124 
3125                 /*
3126                  * Wait N TB3 ticks after the start trigger before
3127                  * clocking (N must be >=2).
3128                  */
3129                 /* following line: 2-1 per STC */
3130                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3131                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3132                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3133         } else { /* TRIG_EXT */
3134                 /* FIXME:  assert scan_begin_arg != 0, ret failure otherwise */
3135                 devpriv->ao_cmd2  |= NISTC_AO_CMD2_BC_GATE_ENA;
3136                 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3137                         ni_get_reg_value(CR_CHAN(cmd->scan_begin_arg),
3138                                          NI_AO_SampleClock,
3139                                          &devpriv->routing_tables));
3140                 if (cmd->scan_begin_arg & CR_INVERT)
3141                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3142         }
3143 
3144         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3145         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3146         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3147                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3148         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3149 
3150         /* Configure DAQ-STC for Timed update mode */
3151         devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3152                             NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3153         /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3154         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3155 
3156         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3157 }
3158 
3159 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3160                                    struct comedi_subdevice *s)
3161 {
3162         struct ni_private *devpriv = dev->private;
3163         const struct comedi_cmd *cmd = &s->async->cmd;
3164         unsigned int bits = 0;
3165 
3166         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3167 
3168         if (devpriv->is_6xxx) {
3169                 unsigned int i;
3170 
3171                 bits = 0;
3172                 for (i = 0; i < cmd->chanlist_len; ++i) {
3173                         int chan = CR_CHAN(cmd->chanlist[i]);
3174 
3175                         bits |= 1 << chan;
3176                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3177                 }
3178                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3179         }
3180 
3181         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3182 
3183         if (cmd->scan_end_arg > 1) {
3184                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3185                 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3186                                  | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3187 
3188         } else {
3189                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3190                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3191                 if (devpriv->is_m_series | devpriv->is_6xxx)
3192                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3193                 else
3194                         bits |= NISTC_AO_OUT_CTRL_CHANS(
3195                                         CR_CHAN(cmd->chanlist[0]));
3196         }
3197 
3198         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3199         ni_stc_writew(dev, bits,              NISTC_AO_OUT_CTRL_REG);
3200 
3201         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3202 }
3203 
3204 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3205                                           const struct comedi_cmd *cmd)
3206 {
3207         struct ni_private *devpriv = dev->private;
3208 
3209         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3210 
3211         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3212         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3213 
3214         /*
3215          * Since we are not supporting waveform staging, we ignore these errors:
3216          * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3217          * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3218          */
3219 
3220         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3221 }
3222 
3223 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3224 {
3225         struct ni_private *devpriv = dev->private;
3226 
3227         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3228 
3229         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3230 #ifdef PCIDMA
3231         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3232 #else
3233         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3234 #endif
3235         /* NOTE:  this is where use_onboard_memory=True would be implemented */
3236         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3237         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3238 
3239         /* enable sending of ao fifo requests (dma request) */
3240         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3241 
3242         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3243 
3244         /* we are not supporting boards with virtual fifos */
3245 }
3246 
3247 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3248                                      struct comedi_subdevice *s)
3249 {
3250         if (s->async->cmd.stop_src == TRIG_COUNT)
3251                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3252                             NISTC_INTB_ENA_AO_BC_TC, 1);
3253 
3254         s->async->inttrig = ni_ao_inttrig;
3255 }
3256 
3257 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3258 {
3259         struct ni_private *devpriv = dev->private;
3260         const struct comedi_cmd *cmd = &s->async->cmd;
3261 
3262         if (dev->irq == 0) {
3263                 dev_err(dev->class_dev, "cannot run command without an irq");
3264                 return -EIO;
3265         }
3266 
3267         /* ni_ao_reset should have already been done */
3268         ni_ao_cmd_personalize(dev, cmd);
3269         /* clearing fifo and preload happens elsewhere */
3270 
3271         ni_ao_cmd_set_trigger(dev, cmd);
3272         ni_ao_cmd_set_counters(dev, cmd);
3273         ni_ao_cmd_set_update(dev, cmd);
3274         ni_ao_cmd_set_channels(dev, s);
3275         ni_ao_cmd_set_stop_conditions(dev, cmd);
3276         ni_ao_cmd_set_fifo_mode(dev);
3277         ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3278         ni_ao_cmd_set_interrupts(dev, s);
3279 
3280         /*
3281          * arm(ing) must happen later so that DMA can be setup and DACs
3282          * preloaded with the actual output buffer before starting.
3283          *
3284          * start(ing) must happen _after_ arming is completed.  Starting can be
3285          * done either via ni_ao_inttrig, or via an external trigger.
3286          *
3287          * **Currently, ni_ao_inttrig will automatically attempt a call to
3288          * ni_ao_arm if the device still needs arming at that point.  This
3289          * allows backwards compatibility.
3290          */
3291         devpriv->ao_needs_arming = 1;
3292         return 0;
3293 }
3294 
3295 /* end ni_ao_cmd */
3296 
3297 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3298                          struct comedi_cmd *cmd)
3299 {
3300         const struct ni_board_struct *board = dev->board_ptr;
3301         struct ni_private *devpriv = dev->private;
3302         int err = 0;
3303         unsigned int tmp;
3304 
3305         /* Step 1 : check if triggers are trivially valid */
3306 
3307         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3308         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3309                                         TRIG_TIMER | TRIG_EXT);
3310         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3311         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3312         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3313 
3314         if (err)
3315                 return 1;
3316 
3317         /* Step 2a : make sure trigger sources are unique */
3318 
3319         err |= comedi_check_trigger_is_unique(cmd->start_src);
3320         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3321         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3322 
3323         /* Step 2b : and mutually compatible */
3324 
3325         if (err)
3326                 return 2;
3327 
3328         /* Step 3: check if arguments are trivially valid */
3329 
3330         switch (cmd->start_src) {
3331         case TRIG_INT:
3332                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3333                 break;
3334         case TRIG_EXT:
3335                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
3336                                                   NI_AO_StartTrigger,
3337                                                   &devpriv->routing_tables, 1);
3338                 break;
3339         }
3340 
3341         if (cmd->scan_begin_src == TRIG_TIMER) {
3342                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3343                                                     board->ao_speed);
3344                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3345                                                     devpriv->clock_ns *
3346                                                     0xffffff);
3347         } else {                /* TRIG_EXT */
3348                 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3349                                             NI_AO_SampleClock,
3350                                             &devpriv->routing_tables);
3351         }
3352 
3353         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3354         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3355                                            cmd->chanlist_len);
3356         err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3357 
3358         if (err)
3359                 return 3;
3360 
3361         /* step 4: fix up any arguments */
3362         if (cmd->scan_begin_src == TRIG_TIMER) {
3363                 tmp = cmd->scan_begin_arg;
3364                 cmd->scan_begin_arg =
3365                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3366                                                        cmd->scan_begin_arg,
3367                                                        cmd->flags));
3368                 if (tmp != cmd->scan_begin_arg)
3369                         err++;
3370         }
3371         if (err)
3372                 return 4;
3373 
3374         return 0;
3375 }
3376 
3377 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3378 {
3379         /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3380 
3381         /*
3382          * In the following, the "--sync" comments are meant to denote
3383          * asynchronous boundaries for setting the registers as described in the
3384          * DAQ-STC mostly in the order also described in the DAQ-STC.
3385          */
3386 
3387         struct ni_private *devpriv = dev->private;
3388 
3389         ni_release_ao_mite_channel(dev);
3390 
3391         /* --sync (reset AO) */
3392         if (devpriv->is_m_series)
3393                 /* following example in mhddk for m-series */
3394                 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3395 
3396         /*--sync (start config) */
3397         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3398 
3399         /*--sync (Disarm) */
3400         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3401 
3402         /*
3403          * --sync
3404          * (clear bunch of registers--mseries mhddk examples do not include
3405          * this)
3406          */
3407         devpriv->ao_cmd1  = 0;
3408         devpriv->ao_cmd2  = 0;
3409         devpriv->ao_mode1 = 0;
3410         devpriv->ao_mode2 = 0;
3411         if (devpriv->is_m_series)
3412                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3413         else
3414                 devpriv->ao_mode3 = 0;
3415 
3416         ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3417         ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3418         ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3419         ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3420         ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3421         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3422         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3423         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3424         ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3425 
3426         /*--sync (disable interrupts) */
3427         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3428 
3429         /*--sync (ack) */
3430         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3431         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3432 
3433         /*--not in DAQ-STC.  which doc? */
3434         if (devpriv->is_6xxx) {
3435                 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3436                                NI671X_AO_IMMEDIATE_REG);
3437                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3438                                NI611X_AO_MISC_REG);
3439         }
3440         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3441         /*--end */
3442 
3443         return 0;
3444 }
3445 
3446 /* digital io */
3447 
3448 static int ni_dio_insn_config(struct comedi_device *dev,
3449                               struct comedi_subdevice *s,
3450                               struct comedi_insn *insn,
3451                               unsigned int *data)
3452 {
3453         struct ni_private *devpriv = dev->private;
3454         int ret;
3455 
3456         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3457         if (ret)
3458                 return ret;
3459 
3460         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3461         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3462         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3463 
3464         return insn->n;
3465 }
3466 
3467 static int ni_dio_insn_bits(struct comedi_device *dev,
3468                             struct comedi_subdevice *s,
3469                             struct comedi_insn *insn,
3470                             unsigned int *data)
3471 {
3472         struct ni_private *devpriv = dev->private;
3473 
3474         /* Make sure we're not using the serial part of the dio */
3475         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3476             devpriv->serial_interval_ns)
3477                 return -EBUSY;
3478 
3479         if (comedi_dio_update_state(s, data)) {
3480                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3481                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3482                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3483         }
3484 
3485         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3486 
3487         return insn->n;
3488 }
3489 
3490 #ifdef PCIDMA
3491 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3492                                        struct comedi_subdevice *s,
3493                                        struct comedi_insn *insn,
3494                                        unsigned int *data)
3495 {
3496         int ret;
3497 
3498         if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
3499                 const struct ni_board_struct *board = dev->board_ptr;
3500 
3501                 /* we don't care about actual channels */
3502                 data[1] = board->dio_speed;
3503                 data[2] = 0;
3504                 return 0;
3505         }
3506 
3507         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3508         if (ret)
3509                 return ret;
3510 
3511         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3512 
3513         return insn->n;
3514 }
3515 
3516 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3517                                      struct comedi_subdevice *s,
3518                                      struct comedi_insn *insn,
3519                                      unsigned int *data)
3520 {
3521         if (comedi_dio_update_state(s, data))
3522                 ni_writel(dev, s->state, NI_M_DIO_REG);
3523 
3524         data[1] = ni_readl(dev, NI_M_DIO_REG);
3525 
3526         return insn->n;
3527 }
3528 
3529 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3530                                   struct comedi_subdevice *s,
3531                                   struct comedi_cmd *cmd)
3532 {
3533         int i;
3534 
3535         for (i = 0; i < cmd->chanlist_len; ++i) {
3536                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3537 
3538                 if (chan != i)
3539                         return -EINVAL;
3540         }
3541 
3542         return 0;
3543 }
3544 
3545 static int ni_cdio_cmdtest(struct comedi_device *dev,
3546                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3547 {
3548         struct ni_private *devpriv = dev->private;
3549         unsigned int bytes_per_scan;
3550         int err = 0;
3551 
3552         /* Step 1 : check if triggers are trivially valid */
3553 
3554         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3555         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3556         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3557         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3558         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3559 
3560         if (err)
3561                 return 1;
3562 
3563         /* Step 2a : make sure trigger sources are unique */
3564         /* Step 2b : and mutually compatible */
3565 
3566         /* Step 3: check if arguments are trivially valid */
3567 
3568         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3569 
3570         /*
3571          * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3572          * for completeness, test whether the cmd is output or input?
3573          */
3574         err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3575                                     NI_DO_SampleClock,
3576                                     &devpriv->routing_tables);
3577         if (CR_RANGE(cmd->scan_begin_arg) != 0 ||
3578             CR_AREF(cmd->scan_begin_arg) != 0)
3579                 err |= -EINVAL;
3580 
3581         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3582         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3583                                            cmd->chanlist_len);
3584         bytes_per_scan = comedi_bytes_per_scan_cmd(s, cmd);
3585         if (bytes_per_scan) {
3586                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3587                                                     s->async->prealloc_bufsz /
3588                                                     bytes_per_scan);
3589         }
3590 
3591         if (err)
3592                 return 3;
3593 
3594         /* Step 4: fix up any arguments */
3595 
3596         /* Step 5: check channel list if it exists */
3597 
3598         if (cmd->chanlist && cmd->chanlist_len > 0)
3599                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3600 
3601         if (err)
3602                 return 5;
3603 
3604         return 0;
3605 }
3606 
3607 static int ni_cdo_inttrig(struct comedi_device *dev,
3608                           struct comedi_subdevice *s,
3609                           unsigned int trig_num)
3610 {
3611         struct comedi_cmd *cmd = &s->async->cmd;
3612         const unsigned int timeout = 1000;
3613         int retval = 0;
3614         unsigned int i;
3615         struct ni_private *devpriv = dev->private;
3616         unsigned long flags;
3617 
3618         if (trig_num != cmd->start_arg)
3619                 return -EINVAL;
3620 
3621         s->async->inttrig = NULL;
3622 
3623         /* read alloc the entire buffer */
3624         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3625 
3626         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3627         if (devpriv->cdo_mite_chan) {
3628                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3629                 mite_dma_arm(devpriv->cdo_mite_chan);
3630         } else {
3631                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3632                 retval = -EIO;
3633         }
3634         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3635         if (retval < 0)
3636                 return retval;
3637 
3638         /*
3639          * XXX not sure what interrupt C group does
3640          * wait for dma to fill output fifo
3641          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3642          */
3643         for (i = 0; i < timeout; ++i) {
3644                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3645                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3646                         break;
3647                 usleep_range(10, 100);
3648         }
3649         if (i == timeout) {
3650                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3651                 s->cancel(dev, s);
3652                 return -EIO;
3653         }
3654         ni_writel(dev, NI_M_CDO_CMD_ARM |
3655                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3656                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3657                   NI_M_CDIO_CMD_REG);
3658         return retval;
3659 }
3660 
3661 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3662 {
3663         struct ni_private *devpriv = dev->private;
3664         const struct comedi_cmd *cmd = &s->async->cmd;
3665         unsigned int cdo_mode_bits;
3666         int retval;
3667 
3668         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3669         /*
3670          * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3671          * for completeness, test whether the cmd is output or input(?)
3672          */
3673         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3674                         NI_M_CDO_MODE_HALT_ON_ERROR |
3675                         NI_M_CDO_MODE_SAMPLE_SRC(
3676                                 ni_get_reg_value(CR_CHAN(cmd->scan_begin_arg),
3677                                                  NI_DO_SampleClock,
3678                                                  &devpriv->routing_tables));
3679         if (cmd->scan_begin_arg & CR_INVERT)
3680                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3681         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3682         if (s->io_bits) {
3683                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3684                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3685                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3686         } else {
3687                 dev_err(dev->class_dev,
3688                         "attempted to run digital output command with no lines configured as outputs\n");
3689                 return -EIO;
3690         }
3691         retval = ni_request_cdo_mite_channel(dev);
3692         if (retval < 0)
3693                 return retval;
3694 
3695         ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3696                                  s->async->prealloc_bufsz /
3697                                  comedi_bytes_per_scan(s));
3698 
3699         s->async->inttrig = ni_cdo_inttrig;
3700 
3701         return 0;
3702 }
3703 
3704 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3705 {
3706         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3707                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3708                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3709                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3710                   NI_M_CDIO_CMD_REG);
3711         /*
3712          * XXX not sure what interrupt C group does
3713          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3714          */
3715         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3716         ni_release_cdo_mite_channel(dev);
3717         return 0;
3718 }
3719 
3720 static void handle_cdio_interrupt(struct comedi_device *dev)
3721 {
3722         struct ni_private *devpriv = dev->private;
3723         unsigned int cdio_status;
3724         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3725         unsigned long flags;
3726 
3727         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3728         if (devpriv->cdo_mite_chan)
3729                 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3730         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3731 
3732         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3733         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3734                 /* XXX just guessing this is needed and does something useful */
3735                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3736                           NI_M_CDIO_CMD_REG);
3737                 s->async->events |= COMEDI_CB_OVERFLOW;
3738         }
3739         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3740                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3741                           NI_M_CDIO_CMD_REG);
3742                 /* s->async->events |= COMEDI_CB_EOA; */
3743         }
3744         comedi_handle_events(dev, s);
3745 }
3746 #endif /*  PCIDMA */
3747 
3748 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3749                                    struct comedi_subdevice *s,
3750                                    unsigned char data_out,
3751                                    unsigned char *data_in)
3752 {
3753         struct ni_private *devpriv = dev->private;
3754         unsigned int status1;
3755         int err = 0, count = 20;
3756 
3757         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3758         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3759         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3760 
3761         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3762         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3763                 err = -EBUSY;
3764                 goto error;
3765         }
3766 
3767         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3768         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3769         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3770 
3771         /* Wait until STC says we're done, but don't loop infinitely. */
3772         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3773                NISTC_STATUS1_SERIO_IN_PROG) {
3774                 /* Delay one bit per loop */
3775                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3776                 if (--count < 0) {
3777                         dev_err(dev->class_dev,
3778                                 "SPI serial I/O didn't finish in time!\n");
3779                         err = -ETIME;
3780                         goto error;
3781                 }
3782         }
3783 
3784         /*
3785          * Delay for last bit. This delay is absolutely necessary, because
3786          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3787          */
3788         udelay((devpriv->serial_interval_ns + 999) / 1000);
3789 
3790         if (data_in)
3791                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3792 
3793 error:
3794         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3795 
3796         return err;
3797 }
3798 
3799 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3800                                    struct comedi_subdevice *s,
3801                                    unsigned char data_out,
3802                                    unsigned char *data_in)
3803 {
3804         struct ni_private *devpriv = dev->private;
3805         unsigned char mask, input = 0;
3806 
3807         /* Wait for one bit before transfer */
3808         udelay((devpriv->serial_interval_ns + 999) / 1000);
3809 
3810         for (mask = 0x80; mask; mask >>= 1) {
3811                 /*
3812                  * Output current bit; note that we cannot touch s->state
3813                  * because it is a per-subdevice field, and serial is
3814                  * a separate subdevice from DIO.
3815                  */
3816                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3817                 if (data_out & mask)
3818                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3819                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3820 
3821                 /*
3822                  * Assert SDCLK (active low, inverted), wait for half of
3823                  * the delay, deassert SDCLK, and wait for the other half.
3824                  */
3825                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3826                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3827 
3828                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3829 
3830                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3831                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3832 
3833                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3834 
3835                 /* Input current bit */
3836                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3837                         input |= mask;
3838         }
3839 
3840         if (data_in)
3841                 *data_in = input;
3842 
3843         return 0;
3844 }
3845 
3846 static int ni_serial_insn_config(struct comedi_device *dev,
3847                                  struct comedi_subdevice *s,
3848                                  struct comedi_insn *insn,
3849                                  unsigned int *data)
3850 {
3851         struct ni_private *devpriv = dev->private;
3852         unsigned int clk_fout = devpriv->clock_and_fout;
3853         int err = insn->n;
3854         unsigned char byte_out, byte_in = 0;
3855 
3856         if (insn->n != 2)
3857                 return -EINVAL;
3858 
3859         switch (data[0]) {
3860         case INSN_CONFIG_SERIAL_CLOCK:
3861                 devpriv->serial_hw_mode = 1;
3862                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3863 
3864                 if (data[1] == SERIAL_DISABLED) {
3865                         devpriv->serial_hw_mode = 0;
3866                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3867                                                   NISTC_DIO_SDCLK);
3868                         data[1] = SERIAL_DISABLED;
3869                         devpriv->serial_interval_ns = data[1];
3870                 } else if (data[1] <= SERIAL_600NS) {
3871                         /*
3872                          * Warning: this clock speed is too fast to reliably
3873                          * control SCXI.
3874                          */
3875                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3876                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3877                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3878                         data[1] = SERIAL_600NS;
3879                         devpriv->serial_interval_ns = data[1];
3880                 } else if (data[1] <= SERIAL_1_2US) {
3881                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3882                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3883                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3884                         data[1] = SERIAL_1_2US;
3885                         devpriv->serial_interval_ns = data[1];
3886                 } else if (data[1] <= SERIAL_10US) {
3887                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3888                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3889                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3890                         /*
3891                          * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3892                          * 600ns/1.2us. If you turn divide_by_2 off with the
3893                          * slow clock, you will still get 10us, except then
3894                          * all your delays are wrong.
3895                          */
3896                         data[1] = SERIAL_10US;
3897                         devpriv->serial_interval_ns = data[1];
3898                 } else {
3899                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3900                                                   NISTC_DIO_SDCLK);
3901                         devpriv->serial_hw_mode = 0;
3902                         data[1] = (data[1] / 1000) * 1000;
3903                         devpriv->serial_interval_ns = data[1];
3904                 }
3905                 devpriv->clock_and_fout = clk_fout;
3906 
3907                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3908                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3909                 return 1;
3910 
3911         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3912 
3913                 if (devpriv->serial_interval_ns == 0)
3914                         return -EINVAL;
3915 
3916                 byte_out = data[1] & 0xFF;
3917 
3918                 if (devpriv->serial_hw_mode) {
3919                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3920                                                       &byte_in);
3921                 } else if (devpriv->serial_interval_ns > 0) {
3922                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3923                                                       &byte_in);
3924                 } else {
3925                         dev_err(dev->class_dev, "serial disabled!\n");
3926                         return -EINVAL;
3927                 }
3928                 if (err < 0)
3929                         return err;
3930                 data[1] = byte_in & 0xFF;
3931                 return insn->n;
3932 
3933                 break;
3934         default:
3935                 return -EINVAL;
3936         }
3937 }
3938 
3939 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3940 {
3941         int i;
3942 
3943         for (i = 0; i < s->n_chan; i++) {
3944                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3945                                NI67XX_AO_CFG2_REG);
3946         }
3947         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3948 }
3949 
3950 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3951         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3952         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
3953         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3954         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3955         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
3956         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
3957         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
3958         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
3959         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3960         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3961         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3962         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3963         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3964         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3965         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3966         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3967         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3968         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3969         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3970         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3971         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
3972         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
3973         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
3974         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
3975         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3976         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3977         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3978         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3979         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3980         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3981         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3982         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3983         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
3984         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
3985         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
3986         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
3987 };
3988 
3989 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3990                                             enum ni_gpct_register reg)
3991 {
3992         const struct mio_regmap *regmap;
3993 
3994         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3995                 regmap = &ni_gpct_to_stc_regmap[reg];
3996         } else {
3997                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3998                          __func__, reg);
3999                 return 0;
4000         }
4001 
4002         return regmap->mio_reg;
4003 }
4004 
4005 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
4006                                    enum ni_gpct_register reg)
4007 {
4008         struct comedi_device *dev = counter->counter_dev->dev;
4009         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4010 
4011         if (stc_register == 0)
4012                 return;
4013 
4014         switch (reg) {
4015                 /* m-series only registers */
4016         case NITIO_G0_CNT_MODE:
4017         case NITIO_G1_CNT_MODE:
4018         case NITIO_G0_GATE2:
4019         case NITIO_G1_GATE2:
4020         case NITIO_G0_DMA_CFG:
4021         case NITIO_G1_DMA_CFG:
4022         case NITIO_G0_ABZ:
4023         case NITIO_G1_ABZ:
4024                 ni_writew(dev, bits, stc_register);
4025                 break;
4026 
4027                 /* 32 bit registers */
4028         case NITIO_G0_LOADA:
4029         case NITIO_G1_LOADA:
4030         case NITIO_G0_LOADB:
4031         case NITIO_G1_LOADB:
4032                 ni_stc_writel(dev, bits, stc_register);
4033                 break;
4034 
4035                 /* 16 bit registers */
4036         case NITIO_G0_INT_ENA:
4037                 ni_set_bitfield(dev, stc_register,
4038                                 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
4039                                 bits);
4040                 break;
4041         case NITIO_G1_INT_ENA:
4042                 ni_set_bitfield(dev, stc_register,
4043                                 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
4044                                 bits);
4045                 break;
4046         default:
4047                 ni_stc_writew(dev, bits, stc_register);
4048         }
4049 }
4050 
4051 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4052                                           enum ni_gpct_register reg)
4053 {
4054         struct comedi_device *dev = counter->counter_dev->dev;
4055         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4056 
4057         if (stc_register == 0)
4058                 return 0;
4059 
4060         switch (reg) {
4061                 /* m-series only registers */
4062         case NITIO_G0_DMA_STATUS:
4063         case NITIO_G1_DMA_STATUS:
4064                 return ni_readw(dev, stc_register);
4065 
4066                 /* 32 bit registers */
4067         case NITIO_G0_HW_SAVE:
4068         case NITIO_G1_HW_SAVE:
4069         case NITIO_G0_SW_SAVE:
4070         case NITIO_G1_SW_SAVE:
4071                 return ni_stc_readl(dev, stc_register);
4072 
4073                 /* 16 bit registers */
4074         default:
4075                 return ni_stc_readw(dev, stc_register);
4076         }
4077 }
4078 
4079 static int ni_freq_out_insn_read(struct comedi_device *dev,
4080                                  struct comedi_subdevice *s,
4081                                  struct comedi_insn *insn,
4082                                  unsigned int *data)
4083 {
4084         struct ni_private *devpriv = dev->private;
4085         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4086         int i;
4087 
4088         for (i = 0; i < insn->n; i++)
4089                 data[i] = val;
4090 
4091         return insn->n;
4092 }
4093 
4094 static int ni_freq_out_insn_write(struct comedi_device *dev,
4095                                   struct comedi_subdevice *s,
4096                                   struct comedi_insn *insn,
4097                                   unsigned int *data)
4098 {
4099         struct ni_private *devpriv = dev->private;
4100 
4101         if (insn->n) {
4102                 unsigned int val = data[insn->n - 1];
4103 
4104                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4105                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4106                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4107 
4108                 /* use the last data value to set the fout divider */
4109                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4110 
4111                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4112                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4113         }
4114         return insn->n;
4115 }
4116 
4117 static int ni_freq_out_insn_config(struct comedi_device *dev,
4118                                    struct comedi_subdevice *s,
4119                                    struct comedi_insn *insn,
4120                                    unsigned int *data)
4121 {
4122         struct ni_private *devpriv = dev->private;
4123 
4124         switch (data[0]) {
4125         case INSN_CONFIG_SET_CLOCK_SRC:
4126                 switch (data[1]) {
4127                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4128                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4129                         break;
4130                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4131                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4132                         break;
4133                 default:
4134                         return -EINVAL;
4135                 }
4136                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4137                 break;
4138         case INSN_CONFIG_GET_CLOCK_SRC:
4139                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4140                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4141                         data[2] = TIMEBASE_2_NS;
4142                 } else {
4143                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4144                         data[2] = TIMEBASE_1_NS * 2;
4145                 }
4146                 break;
4147         default:
4148                 return -EINVAL;
4149         }
4150         return insn->n;
4151 }
4152 
4153 static int ni_8255_callback(struct comedi_device *dev,
4154                             int dir, int port, int data, unsigned long iobase)
4155 {
4156         if (dir) {
4157                 ni_writeb(dev, data, iobase + 2 * port);
4158                 return 0;
4159         }
4160 
4161         return ni_readb(dev, iobase + 2 * port);
4162 }
4163 
4164 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4165 {
4166         struct ni_private *devpriv = dev->private;
4167 
4168         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4169         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4170         return 3;
4171 }
4172 
4173 static int ni_m_series_pwm_config(struct comedi_device *dev,
4174                                   struct comedi_subdevice *s,
4175                                   struct comedi_insn *insn,
4176                                   unsigned int *data)
4177 {
4178         struct ni_private *devpriv = dev->private;
4179         unsigned int up_count, down_count;
4180 
4181         switch (data[0]) {
4182         case INSN_CONFIG_PWM_OUTPUT:
4183                 switch (data[1]) {
4184                 case CMDF_ROUND_NEAREST:
4185                         up_count = DIV_ROUND_CLOSEST(data[2],
4186                                                      devpriv->clock_ns);
4187                         break;
4188                 case CMDF_ROUND_DOWN:
4189                         up_count = data[2] / devpriv->clock_ns;
4190                         break;
4191                 case CMDF_ROUND_UP:
4192                         up_count =
4193                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4194                         break;
4195                 default:
4196                         return -EINVAL;
4197                 }
4198                 switch (data[3]) {
4199                 case CMDF_ROUND_NEAREST:
4200                         down_count = DIV_ROUND_CLOSEST(data[4],
4201                                                        devpriv->clock_ns);
4202                         break;
4203                 case CMDF_ROUND_DOWN:
4204                         down_count = data[4] / devpriv->clock_ns;
4205                         break;
4206                 case CMDF_ROUND_UP:
4207                         down_count =
4208                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4209                         break;
4210                 default:
4211                         return -EINVAL;
4212                 }
4213                 if (up_count * devpriv->clock_ns != data[2] ||
4214                     down_count * devpriv->clock_ns != data[4]) {
4215                         data[2] = up_count * devpriv->clock_ns;
4216                         data[4] = down_count * devpriv->clock_ns;
4217                         return -EAGAIN;
4218                 }
4219                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4220                                NI_M_CAL_PWM_LOW_TIME(down_count),
4221                           NI_M_CAL_PWM_REG);
4222                 devpriv->pwm_up_count = up_count;
4223                 devpriv->pwm_down_count = down_count;
4224                 return 5;
4225         case INSN_CONFIG_GET_PWM_OUTPUT:
4226                 return ni_get_pwm_config(dev, data);
4227         default:
4228                 return -EINVAL;
4229         }
4230         return 0;
4231 }
4232 
4233 static int ni_6143_pwm_config(struct comedi_device *dev,
4234                               struct comedi_subdevice *s,
4235                               struct comedi_insn *insn,
4236                               unsigned int *data)
4237 {
4238         struct ni_private *devpriv = dev->private;
4239         unsigned int up_count, down_count;
4240 
4241         switch (data[0]) {
4242         case INSN_CONFIG_PWM_OUTPUT:
4243                 switch (data[1]) {
4244                 case CMDF_ROUND_NEAREST:
4245                         up_count = DIV_ROUND_CLOSEST(data[2],
4246                                                      devpriv->clock_ns);
4247                         break;
4248                 case CMDF_ROUND_DOWN:
4249                         up_count = data[2] / devpriv->clock_ns;
4250                         break;
4251                 case CMDF_ROUND_UP:
4252                         up_count =
4253                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4254                         break;
4255                 default:
4256                         return -EINVAL;
4257                 }
4258                 switch (data[3]) {
4259                 case CMDF_ROUND_NEAREST:
4260                         down_count = DIV_ROUND_CLOSEST(data[4],
4261                                                        devpriv->clock_ns);
4262                         break;
4263                 case CMDF_ROUND_DOWN:
4264                         down_count = data[4] / devpriv->clock_ns;
4265                         break;
4266                 case CMDF_ROUND_UP:
4267                         down_count =
4268                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4269                         break;
4270                 default:
4271                         return -EINVAL;
4272                 }
4273                 if (up_count * devpriv->clock_ns != data[2] ||
4274                     down_count * devpriv->clock_ns != data[4]) {
4275                         data[2] = up_count * devpriv->clock_ns;
4276                         data[4] = down_count * devpriv->clock_ns;
4277                         return -EAGAIN;
4278                 }
4279                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4280                 devpriv->pwm_up_count = up_count;
4281                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4282                 devpriv->pwm_down_count = down_count;
4283                 return 5;
4284         case INSN_CONFIG_GET_PWM_OUTPUT:
4285                 return ni_get_pwm_config(dev, data);
4286         default:
4287                 return -EINVAL;
4288         }
4289         return 0;
4290 }
4291 
4292 static int pack_mb88341(int addr, int val, int *bitstring)
4293 {
4294         /*
4295          * Fujitsu MB 88341
4296          * Note that address bits are reversed.  Thanks to
4297          * Ingo Keen for noticing this.
4298          *
4299          * Note also that the 88341 expects address values from
4300          * 1-12, whereas we use channel numbers 0-11.  The NI
4301          * docs use 1-12, also, so be careful here.
4302          */
4303         addr++;
4304         *bitstring = ((addr & 0x1) << 11) |
4305             ((addr & 0x2) << 9) |
4306             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4307         return 12;
4308 }
4309 
4310 static int pack_dac8800(int addr, int val, int *bitstring)
4311 {
4312         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4313         return 11;
4314 }
4315 
4316 static int pack_dac8043(int addr, int val, int *bitstring)
4317 {
4318         *bitstring = val & 0xfff;
4319         return 12;
4320 }
4321 
4322 static int pack_ad8522(int addr, int val, int *bitstring)
4323 {
4324         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4325         return 16;
4326 }
4327 
4328 static int pack_ad8804(int addr, int val, int *bitstring)
4329 {
4330         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4331         return 12;
4332 }
4333 
4334 static int pack_ad8842(int addr, int val, int *bitstring)
4335 {
4336         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4337         return 12;
4338 }
4339 
4340 struct caldac_struct {
4341         int n_chans;
4342         int n_bits;
4343         int (*packbits)(int address, int value, int *bitstring);
4344 };
4345 
4346 static struct caldac_struct caldacs[] = {
4347         [mb88341] = {12, 8, pack_mb88341},
4348         [dac8800] = {8, 8, pack_dac8800},
4349         [dac8043] = {1, 12, pack_dac8043},
4350         [ad8522] = {2, 12, pack_ad8522},
4351         [ad8804] = {12, 8, pack_ad8804},
4352         [ad8842] = {8, 8, pack_ad8842},
4353         [ad8804_debug] = {16, 8, pack_ad8804},
4354 };
4355 
4356 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4357 {
4358         const struct ni_board_struct *board = dev->board_ptr;
4359         struct ni_private *devpriv = dev->private;
4360         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4361         unsigned int cmd;
4362         int i;
4363         int type;
4364 
4365         if (devpriv->caldacs[addr] == val)
4366                 return;
4367         devpriv->caldacs[addr] = val;
4368 
4369         for (i = 0; i < 3; i++) {
4370                 type = board->caldac[i];
4371                 if (type == caldac_none)
4372                         break;
4373                 if (addr < caldacs[type].n_chans) {
4374                         bits = caldacs[type].packbits(addr, val, &bitstring);
4375                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4376                         break;
4377                 }
4378                 addr -= caldacs[type].n_chans;
4379         }
4380 
4381         /* bits will be 0 if there is no caldac for the given addr */
4382         if (bits == 0)
4383                 return;
4384 
4385         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4386                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4387                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4388                 udelay(1);
4389                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4390                 udelay(1);
4391         }
4392         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4393         udelay(1);
4394         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4395 }
4396 
4397 static int ni_calib_insn_write(struct comedi_device *dev,
4398                                struct comedi_subdevice *s,
4399                                struct comedi_insn *insn,
4400                                unsigned int *data)
4401 {
4402         if (insn->n) {
4403                 /* only bother writing the last sample to the channel */
4404                 ni_write_caldac(dev, CR_CHAN(insn->chanspec),
4405                                 data[insn->n - 1]);
4406         }
4407 
4408         return insn->n;
4409 }
4410 
4411 static int ni_calib_insn_read(struct comedi_device *dev,
4412                               struct comedi_subdevice *s,
4413                               struct comedi_insn *insn,
4414                               unsigned int *data)
4415 {
4416         struct ni_private *devpriv = dev->private;
4417         unsigned int i;
4418 
4419         for (i = 0; i < insn->n; i++)
4420                 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4421 
4422         return insn->n;
4423 }
4424 
4425 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4426 {
4427         const struct ni_board_struct *board = dev->board_ptr;
4428         struct ni_private *devpriv = dev->private;
4429         int i, j;
4430         int n_dacs;
4431         int n_chans = 0;
4432         int n_bits;
4433         int diffbits = 0;
4434         int type;
4435         int chan;
4436 
4437         type = board->caldac[0];
4438         if (type == caldac_none)
4439                 return;
4440         n_bits = caldacs[type].n_bits;
4441         for (i = 0; i < 3; i++) {
4442                 type = board->caldac[i];
4443                 if (type == caldac_none)
4444                         break;
4445                 if (caldacs[type].n_bits != n_bits)
4446                         diffbits = 1;
4447                 n_chans += caldacs[type].n_chans;
4448         }
4449         n_dacs = i;
4450         s->n_chan = n_chans;
4451 
4452         if (diffbits) {
4453                 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4454 
4455                 if (n_chans > MAX_N_CALDACS)
4456                         dev_err(dev->class_dev,
4457                                 "BUG! MAX_N_CALDACS too small\n");
4458                 s->maxdata_list = maxdata_list;
4459                 chan = 0;
4460                 for (i = 0; i < n_dacs; i++) {
4461                         type = board->caldac[i];
4462                         for (j = 0; j < caldacs[type].n_chans; j++) {
4463                                 maxdata_list[chan] =
4464                                     (1 << caldacs[type].n_bits) - 1;
4465                                 chan++;
4466                         }
4467                 }
4468 
4469                 for (chan = 0; chan < s->n_chan; chan++)
4470                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4471         } else {
4472                 type = board->caldac[0];
4473                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4474 
4475                 for (chan = 0; chan < s->n_chan; chan++)
4476                         ni_write_caldac(dev, i, s->maxdata / 2);
4477         }
4478 }
4479 
4480 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4481 {
4482         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4483         int bit;
4484         int bitstring;
4485 
4486         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4487         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4488         for (bit = 0x8000; bit; bit >>= 1) {
4489                 if (bit & bitstring)
4490                         cmd |= NI_E_SERIAL_CMD_SDATA;
4491                 else
4492                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4493 
4494                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4495                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4496         }
4497         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4498         bitstring = 0;
4499         for (bit = 0x80; bit; bit >>= 1) {
4500                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4501                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4502                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4503                         bitstring |= bit;
4504         }
4505         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4506 
4507         return bitstring;
4508 }
4509 
4510 static int ni_eeprom_insn_read(struct comedi_device *dev,
4511                                struct comedi_subdevice *s,
4512                                struct comedi_insn *insn,
4513                                unsigned int *data)
4514 {
4515         unsigned int val;
4516         unsigned int i;
4517 
4518         if (insn->n) {
4519                 val = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4520                 for (i = 0; i < insn->n; i++)
4521                         data[i] = val;
4522         }
4523         return insn->n;
4524 }
4525 
4526 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4527                                         struct comedi_subdevice *s,
4528                                         struct comedi_insn *insn,
4529                                         unsigned int *data)
4530 {
4531         struct ni_private *devpriv = dev->private;
4532         unsigned int i;
4533 
4534         for (i = 0; i < insn->n; i++)
4535                 data[i] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4536 
4537         return insn->n;
4538 }
4539 
4540 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4541                                            unsigned int chan)
4542 {
4543         /*  pre-m-series boards have fixed signals on pfi pins */
4544         switch (chan) {
4545         case 0:
4546                 return NI_PFI_OUTPUT_AI_START1;
4547         case 1:
4548                 return NI_PFI_OUTPUT_AI_START2;
4549         case 2:
4550                 return NI_PFI_OUTPUT_AI_CONVERT;
4551         case 3:
4552                 return NI_PFI_OUTPUT_G_SRC1;
4553         case 4:
4554                 return NI_PFI_OUTPUT_G_GATE1;
4555         case 5:
4556                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4557         case 6:
4558                 return NI_PFI_OUTPUT_AO_START1;
4559         case 7:
4560                 return NI_PFI_OUTPUT_AI_START_PULSE;
4561         case 8:
4562                 return NI_PFI_OUTPUT_G_SRC0;
4563         case 9:
4564                 return NI_PFI_OUTPUT_G_GATE0;
4565         default:
4566                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4567                 break;
4568         }
4569         return 0;
4570 }
4571 
4572 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4573                                   unsigned int chan, unsigned int source)
4574 {
4575         /*  pre-m-series boards have fixed signals on pfi pins */
4576         if (source != ni_old_get_pfi_routing(dev, chan))
4577                 return -EINVAL;
4578         return 2;
4579 }
4580 
4581 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4582                                                 unsigned int chan)
4583 {
4584         struct ni_private *devpriv = dev->private;
4585         const unsigned int array_offset = chan / 3;
4586 
4587         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4588                                 devpriv->pfi_output_select_reg[array_offset]);
4589 }
4590 
4591 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4592                                        unsigned int chan, unsigned int source)
4593 {
4594         struct ni_private *devpriv = dev->private;
4595         unsigned int index = chan / 3;
4596         unsigned short val = devpriv->pfi_output_select_reg[index];
4597 
4598         if ((source & 0x1f) != source)
4599                 return -EINVAL;
4600 
4601         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4602         val |= NI_M_PFI_OUT_SEL(chan, source);
4603         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4604         devpriv->pfi_output_select_reg[index] = val;
4605 
4606         return 2;
4607 }
4608 
4609 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4610                                        unsigned int chan)
4611 {
4612         struct ni_private *devpriv = dev->private;
4613 
4614         if (chan >= NI_PFI(0)) {
4615                 /* allow new and old names of pfi channels to work. */
4616                 chan -= NI_PFI(0);
4617         }
4618         return (devpriv->is_m_series)
4619                         ? ni_m_series_get_pfi_routing(dev, chan)
4620                         : ni_old_get_pfi_routing(dev, chan);
4621 }
4622 
4623 /* Sets the output mux for the specified PFI channel. */
4624 static int ni_set_pfi_routing(struct comedi_device *dev,
4625                               unsigned int chan, unsigned int source)
4626 {
4627         struct ni_private *devpriv = dev->private;
4628 
4629         if (chan >= NI_PFI(0)) {
4630                 /* allow new and old names of pfi channels to work. */
4631                 chan -= NI_PFI(0);
4632         }
4633         return (devpriv->is_m_series)
4634                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4635                         : ni_old_set_pfi_routing(dev, chan, source);
4636 }
4637 
4638 static int ni_config_pfi_filter(struct comedi_device *dev,
4639                                 unsigned int chan,
4640                                 enum ni_pfi_filter_select filter)
4641 {
4642         struct ni_private *devpriv = dev->private;
4643         unsigned int bits;
4644 
4645         if (!devpriv->is_m_series)
4646                 return -ENOTSUPP;
4647 
4648         if (chan >= NI_PFI(0)) {
4649                 /* allow new and old names of pfi channels to work. */
4650                 chan -= NI_PFI(0);
4651         }
4652 
4653         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4654         bits &= ~NI_M_PFI_FILTER_SEL_MASK(chan);
4655         bits |= NI_M_PFI_FILTER_SEL(chan, filter);
4656         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4657         return 0;
4658 }
4659 
4660 static void ni_set_pfi_direction(struct comedi_device *dev, int chan,
4661                                  unsigned int direction)
4662 {
4663         if (chan >= NI_PFI(0)) {
4664                 /* allow new and old names of pfi channels to work. */
4665                 chan -= NI_PFI(0);
4666         }
4667         direction = (direction == COMEDI_OUTPUT) ? 1u : 0u;
4668         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, direction);
4669 }
4670 
4671 static int ni_get_pfi_direction(struct comedi_device *dev, int chan)
4672 {
4673         struct ni_private *devpriv = dev->private;
4674 
4675         if (chan >= NI_PFI(0)) {
4676                 /* allow new and old names of pfi channels to work. */
4677                 chan -= NI_PFI(0);
4678         }
4679         return devpriv->io_bidirection_pin_reg & (1 << chan) ?
4680                COMEDI_OUTPUT : COMEDI_INPUT;
4681 }
4682 
4683 static int ni_pfi_insn_config(struct comedi_device *dev,
4684                               struct comedi_subdevice *s,
4685                               struct comedi_insn *insn,
4686                               unsigned int *data)
4687 {
4688         unsigned int chan;
4689 
4690         if (insn->n < 1)
4691                 return -EINVAL;
4692 
4693         chan = CR_CHAN(insn->chanspec);
4694 
4695         switch (data[0]) {
4696         case COMEDI_OUTPUT:
4697         case COMEDI_INPUT:
4698                 ni_set_pfi_direction(dev, chan, data[0]);
4699                 break;
4700         case INSN_CONFIG_DIO_QUERY:
4701                 data[1] = ni_get_pfi_direction(dev, chan);
4702                 break;
4703         case INSN_CONFIG_SET_ROUTING:
4704                 return ni_set_pfi_routing(dev, chan, data[1]);
4705         case INSN_CONFIG_GET_ROUTING:
4706                 data[1] = ni_get_pfi_routing(dev, chan);
4707                 break;
4708         case INSN_CONFIG_FILTER:
4709                 return ni_config_pfi_filter(dev, chan, data[1]);
4710         default:
4711                 return -EINVAL;
4712         }
4713         return 0;
4714 }
4715 
4716 static int ni_pfi_insn_bits(struct comedi_device *dev,
4717                             struct comedi_subdevice *s,
4718                             struct comedi_insn *insn,
4719                             unsigned int *data)
4720 {
4721         struct ni_private *devpriv = dev->private;
4722 
4723         if (!devpriv->is_m_series)
4724                 return -ENOTSUPP;
4725 
4726         if (comedi_dio_update_state(s, data))
4727                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4728 
4729         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4730 
4731         return insn->n;
4732 }
4733 
4734 static int cs5529_wait_for_idle(struct comedi_device *dev)
4735 {
4736         unsigned short status;
4737         const int timeout = HZ;
4738         int i;
4739 
4740         for (i = 0; i < timeout; i++) {
4741                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4742                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4743                         break;
4744                 set_current_state(TASK_INTERRUPTIBLE);
4745                 if (schedule_timeout(1))
4746                         return -EIO;
4747         }
4748         if (i == timeout) {
4749                 dev_err(dev->class_dev, "timeout\n");
4750                 return -ETIME;
4751         }
4752         return 0;
4753 }
4754 
4755 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4756 {
4757         static const int timeout = 100;
4758         int i;
4759 
4760         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4761         /* give time for command to start being serially clocked into cs5529.
4762          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4763          * set before we exit this function.
4764          */
4765         for (i = 0; i < timeout; i++) {
4766                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4767                     NI67XX_CAL_STATUS_BUSY)
4768                         break;
4769                 udelay(1);
4770         }
4771         if (i == timeout)
4772                 dev_err(dev->class_dev,
4773                         "possible problem - never saw adc go busy?\n");
4774 }
4775 
4776 static int cs5529_do_conversion(struct comedi_device *dev,
4777                                 unsigned short *data)
4778 {
4779         int retval;
4780         unsigned short status;
4781 
4782         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4783         retval = cs5529_wait_for_idle(dev);
4784         if (retval) {
4785                 dev_err(dev->class_dev,
4786                         "timeout or signal in %s()\n", __func__);
4787                 return -ETIME;
4788         }
4789         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4790         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4791                 dev_err(dev->class_dev,
4792                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4793                 return -EIO;
4794         }
4795         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4796                 dev_err(dev->class_dev,
4797                         "cs5529 conversion error, overrange (ignoring)\n");
4798         }
4799         if (data) {
4800                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4801                 /* cs5529 returns 16 bit signed data in bipolar mode */
4802                 *data ^= BIT(15);
4803         }
4804         return 0;
4805 }
4806 
4807 static int cs5529_ai_insn_read(struct comedi_device *dev,
4808                                struct comedi_subdevice *s,
4809                                struct comedi_insn *insn,
4810                                unsigned int *data)
4811 {
4812         int n, retval;
4813         unsigned short sample;
4814         unsigned int channel_select;
4815         const unsigned int INTERNAL_REF = 0x1000;
4816 
4817         /*
4818          * Set calibration adc source.  Docs lie, reference select bits 8 to 11
4819          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4820          * 13 causes the adc input to go overrange (maybe reads external
4821          * reference?)
4822          */
4823         if (insn->chanspec & CR_ALT_SOURCE)
4824                 channel_select = INTERNAL_REF;
4825         else
4826                 channel_select = CR_CHAN(insn->chanspec);
4827         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4828 
4829         for (n = 0; n < insn->n; n++) {
4830                 retval = cs5529_do_conversion(dev, &sample);
4831                 if (retval < 0)
4832                         return retval;
4833                 data[n] = sample;
4834         }
4835         return insn->n;
4836 }
4837 
4838 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4839                                 unsigned int reg_select_bits)
4840 {
4841         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4842         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4843         reg_select_bits &= CS5529_CMD_REG_MASK;
4844         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4845         if (cs5529_wait_for_idle(dev))
4846                 dev_err(dev->class_dev,
4847                         "timeout or signal in %s\n", __func__);
4848 }
4849 
4850 static int init_cs5529(struct comedi_device *dev)
4851 {
4852         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4853                                    CS5529_CFG_WORD_RATE_2180;
4854 
4855 #if 1
4856         /* do self-calibration */
4857         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4858                             CS5529_CFG_REG);
4859         /* need to force a conversion for calibration to run */
4860         cs5529_do_conversion(dev, NULL);
4861 #else
4862         /* force gain calibration to 1 */
4863         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4864         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4865                             CS5529_CFG_REG);
4866         if (cs5529_wait_for_idle(dev))
4867                 dev_err(dev->class_dev,
4868                         "timeout or signal in %s\n", __func__);
4869 #endif
4870         return 0;
4871 }
4872 
4873 /*
4874  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4875  * given an arbitrary frequency input clock.
4876  */
4877 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4878                                          unsigned int *freq_divider,
4879                                          unsigned int *freq_multiplier,
4880                                          unsigned int *actual_period_ns)
4881 {
4882         unsigned int div;
4883         unsigned int best_div = 1;
4884         unsigned int mult;
4885         unsigned int best_mult = 1;
4886         static const unsigned int pico_per_nano = 1000;
4887         const unsigned int reference_picosec = reference_period_ns *
4888                                                pico_per_nano;
4889         /*
4890          * m-series wants the phased-locked loop to output 80MHz, which is
4891          * divided by 4 to 20 MHz for most timing clocks
4892          */
4893         static const unsigned int target_picosec = 12500;
4894         int best_period_picosec = 0;
4895 
4896         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4897                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4898                         unsigned int new_period_ps =
4899                             (reference_picosec * div) / mult;
4900                         if (abs(new_period_ps - target_picosec) <
4901                             abs(best_period_picosec - target_picosec)) {
4902                                 best_period_picosec = new_period_ps;
4903                                 best_div = div;
4904                                 best_mult = mult;
4905                         }
4906                 }
4907         }
4908         if (best_period_picosec == 0)
4909                 return -EIO;
4910 
4911         *freq_divider = best_div;
4912         *freq_multiplier = best_mult;
4913         /* return the actual period (* fudge factor for 80 to 20 MHz) */
4914         *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4915                                               pico_per_nano);
4916         return 0;
4917 }
4918 
4919 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4920                                            unsigned int source,
4921                                            unsigned int period_ns)
4922 {
4923         struct ni_private *devpriv = dev->private;
4924         static const unsigned int min_period_ns = 50;
4925         static const unsigned int max_period_ns = 1000;
4926         static const unsigned int timeout = 1000;
4927         unsigned int pll_control_bits;
4928         unsigned int freq_divider;
4929         unsigned int freq_multiplier;
4930         unsigned int rtsi;
4931         unsigned int i;
4932         int retval;
4933 
4934         if (source == NI_MIO_PLL_PXI10_CLOCK)
4935                 period_ns = 100;
4936         /*
4937          * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4938          * range so we'll use that.
4939          */
4940         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4941                 dev_err(dev->class_dev,
4942                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4943                         __func__, min_period_ns, max_period_ns);
4944                 return -EINVAL;
4945         }
4946         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4947         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4948                       NISTC_RTSI_TRIG_DIR_REG);
4949         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4950         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4951                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4952         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4953         switch (source) {
4954         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4955                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4956                 break;
4957         case NI_MIO_PLL_PXI10_CLOCK:
4958                 /* pxi clock is 10MHz */
4959                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4960                 break;
4961         default:
4962                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4963                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4964                                 devpriv->clock_and_fout2 |=
4965                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4966                                 break;
4967                         }
4968                 }
4969                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4970                         return -EINVAL;
4971                 break;
4972         }
4973         retval = ni_mseries_get_pll_parameters(period_ns,
4974                                                &freq_divider,
4975                                                &freq_multiplier,
4976                                                &devpriv->clock_ns);
4977         if (retval < 0) {
4978                 dev_err(dev->class_dev,
4979                         "bug, failed to find pll parameters\n");
4980                 return retval;
4981         }
4982 
4983         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4984         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4985                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4986 
4987         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4988         devpriv->clock_source = source;
4989         /* it takes a few hundred microseconds for PLL to lock */
4990         for (i = 0; i < timeout; ++i) {
4991                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4992                         break;
4993                 udelay(1);
4994         }
4995         if (i == timeout) {
4996                 dev_err(dev->class_dev,
4997                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4998                         __func__, source, period_ns);
4999                 return -ETIMEDOUT;
5000         }
5001         return 3;
5002 }
5003 
5004 static int ni_set_master_clock(struct comedi_device *dev,
5005                                unsigned int source, unsigned int period_ns)
5006 {
5007         struct ni_private *devpriv = dev->private;
5008 
5009         if (source == NI_MIO_INTERNAL_CLOCK) {
5010                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
5011                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5012                               NISTC_RTSI_TRIG_DIR_REG);
5013                 devpriv->clock_ns = TIMEBASE_1_NS;
5014                 if (devpriv->is_m_series) {
5015                         devpriv->clock_and_fout2 &=
5016                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
5017                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
5018                         ni_writew(dev, devpriv->clock_and_fout2,
5019                                   NI_M_CLK_FOUT2_REG);
5020                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
5021                 }
5022                 devpriv->clock_source = source;
5023         } else {
5024                 if (devpriv->is_m_series) {
5025                         return ni_mseries_set_pll_master_clock(dev, source,
5026                                                                period_ns);
5027                 } else {
5028                         if (source == NI_MIO_RTSI_CLOCK) {
5029                                 devpriv->rtsi_trig_direction_reg |=
5030                                     NISTC_RTSI_TRIG_USE_CLK;
5031                                 ni_stc_writew(dev,
5032                                               devpriv->rtsi_trig_direction_reg,
5033                                               NISTC_RTSI_TRIG_DIR_REG);
5034                                 if (period_ns == 0) {
5035                                         dev_err(dev->class_dev,
5036                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
5037                                         return -EINVAL;
5038                                 }
5039                                 devpriv->clock_ns = period_ns;
5040                                 devpriv->clock_source = source;
5041                         } else {
5042                                 return -EINVAL;
5043                         }
5044                 }
5045         }
5046         return 3;
5047 }
5048 
5049 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
5050                                        unsigned int chan, unsigned int source)
5051 {
5052         struct ni_private *devpriv = dev->private;
5053 
5054         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5055                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5056                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5057                                 return 1;
5058 
5059                         dev_err(dev->class_dev,
5060                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
5061                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
5062                         return 0;
5063                 }
5064                 return 0;
5065         }
5066         switch (source) {
5067         case NI_RTSI_OUTPUT_ADR_START1:
5068         case NI_RTSI_OUTPUT_ADR_START2:
5069         case NI_RTSI_OUTPUT_SCLKG:
5070         case NI_RTSI_OUTPUT_DACUPDN:
5071         case NI_RTSI_OUTPUT_DA_START1:
5072         case NI_RTSI_OUTPUT_G_SRC0:
5073         case NI_RTSI_OUTPUT_G_GATE0:
5074         case NI_RTSI_OUTPUT_RGOUT0:
5075         case NI_RTSI_OUTPUT_RTSI_BRD(0):
5076         case NI_RTSI_OUTPUT_RTSI_BRD(1):
5077         case NI_RTSI_OUTPUT_RTSI_BRD(2):
5078         case NI_RTSI_OUTPUT_RTSI_BRD(3):
5079                 return 1;
5080         case NI_RTSI_OUTPUT_RTSI_OSC:
5081                 return (devpriv->is_m_series) ? 1 : 0;
5082         default:
5083                 return 0;
5084         }
5085 }
5086 
5087 static int ni_set_rtsi_routing(struct comedi_device *dev,
5088                                unsigned int chan, unsigned int src)
5089 {
5090         struct ni_private *devpriv = dev->private;
5091 
5092         if (chan >= TRIGGER_LINE(0))
5093                 /* allow new and old names of rtsi channels to work. */
5094                 chan -= TRIGGER_LINE(0);
5095 
5096         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5097                 return -EINVAL;
5098         if (chan < 4) {
5099                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5100                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5101                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5102                               NISTC_RTSI_TRIGA_OUT_REG);
5103         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5104                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5105                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5106                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5107                               NISTC_RTSI_TRIGB_OUT_REG);
5108         } else if (chan != NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5109                 /* probably should never reach this, since the
5110                  * ni_valid_rtsi_output_source above errors out if chan is too
5111                  * high
5112                  */
5113                 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5114                 return -EINVAL;
5115         }
5116         return 2;
5117 }
5118 
5119 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5120                                         unsigned int chan)
5121 {
5122         struct ni_private *devpriv = dev->private;
5123 
5124         if (chan >= TRIGGER_LINE(0))
5125                 /* allow new and old names of rtsi channels to work. */
5126                 chan -= TRIGGER_LINE(0);
5127 
5128         if (chan < 4) {
5129                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5130                                               devpriv->rtsi_trig_a_output_reg);
5131         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5132                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5133                                               devpriv->rtsi_trig_b_output_reg);
5134         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5135                 return NI_RTSI_OUTPUT_RTSI_OSC;
5136         }
5137 
5138         dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5139         return -EINVAL;
5140 }
5141 
5142 static void ni_set_rtsi_direction(struct comedi_device *dev, int chan,
5143                                   unsigned int direction)
5144 {
5145         struct ni_private *devpriv = dev->private;
5146         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5147 
5148         if (chan >= TRIGGER_LINE(0))
5149                 /* allow new and old names of rtsi channels to work. */
5150                 chan -= TRIGGER_LINE(0);
5151 
5152         if (direction == COMEDI_OUTPUT) {
5153                 if (chan < max_chan) {
5154                         devpriv->rtsi_trig_direction_reg |=
5155                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5156                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5157                         devpriv->rtsi_trig_direction_reg |=
5158                             NISTC_RTSI_TRIG_DRV_CLK;
5159                 }
5160         } else {
5161                 if (chan < max_chan) {
5162                         devpriv->rtsi_trig_direction_reg &=
5163                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5164                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5165                         devpriv->rtsi_trig_direction_reg &=
5166                             ~NISTC_RTSI_TRIG_DRV_CLK;
5167                 }
5168         }
5169         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5170                       NISTC_RTSI_TRIG_DIR_REG);
5171 }
5172 
5173 static int ni_get_rtsi_direction(struct comedi_device *dev, int chan)
5174 {
5175         struct ni_private *devpriv = dev->private;
5176         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5177 
5178         if (chan >= TRIGGER_LINE(0))
5179                 /* allow new and old names of rtsi channels to work. */
5180                 chan -= TRIGGER_LINE(0);
5181 
5182         if (chan < max_chan) {
5183                 return (devpriv->rtsi_trig_direction_reg &
5184                         NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5185                            ? COMEDI_OUTPUT : COMEDI_INPUT;
5186         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5187                 return (devpriv->rtsi_trig_direction_reg &
5188                         NISTC_RTSI_TRIG_DRV_CLK)
5189                            ? COMEDI_OUTPUT : COMEDI_INPUT;
5190         }
5191         return -EINVAL;
5192 }
5193 
5194 static int ni_rtsi_insn_config(struct comedi_device *dev,
5195                                struct comedi_subdevice *s,
5196                                struct comedi_insn *insn,
5197                                unsigned int *data)
5198 {
5199         struct ni_private *devpriv = dev->private;
5200         unsigned int chan = CR_CHAN(insn->chanspec);
5201 
5202         switch (data[0]) {
5203         case COMEDI_OUTPUT:
5204         case COMEDI_INPUT:
5205                 ni_set_rtsi_direction(dev, chan, data[0]);
5206                 break;
5207         case INSN_CONFIG_DIO_QUERY: {
5208                 int ret = ni_get_rtsi_direction(dev, chan);
5209 
5210                 if (ret < 0)
5211                         return ret;
5212                 data[1] = ret;
5213                 return 2;
5214         }
5215         case INSN_CONFIG_SET_CLOCK_SRC:
5216                 return ni_set_master_clock(dev, data[1], data[2]);
5217         case INSN_CONFIG_GET_CLOCK_SRC:
5218                 data[1] = devpriv->clock_source;
5219                 data[2] = devpriv->clock_ns;
5220                 return 3;
5221         case INSN_CONFIG_SET_ROUTING:
5222                 return ni_set_rtsi_routing(dev, chan, data[1]);
5223         case INSN_CONFIG_GET_ROUTING: {
5224                 int ret = ni_get_rtsi_routing(dev, chan);
5225 
5226                 if (ret < 0)
5227                         return ret;
5228                 data[1] = ret;
5229                 return 2;
5230         }
5231         default:
5232                 return -EINVAL;
5233         }
5234         return 1;
5235 }
5236 
5237 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5238                              struct comedi_subdevice *s,
5239                              struct comedi_insn *insn,
5240                              unsigned int *data)
5241 {
5242         data[1] = 0;
5243 
5244         return insn->n;
5245 }
5246 
5247 /*
5248  * Default routing for RTSI trigger lines.
5249  *
5250  * These values are used here in the init function, as well as in the
5251  * disconnect_route function, after a RTSI route has been disconnected.
5252  */
5253 static const int default_rtsi_routing[] = {
5254         [0] = NI_RTSI_OUTPUT_ADR_START1,
5255         [1] = NI_RTSI_OUTPUT_ADR_START2,
5256         [2] = NI_RTSI_OUTPUT_SCLKG,
5257         [3] = NI_RTSI_OUTPUT_DACUPDN,
5258         [4] = NI_RTSI_OUTPUT_DA_START1,
5259         [5] = NI_RTSI_OUTPUT_G_SRC0,
5260         [6] = NI_RTSI_OUTPUT_G_GATE0,
5261         [7] = NI_RTSI_OUTPUT_RTSI_OSC,
5262 };
5263 
5264 /*
5265  * Route signals through RGOUT0 terminal.
5266  * @reg: raw register value of RGOUT0 bits (only bit0 is important).
5267  * @dev: comedi device handle.
5268  */
5269 static void set_rgout0_reg(int reg, struct comedi_device *dev)
5270 {
5271         struct ni_private *devpriv = dev->private;
5272 
5273         if (devpriv->is_m_series) {
5274                 devpriv->rtsi_trig_direction_reg &=
5275                         ~NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5276                 devpriv->rtsi_trig_direction_reg |=
5277                         (reg << NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT) &
5278                         NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5279                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5280                               NISTC_RTSI_TRIG_DIR_REG);
5281         } else {
5282                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIGB_SUB_SEL1;
5283                 devpriv->rtsi_trig_b_output_reg |=
5284                         (reg << NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT) &
5285                         NISTC_RTSI_TRIGB_SUB_SEL1;
5286                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5287                               NISTC_RTSI_TRIGB_OUT_REG);
5288         }
5289 }
5290 
5291 static int get_rgout0_reg(struct comedi_device *dev)
5292 {
5293         struct ni_private *devpriv = dev->private;
5294         int reg;
5295 
5296         if (devpriv->is_m_series)
5297                 reg = (devpriv->rtsi_trig_direction_reg &
5298                        NISTC_RTSI_TRIG_DIR_SUB_SEL1)
5299                     >> NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT;
5300         else
5301                 reg = (devpriv->rtsi_trig_b_output_reg &
5302                        NISTC_RTSI_TRIGB_SUB_SEL1)
5303                     >> NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT;
5304         return reg;
5305 }
5306 
5307 static inline int get_rgout0_src(struct comedi_device *dev)
5308 {
5309         struct ni_private *devpriv = dev->private;
5310         int reg = get_rgout0_reg(dev);
5311 
5312         return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables);
5313 }
5314 
5315 /*
5316  * Route signals through RGOUT0 terminal and increment the RGOUT0 use for this
5317  * particular route.
5318  * @src: device-global signal name
5319  * @dev: comedi device handle
5320  *
5321  * Return: -EINVAL if the source is not valid to route to RGOUT0;
5322  *         -EBUSY if the RGOUT0 is already used;
5323  *         0 if successful.
5324  */
5325 static int incr_rgout0_src_use(int src, struct comedi_device *dev)
5326 {
5327         struct ni_private *devpriv = dev->private;
5328         s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5329                                           &devpriv->routing_tables);
5330 
5331         if (reg < 0)
5332                 return -EINVAL;
5333 
5334         if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg)
5335                 return -EBUSY;
5336 
5337         ++devpriv->rgout0_usage;
5338         set_rgout0_reg(reg, dev);
5339         return 0;
5340 }
5341 
5342 /*
5343  * Unroute signals through RGOUT0 terminal and deccrement the RGOUT0 use for
5344  * this particular source.  This function does not actually unroute anything
5345  * with respect to RGOUT0.  It does, on the other hand, decrement the usage
5346  * counter for the current src->RGOUT0 mapping.
5347  *
5348  * Return: -EINVAL if the source is not already routed to RGOUT0 (or usage is
5349  *      already at zero); 0 if successful.
5350  */
5351 static int decr_rgout0_src_use(int src, struct comedi_device *dev)
5352 {
5353         struct ni_private *devpriv = dev->private;
5354         s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5355                                           &devpriv->routing_tables);
5356 
5357         if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) {
5358                 --devpriv->rgout0_usage;
5359                 if (!devpriv->rgout0_usage)
5360                         set_rgout0_reg(0, dev); /* ok default? */
5361                 return 0;
5362         }
5363         return -EINVAL;
5364 }
5365 
5366 /*
5367  * Route signals through given NI_RTSI_BRD mux.
5368  * @i: index of mux to route
5369  * @reg: raw register value of RTSI_BRD bits
5370  * @dev: comedi device handle
5371  */
5372 static void set_ith_rtsi_brd_reg(int i, int reg, struct comedi_device *dev)
5373 {
5374         struct ni_private *devpriv = dev->private;
5375         int reg_i_sz = 3; /* value for e-series */
5376         int reg_i_mask;
5377         int reg_i_shift;
5378 
5379         if (devpriv->is_m_series)
5380                 reg_i_sz = 4;
5381         reg_i_mask = ~((~0) << reg_i_sz);
5382         reg_i_shift = i * reg_i_sz;
5383 
5384         /* clear out the current reg_i for ith brd */
5385         devpriv->rtsi_shared_mux_reg &= ~(reg_i_mask       << reg_i_shift);
5386         /* (softcopy) write the new reg_i for ith brd */
5387         devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift;
5388         /* (hardcopy) write the new reg_i for ith brd */
5389         ni_stc_writew(dev, devpriv->rtsi_shared_mux_reg, NISTC_RTSI_BOARD_REG);
5390 }
5391 
5392 static int get_ith_rtsi_brd_reg(int i, struct comedi_device *dev)
5393 {
5394         struct ni_private *devpriv = dev->private;
5395         int reg_i_sz = 3; /* value for e-series */
5396         int reg_i_mask;
5397         int reg_i_shift;
5398 
5399         if (devpriv->is_m_series)
5400                 reg_i_sz = 4;
5401         reg_i_mask = ~((~0) << reg_i_sz);
5402         reg_i_shift = i * reg_i_sz;
5403 
5404         return (devpriv->rtsi_shared_mux_reg >> reg_i_shift) & reg_i_mask;
5405 }
5406 
5407 static inline int get_rtsi_brd_src(int brd, struct comedi_device *dev)
5408 {
5409         struct ni_private *devpriv = dev->private;
5410         int brd_index = brd;
5411         int reg;
5412 
5413         if (brd >= NI_RTSI_BRD(0))
5414                 brd_index = brd - NI_RTSI_BRD(0);
5415         else
5416                 brd = NI_RTSI_BRD(brd);
5417         /*
5418          * And now:
5419          * brd : device-global name
5420          * brd_index : index number of RTSI_BRD mux
5421          */
5422 
5423         reg = get_ith_rtsi_brd_reg(brd_index, dev);
5424 
5425         return ni_find_route_source(reg, brd, &devpriv->routing_tables);
5426 }
5427 
5428 /*
5429  * Route signals through NI_RTSI_BRD mux and increment the use counter for this
5430  * particular route.
5431  *
5432  * Return: -EINVAL if the source is not valid to route to NI_RTSI_BRD(i);
5433  *         -EBUSY if all NI_RTSI_BRD muxes are already used;
5434  *         NI_RTSI_BRD(i) of allocated ith mux if successful.
5435  */
5436 static int incr_rtsi_brd_src_use(int src, struct comedi_device *dev)
5437 {
5438         struct ni_private *devpriv = dev->private;
5439         int first_available = -1;
5440         int err = -EINVAL;
5441         s8 reg;
5442         int i;
5443 
5444         /* first look for a mux that is already configured to provide src */
5445         for (i = 0; i < NUM_RTSI_SHARED_MUXS; ++i) {
5446                 reg = ni_lookup_route_register(CR_CHAN(src), NI_RTSI_BRD(i),
5447                                                &devpriv->routing_tables);
5448 
5449                 if (reg < 0)
5450                         continue; /* invalid route */
5451 
5452                 if (!devpriv->rtsi_shared_mux_usage[i]) {
5453                         if (first_available < 0)
5454                                 /* found the first unused, but usable mux */
5455                                 first_available = i;
5456                 } else {
5457                         /*
5458                          * we've seen at least one possible route, so change the
5459                          * final error to -EBUSY in case there are no muxes
5460                          * available.
5461                          */
5462                         err = -EBUSY;
5463 
5464                         if (get_ith_rtsi_brd_reg(i, dev) == reg) {
5465                                 /*
5466                                  * we've found a mux that is already being used
5467                                  * to provide the requested signal.  Reuse it.
5468                                  */
5469                                 goto success;
5470                         }
5471                 }
5472         }
5473 
5474         if (first_available < 0)
5475                 return err;
5476 
5477         /* we did not find a mux to reuse, but there is at least one usable */
5478         i = first_available;
5479 
5480 success:
5481         ++devpriv->rtsi_shared_mux_usage[i];
5482         set_ith_rtsi_brd_reg(i, reg, dev);
5483         return NI_RTSI_BRD(i);
5484 }
5485 
5486 /*
5487  * Unroute signals through NI_RTSI_BRD mux and decrement the user counter for
5488  * this particular route.
5489  *
5490  * Return: -EINVAL if the source is not already routed to rtsi_brd(i) (or usage
5491  *      is already at zero); 0 if successful.
5492  */
5493 static int decr_rtsi_brd_src_use(int src, int rtsi_brd,
5494                                  struct comedi_device *dev)
5495 {
5496         struct ni_private *devpriv = dev->private;
5497         s8 reg = ni_lookup_route_register(CR_CHAN(src), rtsi_brd,
5498                                           &devpriv->routing_tables);
5499         const int i = rtsi_brd - NI_RTSI_BRD(0);
5500 
5501         if (devpriv->rtsi_shared_mux_usage[i] > 0 &&
5502             get_ith_rtsi_brd_reg(i, dev) == reg) {
5503                 --devpriv->rtsi_shared_mux_usage[i];
5504                 if (!devpriv->rtsi_shared_mux_usage[i])
5505                         set_ith_rtsi_brd_reg(i, 0, dev); /* ok default? */
5506                 return 0;
5507         }
5508 
5509         return -EINVAL;
5510 }
5511 
5512 static void ni_rtsi_init(struct comedi_device *dev)
5513 {
5514         struct ni_private *devpriv = dev->private;
5515         int i;
5516 
5517         /*  Initialises the RTSI bus signal switch to a default state */
5518 
5519         /*
5520          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5521          * to have no effect, at least on pxi-6281, which always uses
5522          * 20MHz rtsi clock frequency
5523          */
5524         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5525         /*  Set clock mode to internal */
5526         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5527                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5528 
5529         /* default internal lines routing to RTSI bus lines */
5530         for (i = 0; i < 8; ++i) {
5531                 ni_set_rtsi_direction(dev, i, COMEDI_INPUT);
5532                 ni_set_rtsi_routing(dev, i, default_rtsi_routing[i]);
5533         }
5534 
5535         /*
5536          * Sets the source and direction of the 4 on board lines.
5537          * This configures all board lines to be:
5538          * for e-series:
5539          *   1) inputs (not sure what "output" would mean)
5540          *   2) copying TRIGGER_LINE(0) (or RTSI0) output
5541          * for m-series:
5542          *   copying NI_PFI(0) output
5543          */
5544         devpriv->rtsi_shared_mux_reg = 0;
5545         for (i = 0; i < 4; ++i)
5546                 set_ith_rtsi_brd_reg(i, 0, dev);
5547         memset(devpriv->rtsi_shared_mux_usage, 0,
5548                sizeof(devpriv->rtsi_shared_mux_usage));
5549 
5550         /* initialize rgout0 pin as unused. */
5551         devpriv->rgout0_usage = 0;
5552         set_rgout0_reg(0, dev);
5553 }
5554 
5555 /* Get route of GPFO_i/CtrOut pins */
5556 static inline int ni_get_gout_routing(unsigned int dest,
5557                                       struct comedi_device *dev)
5558 {
5559         struct ni_private *devpriv = dev->private;
5560         unsigned int reg = devpriv->an_trig_etc_reg;
5561 
5562         switch (dest) {
5563         case 0:
5564                 if (reg & NISTC_ATRIG_ETC_GPFO_0_ENA)
5565                         return NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(reg);
5566                 break;
5567         case 1:
5568                 if (reg & NISTC_ATRIG_ETC_GPFO_1_ENA)
5569                         return NISTC_ATRIG_ETC_GPFO_1_SEL_TO_SRC(reg);
5570                 break;
5571         }
5572 
5573         return -EINVAL;
5574 }
5575 
5576 /* Set route of GPFO_i/CtrOut pins */
5577 static inline int ni_disable_gout_routing(unsigned int dest,
5578                                           struct comedi_device *dev)
5579 {
5580         struct ni_private *devpriv = dev->private;
5581 
5582         switch (dest) {
5583         case 0:
5584                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_ENA;
5585                 break;
5586         case 1:
5587                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_ENA;
5588                 break;
5589         default:
5590                 return -EINVAL;
5591         }
5592 
5593         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5594         return 0;
5595 }
5596 
5597 /* Set route of GPFO_i/CtrOut pins */
5598 static inline int ni_set_gout_routing(unsigned int src, unsigned int dest,
5599                                       struct comedi_device *dev)
5600 {
5601         struct ni_private *devpriv = dev->private;
5602 
5603         switch (dest) {
5604         case 0:
5605                 /* clear reg */
5606                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_SEL(-1);
5607                 /* set reg */
5608                 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_0_ENA
5609                                          |  NISTC_ATRIG_ETC_GPFO_0_SEL(src);
5610                 break;
5611         case 1:
5612                 /* clear reg */
5613                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_SEL;
5614                 src = src ? NISTC_ATRIG_ETC_GPFO_1_SEL : 0;
5615                 /* set reg */
5616                 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_1_ENA | src;
5617                 break;
5618         default:
5619                 return -EINVAL;
5620         }
5621 
5622         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5623         return 0;
5624 }
5625 
5626 /*
5627  * Retrieves the current source of the output selector for the given
5628  * destination.  If the terminal for the destination is not already configured
5629  * as an output, this function returns -EINVAL as error.
5630  *
5631  * Return: the register value of the destination output selector;
5632  *         -EINVAL if terminal is not configured for output.
5633  */
5634 static int get_output_select_source(int dest, struct comedi_device *dev)
5635 {
5636         struct ni_private *devpriv = dev->private;
5637         int reg = -1;
5638 
5639         if (channel_is_pfi(dest)) {
5640                 if (ni_get_pfi_direction(dev, dest) == COMEDI_OUTPUT)
5641                         reg = ni_get_pfi_routing(dev, dest);
5642         } else if (channel_is_rtsi(dest)) {
5643                 if (ni_get_rtsi_direction(dev, dest) == COMEDI_OUTPUT) {
5644                         reg = ni_get_rtsi_routing(dev, dest);
5645 
5646                         if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5647                                 dest = NI_RGOUT0; /* prepare for lookup below */
5648                                 reg = get_rgout0_reg(dev);
5649                         } else if (reg >= NI_RTSI_OUTPUT_RTSI_BRD(0) &&
5650                                    reg <= NI_RTSI_OUTPUT_RTSI_BRD(3)) {
5651                                 const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0);
5652 
5653                                 dest = NI_RTSI_BRD(i); /* prepare for lookup */
5654                                 reg = get_ith_rtsi_brd_reg(i, dev);
5655                         }
5656                 }
5657         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5658                 /*
5659                  * not handled by ni_tio.  Only available for GPFO registers in
5660                  * e/m series.
5661                  */
5662                 dest -= NI_CtrOut(0);
5663                 if (dest > 1)
5664                         /* there are only two g_out outputs. */
5665                         return -EINVAL;
5666                 reg = ni_get_gout_routing(dest, dev);
5667         } else if (channel_is_ctr(dest)) {
5668                 reg = ni_tio_get_routing(devpriv->counter_dev, dest);
5669         } else {
5670                 dev_dbg(dev->class_dev, "%s: unhandled destination (%d) queried\n",
5671                         __func__, dest);
5672         }
5673 
5674         if (reg >= 0)
5675                 return ni_find_route_source(CR_CHAN(reg), dest,
5676                                             &devpriv->routing_tables);
5677         return -EINVAL;
5678 }
5679 
5680 /*
5681  * Test a route:
5682  *
5683  * Return: -1 if not connectible;
5684  *          0 if connectible and not connected;
5685  *          1 if connectible and connected.
5686  */
5687 static int test_route(unsigned int src, unsigned int dest,
5688                       struct comedi_device *dev)
5689 {
5690         struct ni_private *devpriv = dev->private;
5691         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5692                                       &devpriv->routing_tables);
5693 
5694         if (reg < 0)
5695                 return -1;
5696         if (get_output_select_source(dest, dev) != CR_CHAN(src))
5697                 return 0;
5698         return 1;
5699 }
5700 
5701 /* Connect the actual route.  */
5702 static int connect_route(unsigned int src, unsigned int dest,
5703                          struct comedi_device *dev)
5704 {
5705         struct ni_private *devpriv = dev->private;
5706         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5707                                       &devpriv->routing_tables);
5708         s8 current_src;
5709 
5710         if (reg < 0)
5711                 /* route is not valid */
5712                 return -EINVAL;
5713 
5714         current_src = get_output_select_source(dest, dev);
5715         if (current_src == CR_CHAN(src))
5716                 return -EALREADY;
5717         if (current_src >= 0)
5718                 /* destination mux is already busy. complain, don't overwrite */
5719                 return -EBUSY;
5720 
5721         /* The route is valid and available. Now connect... */
5722         if (channel_is_pfi(dest)) {
5723                 /* set routing source, then open output */
5724                 ni_set_pfi_routing(dev, dest, reg);
5725                 ni_set_pfi_direction(dev, dest, COMEDI_OUTPUT);
5726         } else if (channel_is_rtsi(dest)) {
5727                 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5728                         int ret = incr_rgout0_src_use(src, dev);
5729 
5730                         if (ret < 0)
5731                                 return ret;
5732                 } else if (ni_rtsi_route_requires_mux(reg)) {
5733                         /* Attempt to allocate and  route (src->brd) */
5734                         int brd = incr_rtsi_brd_src_use(src, dev);
5735 
5736                         if (brd < 0)
5737                                 return brd;
5738 
5739                         /* Now lookup the register value for (brd->dest) */
5740                         reg = ni_lookup_route_register(
5741                                 brd, dest, &devpriv->routing_tables);
5742                 }
5743 
5744                 ni_set_rtsi_direction(dev, dest, COMEDI_OUTPUT);
5745                 ni_set_rtsi_routing(dev, dest, reg);
5746         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5747                 /*
5748                  * not handled by ni_tio.  Only available for GPFO registers in
5749                  * e/m series.
5750                  */
5751                 dest -= NI_CtrOut(0);
5752                 if (dest > 1)
5753                         /* there are only two g_out outputs. */
5754                         return -EINVAL;
5755                 if (ni_set_gout_routing(src, dest, dev))
5756                         return -EINVAL;
5757         } else if (channel_is_ctr(dest)) {
5758                 /*
5759                  * we are adding back the channel modifier info to set
5760                  * invert/edge info passed by the user
5761                  */
5762                 ni_tio_set_routing(devpriv->counter_dev, dest,
5763                                    reg | (src & ~CR_CHAN(-1)));
5764         } else {
5765                 return -EINVAL;
5766         }
5767         return 0;
5768 }
5769 
5770 static int disconnect_route(unsigned int src, unsigned int dest,
5771                             struct comedi_device *dev)
5772 {
5773         struct ni_private *devpriv = dev->private;
5774         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5775                                       &devpriv->routing_tables);
5776 
5777         if (reg < 0)
5778                 /* route is not valid */
5779                 return -EINVAL;
5780         if (get_output_select_source(dest, dev) != src)
5781                 /* cannot disconnect something not connected */
5782                 return -EINVAL;
5783 
5784         /* The route is valid and is connected.  Now disconnect... */
5785         if (channel_is_pfi(dest)) {
5786                 /* set the pfi to high impedance, and disconnect */
5787                 ni_set_pfi_direction(dev, dest, COMEDI_INPUT);
5788                 ni_set_pfi_routing(dev, dest, NI_PFI_OUTPUT_PFI_DEFAULT);
5789         } else if (channel_is_rtsi(dest)) {
5790                 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5791                         int ret = decr_rgout0_src_use(src, dev);
5792 
5793                         if (ret < 0)
5794                                 return ret;
5795                 } else if (ni_rtsi_route_requires_mux(reg)) {
5796                         /* find which RTSI_BRD line is source for rtsi pin */
5797                         int brd = ni_find_route_source(
5798                                 ni_get_rtsi_routing(dev, dest), dest,
5799                                 &devpriv->routing_tables);
5800 
5801                         if (brd < 0)
5802                                 return brd;
5803 
5804                         /* decrement/disconnect RTSI_BRD line from source */
5805                         decr_rtsi_brd_src_use(src, brd, dev);
5806                 }
5807 
5808                 /* set rtsi output selector to default state */
5809                 reg = default_rtsi_routing[dest - TRIGGER_LINE(0)];
5810                 ni_set_rtsi_direction(dev, dest, COMEDI_INPUT);
5811                 ni_set_rtsi_routing(dev, dest, reg);
5812         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5813                 /*
5814                  * not handled by ni_tio.  Only available for GPFO registers in
5815                  * e/m series.
5816                  */
5817                 dest -= NI_CtrOut(0);
5818                 if (dest > 1)
5819                         /* there are only two g_out outputs. */
5820                         return -EINVAL;
5821                 reg = ni_disable_gout_routing(dest, dev);
5822         } else if (channel_is_ctr(dest)) {
5823                 ni_tio_unset_routing(devpriv->counter_dev, dest);
5824         } else {
5825                 return -EINVAL;
5826         }
5827         return 0;
5828 }
5829 
5830 static int ni_global_insn_config(struct comedi_device *dev,
5831                                  struct comedi_insn *insn,
5832                                  unsigned int *data)
5833 {
5834         switch (data[0]) {
5835         case INSN_DEVICE_CONFIG_TEST_ROUTE:
5836                 data[0] = test_route(data[1], data[2], dev);
5837                 return 2;
5838         case INSN_DEVICE_CONFIG_CONNECT_ROUTE:
5839                 return connect_route(data[1], data[2], dev);
5840         case INSN_DEVICE_CONFIG_DISCONNECT_ROUTE:
5841                 return disconnect_route(data[1], data[2], dev);
5842         /*
5843          * This case is already handled one level up.
5844          * case INSN_DEVICE_CONFIG_GET_ROUTES:
5845          */
5846         default:
5847                 return -EINVAL;
5848         }
5849         return 1;
5850 }
5851 
5852 #ifdef PCIDMA
5853 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5854 {
5855         struct ni_gpct *counter = s->private;
5856         int retval;
5857 
5858         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5859                                               COMEDI_INPUT);
5860         if (retval) {
5861                 dev_err(dev->class_dev,
5862                         "no dma channel available for use by counter\n");
5863                 return retval;
5864         }
5865         ni_tio_acknowledge(counter);
5866         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5867 
5868         return ni_tio_cmd(dev, s);
5869 }
5870 
5871 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5872 {
5873         struct ni_gpct *counter = s->private;
5874         int retval;
5875 
5876         retval = ni_tio_cancel(counter);
5877         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5878         ni_release_gpct_mite_channel(dev, counter->counter_index);
5879         return retval;
5880 }
5881 #endif
5882 
5883 static irqreturn_t ni_E_interrupt(int irq, void *d)
5884 {
5885         struct comedi_device *dev = d;
5886         struct comedi_subdevice *s_ai = dev->read_subdev;
5887         struct comedi_subdevice *s_ao = dev->write_subdev;
5888         unsigned short a_status;
5889         unsigned short b_status;
5890         unsigned long flags;
5891 #ifdef PCIDMA
5892         struct ni_private *devpriv = dev->private;
5893 #endif
5894 
5895         if (!dev->attached)
5896                 return IRQ_NONE;
5897         smp_mb();               /* make sure dev->attached is checked */
5898 
5899         /*  lock to avoid race with comedi_poll */
5900         spin_lock_irqsave(&dev->spinlock, flags);
5901         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5902         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5903 #ifdef PCIDMA
5904         if (devpriv->mite) {
5905                 unsigned long flags_too;
5906 
5907                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5908                 if (s_ai && devpriv->ai_mite_chan)
5909                         mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5910                 if (s_ao && devpriv->ao_mite_chan)
5911                         mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5912                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5913         }
5914 #endif
5915         ack_a_interrupt(dev, a_status);
5916         ack_b_interrupt(dev, b_status);
5917         if (s_ai) {
5918                 if (a_status & NISTC_AI_STATUS1_INTA)
5919                         handle_a_interrupt(dev, s_ai, a_status);
5920                 /* handle any interrupt or dma events */
5921                 comedi_handle_events(dev, s_ai);
5922         }
5923         if (s_ao) {
5924                 if (b_status & NISTC_AO_STATUS1_INTB)
5925                         handle_b_interrupt(dev, s_ao, b_status);
5926                 /* handle any interrupt or dma events */
5927                 comedi_handle_events(dev, s_ao);
5928         }
5929         handle_gpct_interrupt(dev, 0);
5930         handle_gpct_interrupt(dev, 1);
5931 #ifdef PCIDMA
5932         if (devpriv->is_m_series)
5933                 handle_cdio_interrupt(dev);
5934 #endif
5935 
5936         spin_unlock_irqrestore(&dev->spinlock, flags);
5937         return IRQ_HANDLED;
5938 }
5939 
5940 static int ni_alloc_private(struct comedi_device *dev)
5941 {
5942         struct ni_private *devpriv;
5943 
5944         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5945         if (!devpriv)
5946                 return -ENOMEM;
5947 
5948         spin_lock_init(&devpriv->window_lock);
5949         spin_lock_init(&devpriv->soft_reg_copy_lock);
5950         spin_lock_init(&devpriv->mite_channel_lock);
5951 
5952         return 0;
5953 }
5954 
5955 static unsigned int _ni_get_valid_routes(struct comedi_device *dev,
5956                                          unsigned int n_pairs,
5957                                          unsigned int *pair_data)
5958 {
5959         struct ni_private *devpriv = dev->private;
5960 
5961         return ni_get_valid_routes(&devpriv->routing_tables, n_pairs,
5962                                    pair_data);
5963 }
5964 
5965 static int ni_E_init(struct comedi_device *dev,
5966                      unsigned int interrupt_pin, unsigned int irq_polarity)
5967 {
5968         const struct ni_board_struct *board = dev->board_ptr;
5969         struct ni_private *devpriv = dev->private;
5970         struct comedi_subdevice *s;
5971         int ret;
5972         int i;
5973         const char *dev_family = devpriv->is_m_series ? "ni_mseries"
5974                                                       : "ni_eseries";
5975 
5976         /* prepare the device for globally-named routes. */
5977         if (ni_assign_device_routes(dev_family, board->name,
5978                                     &devpriv->routing_tables) < 0) {
5979                 dev_warn(dev->class_dev, "%s: %s device has no signal routing table.\n",
5980                          __func__, board->name);
5981                 dev_warn(dev->class_dev, "%s: High level NI signal names will not be available for this %s board.\n",
5982                          __func__, board->name);
5983         } else {
5984                 /*
5985                  * only(?) assign insn_device_config if we have global names for
5986                  * this device.
5987                  */
5988                 dev->insn_device_config = ni_global_insn_config;
5989                 dev->get_valid_routes = _ni_get_valid_routes;
5990         }
5991 
5992         if (board->n_aochan > MAX_N_AO_CHAN) {
5993                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5994                 return -EINVAL;
5995         }
5996 
5997         /* initialize clock dividers */
5998         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5999                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
6000                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
6001                                   NISTC_CLK_FOUT_TO_BOARD;
6002         if (!devpriv->is_6xxx) {
6003                 /* BEAM is this needed for PCI-6143 ?? */
6004                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
6005                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
6006         }
6007         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
6008 
6009         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
6010         if (ret)
6011                 return ret;
6012 
6013         /* Analog Input subdevice */
6014         s = &dev->subdevices[NI_AI_SUBDEV];
6015         if (board->n_adchan) {
6016                 s->type         = COMEDI_SUBD_AI;
6017                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
6018                 if (!devpriv->is_611x)
6019                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
6020                 if (board->ai_maxdata > 0xffff)
6021                         s->subdev_flags |= SDF_LSAMPL;
6022                 if (devpriv->is_m_series)
6023                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
6024                 s->n_chan       = board->n_adchan;
6025                 s->maxdata      = board->ai_maxdata;
6026                 s->range_table  = ni_range_lkup[board->gainlkup];
6027                 s->insn_read    = ni_ai_insn_read;
6028                 s->insn_config  = ni_ai_insn_config;
6029                 if (dev->irq) {
6030                         dev->read_subdev = s;
6031                         s->subdev_flags |= SDF_CMD_READ;
6032                         s->len_chanlist = 512;
6033                         s->do_cmdtest   = ni_ai_cmdtest;
6034                         s->do_cmd       = ni_ai_cmd;
6035                         s->cancel       = ni_ai_reset;
6036                         s->poll         = ni_ai_poll;
6037                         s->munge        = ni_ai_munge;
6038 
6039                         if (devpriv->mite)
6040                                 s->async_dma_dir = DMA_FROM_DEVICE;
6041                 }
6042 
6043                 /* reset the analog input configuration */
6044                 ni_ai_reset(dev, s);
6045         } else {
6046                 s->type         = COMEDI_SUBD_UNUSED;
6047         }
6048 
6049         /* Analog Output subdevice */
6050         s = &dev->subdevices[NI_AO_SUBDEV];
6051         if (board->n_aochan) {
6052                 s->type         = COMEDI_SUBD_AO;
6053                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
6054                 if (devpriv->is_m_series)
6055                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
6056                 s->n_chan       = board->n_aochan;
6057                 s->maxdata      = board->ao_maxdata;
6058                 s->range_table  = board->ao_range_table;
6059                 s->insn_config  = ni_ao_insn_config;
6060                 s->insn_write   = ni_ao_insn_write;
6061 
6062                 ret = comedi_alloc_subdev_readback(s);
6063                 if (ret)
6064                         return ret;
6065 
6066                 /*
6067                  * Along with the IRQ we need either a FIFO or DMA for
6068                  * async command support.
6069                  */
6070                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
6071                         dev->write_subdev = s;
6072                         s->subdev_flags |= SDF_CMD_WRITE;
6073                         s->len_chanlist = s->n_chan;
6074                         s->do_cmdtest   = ni_ao_cmdtest;
6075                         s->do_cmd       = ni_ao_cmd;
6076                         s->cancel       = ni_ao_reset;
6077                         if (!devpriv->is_m_series)
6078                                 s->munge        = ni_ao_munge;
6079 
6080                         if (devpriv->mite)
6081                                 s->async_dma_dir = DMA_TO_DEVICE;
6082                 }
6083 
6084                 if (devpriv->is_67xx)
6085                         init_ao_67xx(dev, s);
6086 
6087                 /* reset the analog output configuration */
6088                 ni_ao_reset(dev, s);
6089         } else {
6090                 s->type         = COMEDI_SUBD_UNUSED;
6091         }
6092 
6093         /* Digital I/O subdevice */
6094         s = &dev->subdevices[NI_DIO_SUBDEV];
6095         s->type         = COMEDI_SUBD_DIO;
6096         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
6097         s->n_chan       = board->has_32dio_chan ? 32 : 8;
6098         s->maxdata      = 1;
6099         s->range_table  = &range_digital;
6100         if (devpriv->is_m_series) {
6101 #ifdef PCIDMA
6102                 s->subdev_flags |= SDF_LSAMPL;
6103                 s->insn_bits    = ni_m_series_dio_insn_bits;
6104                 s->insn_config  = ni_m_series_dio_insn_config;
6105                 if (dev->irq) {
6106                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
6107                         s->len_chanlist = s->n_chan;
6108                         s->do_cmdtest   = ni_cdio_cmdtest;
6109                         s->do_cmd       = ni_cdio_cmd;
6110                         s->cancel       = ni_cdio_cancel;
6111 
6112                         /* M-series boards use DMA */
6113                         s->async_dma_dir = DMA_BIDIRECTIONAL;
6114                 }
6115 
6116                 /* reset DIO and set all channels to inputs */
6117                 ni_writel(dev, NI_M_CDO_CMD_RESET |
6118                                NI_M_CDI_CMD_RESET,
6119                           NI_M_CDIO_CMD_REG);
6120                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
6121 #endif /* PCIDMA */
6122         } else {
6123                 s->insn_bits    = ni_dio_insn_bits;
6124                 s->insn_config  = ni_dio_insn_config;
6125 
6126                 /* set all channels to inputs */
6127                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
6128                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
6129         }
6130 
6131         /* 8255 device */
6132         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
6133         if (board->has_8255) {
6134                 ret = subdev_8255_init(dev, s, ni_8255_callback,
6135                                        NI_E_8255_BASE);
6136                 if (ret)
6137                         return ret;
6138         } else {
6139                 s->type = COMEDI_SUBD_UNUSED;
6140         }
6141 
6142         /* formerly general purpose counter/timer device, but no longer used */
6143         s = &dev->subdevices[NI_UNUSED_SUBDEV];
6144         s->type = COMEDI_SUBD_UNUSED;
6145 
6146         /* Calibration subdevice */
6147         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
6148         s->type         = COMEDI_SUBD_CALIB;
6149         s->subdev_flags = SDF_INTERNAL;
6150         s->n_chan       = 1;
6151         s->maxdata      = 0;
6152         if (devpriv->is_m_series) {
6153                 /* internal PWM output used for AI nonlinearity calibration */
6154                 s->insn_config  = ni_m_series_pwm_config;
6155 
6156                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
6157         } else if (devpriv->is_6143) {
6158                 /* internal PWM output used for AI nonlinearity calibration */
6159                 s->insn_config  = ni_6143_pwm_config;
6160         } else {
6161                 s->subdev_flags |= SDF_WRITABLE;
6162                 s->insn_read    = ni_calib_insn_read;
6163                 s->insn_write   = ni_calib_insn_write;
6164 
6165                 /* setup the caldacs and find the real n_chan and maxdata */
6166                 caldac_setup(dev, s);
6167         }
6168 
6169         /* EEPROM subdevice */
6170         s = &dev->subdevices[NI_EEPROM_SUBDEV];
6171         s->type         = COMEDI_SUBD_MEMORY;
6172         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
6173         s->maxdata      = 0xff;
6174         if (devpriv->is_m_series) {
6175                 s->n_chan       = M_SERIES_EEPROM_SIZE;
6176                 s->insn_read    = ni_m_series_eeprom_insn_read;
6177         } else {
6178                 s->n_chan       = 512;
6179                 s->insn_read    = ni_eeprom_insn_read;
6180         }
6181 
6182         /* Digital I/O (PFI) subdevice */
6183         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
6184         s->type         = COMEDI_SUBD_DIO;
6185         s->maxdata      = 1;
6186         if (devpriv->is_m_series) {
6187                 s->n_chan       = 16;
6188                 s->insn_bits    = ni_pfi_insn_bits;
6189                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6190 
6191                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
6192                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
6193                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
6194                                   NI_M_PFI_OUT_SEL_REG(i));
6195                 }
6196         } else {
6197                 s->n_chan       = 10;
6198                 s->subdev_flags = SDF_INTERNAL;
6199         }
6200         s->insn_config  = ni_pfi_insn_config;
6201 
6202         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
6203 
6204         /* cs5529 calibration adc */
6205         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
6206         if (devpriv->is_67xx) {
6207                 s->type = COMEDI_SUBD_AI;
6208                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
6209                 /*  one channel for each analog output channel */
6210                 s->n_chan = board->n_aochan;
6211                 s->maxdata = BIT(16) - 1;
6212                 s->range_table = &range_unknown;        /* XXX */
6213                 s->insn_read = cs5529_ai_insn_read;
6214                 s->insn_config = NULL;
6215                 init_cs5529(dev);
6216         } else {
6217                 s->type = COMEDI_SUBD_UNUSED;
6218         }
6219 
6220         /* Serial */
6221         s = &dev->subdevices[NI_SERIAL_SUBDEV];
6222         s->type = COMEDI_SUBD_SERIAL;
6223         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6224         s->n_chan = 1;
6225         s->maxdata = 0xff;
6226         s->insn_config = ni_serial_insn_config;
6227         devpriv->serial_interval_ns = 0;
6228         devpriv->serial_hw_mode = 0;
6229 
6230         /* RTSI */
6231         s = &dev->subdevices[NI_RTSI_SUBDEV];
6232         s->type = COMEDI_SUBD_DIO;
6233         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6234         s->n_chan = 8;
6235         s->maxdata = 1;
6236         s->insn_bits = ni_rtsi_insn_bits;
6237         s->insn_config = ni_rtsi_insn_config;
6238         ni_rtsi_init(dev);
6239 
6240         /* allocate and initialize the gpct counter device */
6241         devpriv->counter_dev = ni_gpct_device_construct(dev,
6242                                         ni_gpct_write_register,
6243                                         ni_gpct_read_register,
6244                                         (devpriv->is_m_series)
6245                                                 ? ni_gpct_variant_m_series
6246                                                 : ni_gpct_variant_e_series,
6247                                         NUM_GPCT,
6248                                         NUM_GPCT,
6249                                         &devpriv->routing_tables);
6250         if (!devpriv->counter_dev)
6251                 return -ENOMEM;
6252 
6253         /* Counter (gpct) subdevices */
6254         for (i = 0; i < NUM_GPCT; ++i) {
6255                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
6256 
6257                 /* setup and initialize the counter */
6258                 ni_tio_init_counter(gpct);
6259 
6260                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
6261                 s->type         = COMEDI_SUBD_COUNTER;
6262                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
6263                 s->n_chan       = 3;
6264                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
6265                                                          : 0x00ffffff;
6266                 s->insn_read    = ni_tio_insn_read;
6267                 s->insn_write   = ni_tio_insn_write;
6268                 s->insn_config  = ni_tio_insn_config;
6269 #ifdef PCIDMA
6270                 if (dev->irq && devpriv->mite) {
6271                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
6272                         s->len_chanlist = 1;
6273                         s->do_cmdtest   = ni_tio_cmdtest;
6274                         s->do_cmd       = ni_gpct_cmd;
6275                         s->cancel       = ni_gpct_cancel;
6276 
6277                         s->async_dma_dir = DMA_BIDIRECTIONAL;
6278                 }
6279 #endif
6280                 s->private      = gpct;
6281         }
6282 
6283         /* Initialize GPFO_{0,1} to produce output of counters */
6284         ni_set_gout_routing(0, 0, dev); /* output of counter 0; DAQ STC, p338 */
6285         ni_set_gout_routing(0, 1, dev); /* output of counter 1; DAQ STC, p338 */
6286 
6287         /* Frequency output subdevice */
6288         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
6289         s->type         = COMEDI_SUBD_COUNTER;
6290         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
6291         s->n_chan       = 1;
6292         s->maxdata      = 0xf;
6293         s->insn_read    = ni_freq_out_insn_read;
6294         s->insn_write   = ni_freq_out_insn_write;
6295         s->insn_config  = ni_freq_out_insn_config;
6296 
6297         if (dev->irq) {
6298                 ni_stc_writew(dev,
6299                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
6300                               (NISTC_INT_CTRL_3PIN_INT & 0) |
6301                               NISTC_INT_CTRL_INTA_ENA |
6302                               NISTC_INT_CTRL_INTB_ENA |
6303                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
6304                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
6305                               NISTC_INT_CTRL_REG);
6306         }
6307 
6308         /* DMA setup */
6309         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
6310         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
6311 
6312         if (devpriv->is_6xxx) {
6313                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
6314         } else if (devpriv->is_m_series) {
6315                 int channel;
6316 
6317                 for (channel = 0; channel < board->n_aochan; ++channel) {
6318                         ni_writeb(dev, 0xf,
6319                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
6320                         ni_writeb(dev, 0x0,
6321                                   NI_M_AO_REF_ATTENUATION_REG(channel));
6322                 }
6323                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
6324         }
6325 
6326         return 0;
6327 }
6328 
6329 static void mio_common_detach(struct comedi_device *dev)
6330 {
6331         struct ni_private *devpriv = dev->private;
6332 
6333         if (devpriv)
6334                 ni_gpct_device_destroy(devpriv->counter_dev);
6335 }

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