This source file includes following definitions.
- ad7746_select_channel
- ad7746_start_calib
- ad7746_start_offset_calib
- ad7746_start_gain_calib
- ad7746_store_cap_filter_rate_setup
- ad7746_store_vt_filter_rate_setup
- ad7746_write_raw
- ad7746_read_raw
- ad7746_probe
1
2
3
4
5
6
7
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/stat.h>
16 #include <linux/sysfs.h>
17
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20
21 #include "ad7746.h"
22
23
24
25
26
27 #define AD7746_REG_STATUS 0
28 #define AD7746_REG_CAP_DATA_HIGH 1
29 #define AD7746_REG_VT_DATA_HIGH 4
30 #define AD7746_REG_CAP_SETUP 7
31 #define AD7746_REG_VT_SETUP 8
32 #define AD7746_REG_EXC_SETUP 9
33 #define AD7746_REG_CFG 10
34 #define AD7746_REG_CAPDACA 11
35 #define AD7746_REG_CAPDACB 12
36 #define AD7746_REG_CAP_OFFH 13
37 #define AD7746_REG_CAP_GAINH 15
38 #define AD7746_REG_VOLT_GAINH 17
39
40
41 #define AD7746_STATUS_EXCERR BIT(3)
42 #define AD7746_STATUS_RDY BIT(2)
43 #define AD7746_STATUS_RDYVT BIT(1)
44 #define AD7746_STATUS_RDYCAP BIT(0)
45
46
47 #define AD7746_CAPSETUP_CAPEN BIT(7)
48 #define AD7746_CAPSETUP_CIN2 BIT(6)
49 #define AD7746_CAPSETUP_CAPDIFF BIT(5)
50 #define AD7746_CAPSETUP_CACHOP BIT(0)
51
52
53 #define AD7746_VTSETUP_VTEN (1 << 7)
54 #define AD7746_VTSETUP_VTMD_INT_TEMP (0 << 5)
55 #define AD7746_VTSETUP_VTMD_EXT_TEMP (1 << 5)
56 #define AD7746_VTSETUP_VTMD_VDD_MON (2 << 5)
57 #define AD7746_VTSETUP_VTMD_EXT_VIN (3 << 5)
58 #define AD7746_VTSETUP_EXTREF BIT(4)
59 #define AD7746_VTSETUP_VTSHORT BIT(1)
60 #define AD7746_VTSETUP_VTCHOP BIT(0)
61
62
63 #define AD7746_EXCSETUP_CLKCTRL BIT(7)
64 #define AD7746_EXCSETUP_EXCON BIT(6)
65 #define AD7746_EXCSETUP_EXCB BIT(5)
66 #define AD7746_EXCSETUP_NEXCB BIT(4)
67 #define AD7746_EXCSETUP_EXCA BIT(3)
68 #define AD7746_EXCSETUP_NEXCA BIT(2)
69 #define AD7746_EXCSETUP_EXCLVL(x) (((x) & 0x3) << 0)
70
71
72 #define AD7746_CONF_VTFS_SHIFT 6
73 #define AD7746_CONF_CAPFS_SHIFT 3
74 #define AD7746_CONF_VTFS_MASK GENMASK(7, 6)
75 #define AD7746_CONF_CAPFS_MASK GENMASK(5, 3)
76 #define AD7746_CONF_MODE_IDLE (0 << 0)
77 #define AD7746_CONF_MODE_CONT_CONV (1 << 0)
78 #define AD7746_CONF_MODE_SINGLE_CONV (2 << 0)
79 #define AD7746_CONF_MODE_PWRDN (3 << 0)
80 #define AD7746_CONF_MODE_OFFS_CAL (5 << 0)
81 #define AD7746_CONF_MODE_GAIN_CAL (6 << 0)
82
83
84 #define AD7746_CAPDAC_DACEN BIT(7)
85 #define AD7746_CAPDAC_DACP(x) ((x) & 0x7F)
86
87
88
89
90
91 struct ad7746_chip_info {
92 struct i2c_client *client;
93 struct mutex lock;
94
95
96
97
98 u8 config;
99 u8 cap_setup;
100 u8 vt_setup;
101 u8 capdac[2][2];
102 s8 capdac_set;
103
104 union {
105 __be32 d32;
106 u8 d8[4];
107 } data ____cacheline_aligned;
108 };
109
110 enum ad7746_chan {
111 VIN,
112 VIN_VDD,
113 TEMP_INT,
114 TEMP_EXT,
115 CIN1,
116 CIN1_DIFF,
117 CIN2,
118 CIN2_DIFF,
119 };
120
121 static const struct iio_chan_spec ad7746_channels[] = {
122 [VIN] = {
123 .type = IIO_VOLTAGE,
124 .indexed = 1,
125 .channel = 0,
126 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
127 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
128 BIT(IIO_CHAN_INFO_SAMP_FREQ),
129 .address = AD7746_REG_VT_DATA_HIGH << 8 |
130 AD7746_VTSETUP_VTMD_EXT_VIN,
131 },
132 [VIN_VDD] = {
133 .type = IIO_VOLTAGE,
134 .indexed = 1,
135 .channel = 1,
136 .extend_name = "supply",
137 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
138 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
139 BIT(IIO_CHAN_INFO_SAMP_FREQ),
140 .address = AD7746_REG_VT_DATA_HIGH << 8 |
141 AD7746_VTSETUP_VTMD_VDD_MON,
142 },
143 [TEMP_INT] = {
144 .type = IIO_TEMP,
145 .indexed = 1,
146 .channel = 0,
147 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
148 .address = AD7746_REG_VT_DATA_HIGH << 8 |
149 AD7746_VTSETUP_VTMD_INT_TEMP,
150 },
151 [TEMP_EXT] = {
152 .type = IIO_TEMP,
153 .indexed = 1,
154 .channel = 1,
155 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
156 .address = AD7746_REG_VT_DATA_HIGH << 8 |
157 AD7746_VTSETUP_VTMD_EXT_TEMP,
158 },
159 [CIN1] = {
160 .type = IIO_CAPACITANCE,
161 .indexed = 1,
162 .channel = 0,
163 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
164 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
165 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
166 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
167 .address = AD7746_REG_CAP_DATA_HIGH << 8,
168 },
169 [CIN1_DIFF] = {
170 .type = IIO_CAPACITANCE,
171 .differential = 1,
172 .indexed = 1,
173 .channel = 0,
174 .channel2 = 2,
175 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
176 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
177 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
178 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
179 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
180 AD7746_CAPSETUP_CAPDIFF
181 },
182 [CIN2] = {
183 .type = IIO_CAPACITANCE,
184 .indexed = 1,
185 .channel = 1,
186 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
187 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
188 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
189 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
190 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
191 AD7746_CAPSETUP_CIN2,
192 },
193 [CIN2_DIFF] = {
194 .type = IIO_CAPACITANCE,
195 .differential = 1,
196 .indexed = 1,
197 .channel = 1,
198 .channel2 = 3,
199 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
200 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
201 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
202 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
203 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
204 AD7746_CAPSETUP_CAPDIFF | AD7746_CAPSETUP_CIN2,
205 }
206 };
207
208
209 static const unsigned char ad7746_vt_filter_rate_table[][2] = {
210 {50, 20 + 1}, {31, 32 + 1}, {16, 62 + 1}, {8, 122 + 1},
211 };
212
213 static const unsigned char ad7746_cap_filter_rate_table[][2] = {
214 {91, 11 + 1}, {84, 12 + 1}, {50, 20 + 1}, {26, 38 + 1},
215 {16, 62 + 1}, {13, 77 + 1}, {11, 92 + 1}, {9, 110 + 1},
216 };
217
218 static int ad7746_select_channel(struct iio_dev *indio_dev,
219 struct iio_chan_spec const *chan)
220 {
221 struct ad7746_chip_info *chip = iio_priv(indio_dev);
222 u8 vt_setup, cap_setup;
223 int ret, delay, idx;
224
225 switch (chan->type) {
226 case IIO_CAPACITANCE:
227 cap_setup = (chan->address & 0xFF) | AD7746_CAPSETUP_CAPEN;
228 vt_setup = chip->vt_setup & ~AD7746_VTSETUP_VTEN;
229 idx = (chip->config & AD7746_CONF_CAPFS_MASK) >>
230 AD7746_CONF_CAPFS_SHIFT;
231 delay = ad7746_cap_filter_rate_table[idx][1];
232
233 if (chip->capdac_set != chan->channel) {
234 ret = i2c_smbus_write_byte_data(chip->client,
235 AD7746_REG_CAPDACA,
236 chip->capdac[chan->channel][0]);
237 if (ret < 0)
238 return ret;
239 ret = i2c_smbus_write_byte_data(chip->client,
240 AD7746_REG_CAPDACB,
241 chip->capdac[chan->channel][1]);
242 if (ret < 0)
243 return ret;
244
245 chip->capdac_set = chan->channel;
246 }
247 break;
248 case IIO_VOLTAGE:
249 case IIO_TEMP:
250 vt_setup = (chan->address & 0xFF) | AD7746_VTSETUP_VTEN;
251 cap_setup = chip->cap_setup & ~AD7746_CAPSETUP_CAPEN;
252 idx = (chip->config & AD7746_CONF_VTFS_MASK) >>
253 AD7746_CONF_VTFS_SHIFT;
254 delay = ad7746_cap_filter_rate_table[idx][1];
255 break;
256 default:
257 return -EINVAL;
258 }
259
260 if (chip->cap_setup != cap_setup) {
261 ret = i2c_smbus_write_byte_data(chip->client,
262 AD7746_REG_CAP_SETUP,
263 cap_setup);
264 if (ret < 0)
265 return ret;
266
267 chip->cap_setup = cap_setup;
268 }
269
270 if (chip->vt_setup != vt_setup) {
271 ret = i2c_smbus_write_byte_data(chip->client,
272 AD7746_REG_VT_SETUP,
273 vt_setup);
274 if (ret < 0)
275 return ret;
276
277 chip->vt_setup = vt_setup;
278 }
279
280 return delay;
281 }
282
283 static inline ssize_t ad7746_start_calib(struct device *dev,
284 struct device_attribute *attr,
285 const char *buf,
286 size_t len,
287 u8 regval)
288 {
289 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
290 struct ad7746_chip_info *chip = iio_priv(indio_dev);
291 int ret, timeout = 10;
292 bool doit;
293
294 ret = strtobool(buf, &doit);
295 if (ret < 0)
296 return ret;
297
298 if (!doit)
299 return 0;
300
301 mutex_lock(&chip->lock);
302 regval |= chip->config;
303 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval);
304 if (ret < 0)
305 goto unlock;
306
307 do {
308 msleep(20);
309 ret = i2c_smbus_read_byte_data(chip->client, AD7746_REG_CFG);
310 if (ret < 0)
311 goto unlock;
312
313 } while ((ret == regval) && timeout--);
314
315 mutex_unlock(&chip->lock);
316
317 return len;
318
319 unlock:
320 mutex_unlock(&chip->lock);
321 return ret;
322 }
323
324 static ssize_t ad7746_start_offset_calib(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf,
327 size_t len)
328 {
329 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
330 int ret = ad7746_select_channel(indio_dev,
331 &ad7746_channels[to_iio_dev_attr(attr)->address]);
332 if (ret < 0)
333 return ret;
334
335 return ad7746_start_calib(dev, attr, buf, len,
336 AD7746_CONF_MODE_OFFS_CAL);
337 }
338
339 static ssize_t ad7746_start_gain_calib(struct device *dev,
340 struct device_attribute *attr,
341 const char *buf,
342 size_t len)
343 {
344 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
345 int ret = ad7746_select_channel(indio_dev,
346 &ad7746_channels[to_iio_dev_attr(attr)->address]);
347 if (ret < 0)
348 return ret;
349
350 return ad7746_start_calib(dev, attr, buf, len,
351 AD7746_CONF_MODE_GAIN_CAL);
352 }
353
354 static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration,
355 0200, NULL, ad7746_start_offset_calib, CIN1);
356 static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration,
357 0200, NULL, ad7746_start_offset_calib, CIN2);
358 static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration,
359 0200, NULL, ad7746_start_gain_calib, CIN1);
360 static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration,
361 0200, NULL, ad7746_start_gain_calib, CIN2);
362 static IIO_DEVICE_ATTR(in_voltage0_calibscale_calibration,
363 0200, NULL, ad7746_start_gain_calib, VIN);
364
365 static int ad7746_store_cap_filter_rate_setup(struct ad7746_chip_info *chip,
366 int val)
367 {
368 int i;
369
370 for (i = 0; i < ARRAY_SIZE(ad7746_cap_filter_rate_table); i++)
371 if (val >= ad7746_cap_filter_rate_table[i][0])
372 break;
373
374 if (i >= ARRAY_SIZE(ad7746_cap_filter_rate_table))
375 i = ARRAY_SIZE(ad7746_cap_filter_rate_table) - 1;
376
377 chip->config &= ~AD7746_CONF_CAPFS_MASK;
378 chip->config |= i << AD7746_CONF_CAPFS_SHIFT;
379
380 return 0;
381 }
382
383 static int ad7746_store_vt_filter_rate_setup(struct ad7746_chip_info *chip,
384 int val)
385 {
386 int i;
387
388 for (i = 0; i < ARRAY_SIZE(ad7746_vt_filter_rate_table); i++)
389 if (val >= ad7746_vt_filter_rate_table[i][0])
390 break;
391
392 if (i >= ARRAY_SIZE(ad7746_vt_filter_rate_table))
393 i = ARRAY_SIZE(ad7746_vt_filter_rate_table) - 1;
394
395 chip->config &= ~AD7746_CONF_VTFS_MASK;
396 chip->config |= i << AD7746_CONF_VTFS_SHIFT;
397
398 return 0;
399 }
400
401 static IIO_CONST_ATTR(in_voltage_sampling_frequency_available, "50 31 16 8");
402 static IIO_CONST_ATTR(in_capacitance_sampling_frequency_available,
403 "91 84 50 26 16 13 11 9");
404
405 static struct attribute *ad7746_attributes[] = {
406 &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr,
407 &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr,
408 &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr,
409 &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr,
410 &iio_dev_attr_in_voltage0_calibscale_calibration.dev_attr.attr,
411 &iio_const_attr_in_voltage_sampling_frequency_available.dev_attr.attr,
412 &iio_const_attr_in_capacitance_sampling_frequency_available.dev_attr.attr,
413 NULL,
414 };
415
416 static const struct attribute_group ad7746_attribute_group = {
417 .attrs = ad7746_attributes,
418 };
419
420 static int ad7746_write_raw(struct iio_dev *indio_dev,
421 struct iio_chan_spec const *chan,
422 int val,
423 int val2,
424 long mask)
425 {
426 struct ad7746_chip_info *chip = iio_priv(indio_dev);
427 int ret, reg;
428
429 mutex_lock(&chip->lock);
430
431 switch (mask) {
432 case IIO_CHAN_INFO_CALIBSCALE:
433 if (val != 1) {
434 ret = -EINVAL;
435 goto out;
436 }
437
438 val = (val2 * 1024) / 15625;
439
440 switch (chan->type) {
441 case IIO_CAPACITANCE:
442 reg = AD7746_REG_CAP_GAINH;
443 break;
444 case IIO_VOLTAGE:
445 reg = AD7746_REG_VOLT_GAINH;
446 break;
447 default:
448 ret = -EINVAL;
449 goto out;
450 }
451
452 ret = i2c_smbus_write_word_swapped(chip->client, reg, val);
453 if (ret < 0)
454 goto out;
455
456 ret = 0;
457 break;
458 case IIO_CHAN_INFO_CALIBBIAS:
459 if (val < 0 || val > 0xFFFF) {
460 ret = -EINVAL;
461 goto out;
462 }
463 ret = i2c_smbus_write_word_swapped(chip->client,
464 AD7746_REG_CAP_OFFH, val);
465 if (ret < 0)
466 goto out;
467
468 ret = 0;
469 break;
470 case IIO_CHAN_INFO_OFFSET:
471 if (val < 0 || val > 43008000) {
472 ret = -EINVAL;
473 goto out;
474 }
475
476
477
478
479
480
481
482 val /= 338646;
483
484 chip->capdac[chan->channel][chan->differential] = val > 0 ?
485 AD7746_CAPDAC_DACP(val) | AD7746_CAPDAC_DACEN : 0;
486
487 ret = i2c_smbus_write_byte_data(chip->client,
488 AD7746_REG_CAPDACA,
489 chip->capdac[chan->channel][0]);
490 if (ret < 0)
491 goto out;
492 ret = i2c_smbus_write_byte_data(chip->client,
493 AD7746_REG_CAPDACB,
494 chip->capdac[chan->channel][1]);
495 if (ret < 0)
496 goto out;
497
498 chip->capdac_set = chan->channel;
499
500 ret = 0;
501 break;
502 case IIO_CHAN_INFO_SAMP_FREQ:
503 if (val2) {
504 ret = -EINVAL;
505 goto out;
506 }
507
508 switch (chan->type) {
509 case IIO_CAPACITANCE:
510 ret = ad7746_store_cap_filter_rate_setup(chip, val);
511 break;
512 case IIO_VOLTAGE:
513 ret = ad7746_store_vt_filter_rate_setup(chip, val);
514 break;
515 default:
516 ret = -EINVAL;
517 }
518 break;
519 default:
520 ret = -EINVAL;
521 }
522
523 out:
524 mutex_unlock(&chip->lock);
525 return ret;
526 }
527
528 static int ad7746_read_raw(struct iio_dev *indio_dev,
529 struct iio_chan_spec const *chan,
530 int *val, int *val2,
531 long mask)
532 {
533 struct ad7746_chip_info *chip = iio_priv(indio_dev);
534 int ret, delay, idx;
535 u8 regval, reg;
536
537 mutex_lock(&chip->lock);
538
539 switch (mask) {
540 case IIO_CHAN_INFO_RAW:
541 case IIO_CHAN_INFO_PROCESSED:
542 ret = ad7746_select_channel(indio_dev, chan);
543 if (ret < 0)
544 goto out;
545 delay = ret;
546
547 regval = chip->config | AD7746_CONF_MODE_SINGLE_CONV;
548 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG,
549 regval);
550 if (ret < 0)
551 goto out;
552
553 msleep(delay);
554
555
556 ret = i2c_smbus_read_i2c_block_data(chip->client,
557 chan->address >> 8, 3,
558 &chip->data.d8[1]);
559
560 if (ret < 0)
561 goto out;
562
563 *val = (be32_to_cpu(chip->data.d32) & 0xFFFFFF) - 0x800000;
564
565 switch (chan->type) {
566 case IIO_TEMP:
567
568
569
570
571 *val = (*val * 125) / 256;
572 break;
573 case IIO_VOLTAGE:
574 if (chan->channel == 1)
575 *val = *val * 6;
576 break;
577 default:
578 break;
579 }
580
581 ret = IIO_VAL_INT;
582 break;
583 case IIO_CHAN_INFO_CALIBSCALE:
584 switch (chan->type) {
585 case IIO_CAPACITANCE:
586 reg = AD7746_REG_CAP_GAINH;
587 break;
588 case IIO_VOLTAGE:
589 reg = AD7746_REG_VOLT_GAINH;
590 break;
591 default:
592 ret = -EINVAL;
593 goto out;
594 }
595
596 ret = i2c_smbus_read_word_swapped(chip->client, reg);
597 if (ret < 0)
598 goto out;
599
600 *val = 1;
601 *val2 = (15625 * ret) / 1024;
602
603 ret = IIO_VAL_INT_PLUS_MICRO;
604 break;
605 case IIO_CHAN_INFO_CALIBBIAS:
606 ret = i2c_smbus_read_word_swapped(chip->client,
607 AD7746_REG_CAP_OFFH);
608 if (ret < 0)
609 goto out;
610 *val = ret;
611
612 ret = IIO_VAL_INT;
613 break;
614 case IIO_CHAN_INFO_OFFSET:
615 *val = AD7746_CAPDAC_DACP(chip->capdac[chan->channel]
616 [chan->differential]) * 338646;
617
618 ret = IIO_VAL_INT;
619 break;
620 case IIO_CHAN_INFO_SCALE:
621 switch (chan->type) {
622 case IIO_CAPACITANCE:
623
624 *val = 0;
625 *val2 = 488;
626 ret = IIO_VAL_INT_PLUS_NANO;
627 break;
628 case IIO_VOLTAGE:
629
630 *val = 1170;
631 *val2 = 23;
632 ret = IIO_VAL_FRACTIONAL_LOG2;
633 break;
634 default:
635 ret = -EINVAL;
636 break;
637 }
638
639 break;
640 case IIO_CHAN_INFO_SAMP_FREQ:
641 switch (chan->type) {
642 case IIO_CAPACITANCE:
643 idx = (chip->config & AD7746_CONF_CAPFS_MASK) >>
644 AD7746_CONF_CAPFS_SHIFT;
645 *val = ad7746_cap_filter_rate_table[idx][0];
646 ret = IIO_VAL_INT;
647 break;
648 case IIO_VOLTAGE:
649 idx = (chip->config & AD7746_CONF_VTFS_MASK) >>
650 AD7746_CONF_VTFS_SHIFT;
651 *val = ad7746_vt_filter_rate_table[idx][0];
652 ret = IIO_VAL_INT;
653 break;
654 default:
655 ret = -EINVAL;
656 }
657 break;
658 default:
659 ret = -EINVAL;
660 }
661 out:
662 mutex_unlock(&chip->lock);
663 return ret;
664 }
665
666 static const struct iio_info ad7746_info = {
667 .attrs = &ad7746_attribute_group,
668 .read_raw = ad7746_read_raw,
669 .write_raw = ad7746_write_raw,
670 };
671
672
673
674
675
676 static int ad7746_probe(struct i2c_client *client,
677 const struct i2c_device_id *id)
678 {
679 struct ad7746_platform_data *pdata = client->dev.platform_data;
680 struct ad7746_chip_info *chip;
681 struct iio_dev *indio_dev;
682 unsigned char regval = 0;
683 int ret = 0;
684
685 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
686 if (!indio_dev)
687 return -ENOMEM;
688 chip = iio_priv(indio_dev);
689 mutex_init(&chip->lock);
690
691 i2c_set_clientdata(client, indio_dev);
692
693 chip->client = client;
694 chip->capdac_set = -1;
695
696
697 indio_dev->name = id->name;
698 indio_dev->dev.parent = &client->dev;
699 indio_dev->info = &ad7746_info;
700 indio_dev->channels = ad7746_channels;
701 if (id->driver_data == 7746)
702 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels);
703 else
704 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels) - 2;
705 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels);
706 indio_dev->modes = INDIO_DIRECT_MODE;
707
708 if (pdata) {
709 if (pdata->exca_en) {
710 if (pdata->exca_inv_en)
711 regval |= AD7746_EXCSETUP_NEXCA;
712 else
713 regval |= AD7746_EXCSETUP_EXCA;
714 }
715
716 if (pdata->excb_en) {
717 if (pdata->excb_inv_en)
718 regval |= AD7746_EXCSETUP_NEXCB;
719 else
720 regval |= AD7746_EXCSETUP_EXCB;
721 }
722
723 regval |= AD7746_EXCSETUP_EXCLVL(pdata->exclvl);
724 } else {
725 dev_warn(&client->dev, "No platform data? using default\n");
726 regval = AD7746_EXCSETUP_EXCA | AD7746_EXCSETUP_EXCB |
727 AD7746_EXCSETUP_EXCLVL(3);
728 }
729
730 ret = i2c_smbus_write_byte_data(chip->client,
731 AD7746_REG_EXC_SETUP, regval);
732 if (ret < 0)
733 return ret;
734
735 ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev);
736 if (ret)
737 return ret;
738
739 return 0;
740 }
741
742 static const struct i2c_device_id ad7746_id[] = {
743 { "ad7745", 7745 },
744 { "ad7746", 7746 },
745 { "ad7747", 7747 },
746 {}
747 };
748
749 MODULE_DEVICE_TABLE(i2c, ad7746_id);
750
751 static const struct of_device_id ad7746_of_match[] = {
752 { .compatible = "adi,ad7745" },
753 { .compatible = "adi,ad7746" },
754 { .compatible = "adi,ad7747" },
755 { },
756 };
757
758 MODULE_DEVICE_TABLE(of, ad7746_of_match);
759
760 static struct i2c_driver ad7746_driver = {
761 .driver = {
762 .name = KBUILD_MODNAME,
763 .of_match_table = ad7746_of_match,
764 },
765 .probe = ad7746_probe,
766 .id_table = ad7746_id,
767 };
768 module_i2c_driver(ad7746_driver);
769
770 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
771 MODULE_DESCRIPTION("Analog Devices AD7746/5/7 capacitive sensor driver");
772 MODULE_LICENSE("GPL v2");