root/drivers/staging/iio/frequency/ad9834.c

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DEFINITIONS

This source file includes following definitions.
  1. ad9834_calc_freqreg
  2. ad9834_write_frequency
  3. ad9834_write_phase
  4. ad9834_write
  5. ad9834_store_wavetype
  6. ad9834_show_out0_wavetype_available
  7. ad9834_show_out1_wavetype_available
  8. ad9834_probe
  9. ad9834_remove

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * AD9833/AD9834/AD9837/AD9838 SPI DDS driver
   4  *
   5  * Copyright 2010-2011 Analog Devices Inc.
   6  */
   7 
   8 #include <linux/clk.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/workqueue.h>
  11 #include <linux/device.h>
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/sysfs.h>
  15 #include <linux/list.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/err.h>
  19 #include <linux/module.h>
  20 #include <asm/div64.h>
  21 
  22 #include <linux/iio/iio.h>
  23 #include <linux/iio/sysfs.h>
  24 #include "dds.h"
  25 
  26 #include "ad9834.h"
  27 
  28 /* Registers */
  29 
  30 #define AD9834_REG_CMD          0
  31 #define AD9834_REG_FREQ0        BIT(14)
  32 #define AD9834_REG_FREQ1        BIT(15)
  33 #define AD9834_REG_PHASE0       (BIT(15) | BIT(14))
  34 #define AD9834_REG_PHASE1       (BIT(15) | BIT(14) | BIT(13))
  35 
  36 /* Command Control Bits */
  37 
  38 #define AD9834_B28              BIT(13)
  39 #define AD9834_HLB              BIT(12)
  40 #define AD9834_FSEL             BIT(11)
  41 #define AD9834_PSEL             BIT(10)
  42 #define AD9834_PIN_SW           BIT(9)
  43 #define AD9834_RESET            BIT(8)
  44 #define AD9834_SLEEP1           BIT(7)
  45 #define AD9834_SLEEP12          BIT(6)
  46 #define AD9834_OPBITEN          BIT(5)
  47 #define AD9834_SIGN_PIB         BIT(4)
  48 #define AD9834_DIV2             BIT(3)
  49 #define AD9834_MODE             BIT(1)
  50 
  51 #define AD9834_FREQ_BITS        28
  52 #define AD9834_PHASE_BITS       12
  53 
  54 #define RES_MASK(bits)  (BIT(bits) - 1)
  55 
  56 /**
  57  * struct ad9834_state - driver instance specific data
  58  * @spi:                spi_device
  59  * @reg:                supply regulator
  60  * @mclk:               external master clock
  61  * @control:            cached control word
  62  * @xfer:               default spi transfer
  63  * @msg:                default spi message
  64  * @freq_xfer:          tuning word spi transfer
  65  * @freq_msg:           tuning word spi message
  66  * @lock:               protect sensor state
  67  * @data:               spi transmit buffer
  68  * @freq_data:          tuning word spi transmit buffer
  69  */
  70 
  71 struct ad9834_state {
  72         struct spi_device               *spi;
  73         struct regulator                *reg;
  74         struct clk                      *mclk;
  75         unsigned short                  control;
  76         unsigned short                  devid;
  77         struct spi_transfer             xfer;
  78         struct spi_message              msg;
  79         struct spi_transfer             freq_xfer[2];
  80         struct spi_message              freq_msg;
  81         struct mutex                    lock;   /* protect sensor state */
  82 
  83         /*
  84          * DMA (thus cache coherency maintenance) requires the
  85          * transfer buffers to live in their own cache lines.
  86          */
  87         __be16                          data ____cacheline_aligned;
  88         __be16                          freq_data[2];
  89 };
  90 
  91 /**
  92  * ad9834_supported_device_ids:
  93  */
  94 
  95 enum ad9834_supported_device_ids {
  96         ID_AD9833,
  97         ID_AD9834,
  98         ID_AD9837,
  99         ID_AD9838,
 100 };
 101 
 102 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
 103 {
 104         unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
 105 
 106         do_div(freqreg, mclk);
 107         return freqreg;
 108 }
 109 
 110 static int ad9834_write_frequency(struct ad9834_state *st,
 111                                   unsigned long addr, unsigned long fout)
 112 {
 113         unsigned long clk_freq;
 114         unsigned long regval;
 115 
 116         clk_freq = clk_get_rate(st->mclk);
 117 
 118         if (fout > (clk_freq / 2))
 119                 return -EINVAL;
 120 
 121         regval = ad9834_calc_freqreg(clk_freq, fout);
 122 
 123         st->freq_data[0] = cpu_to_be16(addr | (regval &
 124                                        RES_MASK(AD9834_FREQ_BITS / 2)));
 125         st->freq_data[1] = cpu_to_be16(addr | ((regval >>
 126                                        (AD9834_FREQ_BITS / 2)) &
 127                                        RES_MASK(AD9834_FREQ_BITS / 2)));
 128 
 129         return spi_sync(st->spi, &st->freq_msg);
 130 }
 131 
 132 static int ad9834_write_phase(struct ad9834_state *st,
 133                               unsigned long addr, unsigned long phase)
 134 {
 135         if (phase > BIT(AD9834_PHASE_BITS))
 136                 return -EINVAL;
 137         st->data = cpu_to_be16(addr | phase);
 138 
 139         return spi_sync(st->spi, &st->msg);
 140 }
 141 
 142 static ssize_t ad9834_write(struct device *dev,
 143                             struct device_attribute *attr,
 144                             const char *buf,
 145                             size_t len)
 146 {
 147         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 148         struct ad9834_state *st = iio_priv(indio_dev);
 149         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 150         int ret;
 151         unsigned long val;
 152 
 153         ret = kstrtoul(buf, 10, &val);
 154         if (ret)
 155                 return ret;
 156 
 157         mutex_lock(&st->lock);
 158         switch ((u32)this_attr->address) {
 159         case AD9834_REG_FREQ0:
 160         case AD9834_REG_FREQ1:
 161                 ret = ad9834_write_frequency(st, this_attr->address, val);
 162                 break;
 163         case AD9834_REG_PHASE0:
 164         case AD9834_REG_PHASE1:
 165                 ret = ad9834_write_phase(st, this_attr->address, val);
 166                 break;
 167         case AD9834_OPBITEN:
 168                 if (st->control & AD9834_MODE) {
 169                         ret = -EINVAL;  /* AD9843 reserved mode */
 170                         break;
 171                 }
 172 
 173                 if (val)
 174                         st->control |= AD9834_OPBITEN;
 175                 else
 176                         st->control &= ~AD9834_OPBITEN;
 177 
 178                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
 179                 ret = spi_sync(st->spi, &st->msg);
 180                 break;
 181         case AD9834_PIN_SW:
 182                 if (val)
 183                         st->control |= AD9834_PIN_SW;
 184                 else
 185                         st->control &= ~AD9834_PIN_SW;
 186                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
 187                 ret = spi_sync(st->spi, &st->msg);
 188                 break;
 189         case AD9834_FSEL:
 190         case AD9834_PSEL:
 191                 if (!val) {
 192                         st->control &= ~(this_attr->address | AD9834_PIN_SW);
 193                 } else if (val == 1) {
 194                         st->control |= this_attr->address;
 195                         st->control &= ~AD9834_PIN_SW;
 196                 } else {
 197                         ret = -EINVAL;
 198                         break;
 199                 }
 200                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
 201                 ret = spi_sync(st->spi, &st->msg);
 202                 break;
 203         case AD9834_RESET:
 204                 if (val)
 205                         st->control &= ~AD9834_RESET;
 206                 else
 207                         st->control |= AD9834_RESET;
 208 
 209                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
 210                 ret = spi_sync(st->spi, &st->msg);
 211                 break;
 212         default:
 213                 ret = -ENODEV;
 214         }
 215         mutex_unlock(&st->lock);
 216 
 217         return ret ? ret : len;
 218 }
 219 
 220 static ssize_t ad9834_store_wavetype(struct device *dev,
 221                                      struct device_attribute *attr,
 222                                      const char *buf,
 223                                      size_t len)
 224 {
 225         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 226         struct ad9834_state *st = iio_priv(indio_dev);
 227         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 228         int ret = 0;
 229         bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
 230 
 231         mutex_lock(&st->lock);
 232 
 233         switch ((u32)this_attr->address) {
 234         case 0:
 235                 if (sysfs_streq(buf, "sine")) {
 236                         st->control &= ~AD9834_MODE;
 237                         if (is_ad9833_7)
 238                                 st->control &= ~AD9834_OPBITEN;
 239                 } else if (sysfs_streq(buf, "triangle")) {
 240                         if (is_ad9833_7) {
 241                                 st->control &= ~AD9834_OPBITEN;
 242                                 st->control |= AD9834_MODE;
 243                         } else if (st->control & AD9834_OPBITEN) {
 244                                 ret = -EINVAL;  /* AD9843 reserved mode */
 245                         } else {
 246                                 st->control |= AD9834_MODE;
 247                         }
 248                 } else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
 249                         st->control &= ~AD9834_MODE;
 250                         st->control |= AD9834_OPBITEN;
 251                 } else {
 252                         ret = -EINVAL;
 253                 }
 254 
 255                 break;
 256         case 1:
 257                 if (sysfs_streq(buf, "square") &&
 258                     !(st->control & AD9834_MODE)) {
 259                         st->control &= ~AD9834_MODE;
 260                         st->control |= AD9834_OPBITEN;
 261                 } else {
 262                         ret = -EINVAL;
 263                 }
 264                 break;
 265         default:
 266                 ret = -EINVAL;
 267                 break;
 268         }
 269 
 270         if (!ret) {
 271                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
 272                 ret = spi_sync(st->spi, &st->msg);
 273         }
 274         mutex_unlock(&st->lock);
 275 
 276         return ret ? ret : len;
 277 }
 278 
 279 static
 280 ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
 281                                             struct device_attribute *attr,
 282                                             char *buf)
 283 {
 284         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 285         struct ad9834_state *st = iio_priv(indio_dev);
 286         char *str;
 287 
 288         if (st->devid == ID_AD9833 || st->devid == ID_AD9837)
 289                 str = "sine triangle square";
 290         else if (st->control & AD9834_OPBITEN)
 291                 str = "sine";
 292         else
 293                 str = "sine triangle";
 294 
 295         return sprintf(buf, "%s\n", str);
 296 }
 297 
 298 static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444,
 299                        ad9834_show_out0_wavetype_available, NULL, 0);
 300 
 301 static
 302 ssize_t ad9834_show_out1_wavetype_available(struct device *dev,
 303                                             struct device_attribute *attr,
 304                                             char *buf)
 305 {
 306         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 307         struct ad9834_state *st = iio_priv(indio_dev);
 308         char *str;
 309 
 310         if (st->control & AD9834_MODE)
 311                 str = "";
 312         else
 313                 str = "square";
 314 
 315         return sprintf(buf, "%s\n", str);
 316 }
 317 
 318 static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,
 319                        ad9834_show_out1_wavetype_available, NULL, 0);
 320 
 321 /**
 322  * see dds.h for further information
 323  */
 324 
 325 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0);
 326 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1);
 327 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL);
 328 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
 329 
 330 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0);
 331 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1);
 332 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL);
 333 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
 334 
 335 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
 336         ad9834_write, AD9834_PIN_SW);
 337 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET);
 338 static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL,
 339         ad9834_write, AD9834_OPBITEN);
 340 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0);
 341 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1);
 342 
 343 static struct attribute *ad9834_attributes[] = {
 344         &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
 345         &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
 346         &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
 347         &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
 348         &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
 349         &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
 350         &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
 351         &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
 352         &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
 353         &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
 354         &iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr,
 355         &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
 356         &iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr,
 357         &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
 358         &iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr,
 359         NULL,
 360 };
 361 
 362 static struct attribute *ad9833_attributes[] = {
 363         &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
 364         &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
 365         &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
 366         &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
 367         &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
 368         &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
 369         &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
 370         &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
 371         &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
 372         &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
 373         &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
 374         NULL,
 375 };
 376 
 377 static const struct attribute_group ad9834_attribute_group = {
 378         .attrs = ad9834_attributes,
 379 };
 380 
 381 static const struct attribute_group ad9833_attribute_group = {
 382         .attrs = ad9833_attributes,
 383 };
 384 
 385 static const struct iio_info ad9834_info = {
 386         .attrs = &ad9834_attribute_group,
 387 };
 388 
 389 static const struct iio_info ad9833_info = {
 390         .attrs = &ad9833_attribute_group,
 391 };
 392 
 393 static int ad9834_probe(struct spi_device *spi)
 394 {
 395         struct ad9834_state *st;
 396         struct iio_dev *indio_dev;
 397         struct regulator *reg;
 398         int ret;
 399 
 400 
 401         reg = devm_regulator_get(&spi->dev, "avdd");
 402         if (IS_ERR(reg))
 403                 return PTR_ERR(reg);
 404 
 405         ret = regulator_enable(reg);
 406         if (ret) {
 407                 dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
 408                 return ret;
 409         }
 410 
 411         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 412         if (!indio_dev) {
 413                 ret = -ENOMEM;
 414                 goto error_disable_reg;
 415         }
 416         spi_set_drvdata(spi, indio_dev);
 417         st = iio_priv(indio_dev);
 418         mutex_init(&st->lock);
 419         st->mclk = devm_clk_get(&spi->dev, NULL);
 420         if (IS_ERR(st->mclk)) {
 421                 ret = PTR_ERR(st->mclk);
 422                 goto error_disable_reg;
 423         }
 424 
 425         ret = clk_prepare_enable(st->mclk);
 426         if (ret) {
 427                 dev_err(&spi->dev, "Failed to enable master clock\n");
 428                 goto error_disable_reg;
 429         }
 430 
 431         st->spi = spi;
 432         st->devid = spi_get_device_id(spi)->driver_data;
 433         st->reg = reg;
 434         indio_dev->dev.parent = &spi->dev;
 435         indio_dev->name = spi_get_device_id(spi)->name;
 436         switch (st->devid) {
 437         case ID_AD9833:
 438         case ID_AD9837:
 439                 indio_dev->info = &ad9833_info;
 440                 break;
 441         default:
 442                 indio_dev->info = &ad9834_info;
 443                 break;
 444         }
 445         indio_dev->modes = INDIO_DIRECT_MODE;
 446 
 447         /* Setup default messages */
 448 
 449         st->xfer.tx_buf = &st->data;
 450         st->xfer.len = 2;
 451 
 452         spi_message_init(&st->msg);
 453         spi_message_add_tail(&st->xfer, &st->msg);
 454 
 455         st->freq_xfer[0].tx_buf = &st->freq_data[0];
 456         st->freq_xfer[0].len = 2;
 457         st->freq_xfer[0].cs_change = 1;
 458         st->freq_xfer[1].tx_buf = &st->freq_data[1];
 459         st->freq_xfer[1].len = 2;
 460 
 461         spi_message_init(&st->freq_msg);
 462         spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
 463         spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
 464 
 465         st->control = AD9834_B28 | AD9834_RESET;
 466         st->control |= AD9834_DIV2;
 467 
 468         if (st->devid == ID_AD9834)
 469                 st->control |= AD9834_SIGN_PIB;
 470 
 471         st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
 472         ret = spi_sync(st->spi, &st->msg);
 473         if (ret) {
 474                 dev_err(&spi->dev, "device init failed\n");
 475                 goto error_clock_unprepare;
 476         }
 477 
 478         ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000);
 479         if (ret)
 480                 goto error_clock_unprepare;
 481 
 482         ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000);
 483         if (ret)
 484                 goto error_clock_unprepare;
 485 
 486         ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512);
 487         if (ret)
 488                 goto error_clock_unprepare;
 489 
 490         ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024);
 491         if (ret)
 492                 goto error_clock_unprepare;
 493 
 494         ret = iio_device_register(indio_dev);
 495         if (ret)
 496                 goto error_clock_unprepare;
 497 
 498         return 0;
 499 error_clock_unprepare:
 500         clk_disable_unprepare(st->mclk);
 501 error_disable_reg:
 502         regulator_disable(reg);
 503 
 504         return ret;
 505 }
 506 
 507 static int ad9834_remove(struct spi_device *spi)
 508 {
 509         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 510         struct ad9834_state *st = iio_priv(indio_dev);
 511 
 512         iio_device_unregister(indio_dev);
 513         clk_disable_unprepare(st->mclk);
 514         regulator_disable(st->reg);
 515 
 516         return 0;
 517 }
 518 
 519 static const struct spi_device_id ad9834_id[] = {
 520         {"ad9833", ID_AD9833},
 521         {"ad9834", ID_AD9834},
 522         {"ad9837", ID_AD9837},
 523         {"ad9838", ID_AD9838},
 524         {}
 525 };
 526 MODULE_DEVICE_TABLE(spi, ad9834_id);
 527 
 528 static const struct of_device_id ad9834_of_match[] = {
 529         {.compatible = "adi,ad9833"},
 530         {.compatible = "adi,ad9834"},
 531         {.compatible = "adi,ad9837"},
 532         {.compatible = "adi,ad9838"},
 533         {}
 534 };
 535 
 536 MODULE_DEVICE_TABLE(of, ad9834_of_match);
 537 
 538 static struct spi_driver ad9834_driver = {
 539         .driver = {
 540                 .name   = "ad9834",
 541                 .of_match_table = ad9834_of_match
 542         },
 543         .probe          = ad9834_probe,
 544         .remove         = ad9834_remove,
 545         .id_table       = ad9834_id,
 546 };
 547 module_spi_driver(ad9834_driver);
 548 
 549 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
 550 MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
 551 MODULE_LICENSE("GPL v2");

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