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7 #ifndef _RTL819XU_HTTYPE_H_
8 #define _RTL819XU_HTTYPE_H_
9
10 #define MIMO_PS_STATIC 0
11
12 #define sHTCLng 4
13
14 enum ht_channel_width {
15 HT_CHANNEL_WIDTH_20 = 0,
16 HT_CHANNEL_WIDTH_20_40 = 1,
17 };
18
19 enum ht_extchnl_offset {
20 HT_EXTCHNL_OFFSET_NO_EXT = 0,
21 HT_EXTCHNL_OFFSET_UPPER = 1,
22 HT_EXTCHNL_OFFSET_NO_DEF = 2,
23 HT_EXTCHNL_OFFSET_LOWER = 3,
24 };
25
26 struct ht_capab_ele {
27
28 u8 AdvCoding:1;
29 u8 ChlWidth:1;
30 u8 MimoPwrSave:2;
31 u8 GreenField:1;
32 u8 ShortGI20Mhz:1;
33 u8 ShortGI40Mhz:1;
34 u8 TxSTBC:1;
35 u8 RxSTBC:2;
36 u8 DelayBA:1;
37 u8 MaxAMSDUSize:1;
38 u8 DssCCk:1;
39 u8 PSMP:1;
40 u8 Rsvd1:1;
41 u8 LSigTxopProtect:1;
42
43 u8 MaxRxAMPDUFactor:2;
44 u8 MPDUDensity:3;
45 u8 Rsvd2:3;
46
47 u8 MCS[16];
48
49
50 u16 ExtHTCapInfo;
51
52 u8 TxBFCap[4];
53
54 u8 ASCap;
55
56 } __packed;
57
58
59 struct ht_info_ele {
60 u8 ControlChl;
61
62 u8 ExtChlOffset:2;
63 u8 RecommemdedTxWidth:1;
64 u8 RIFS:1;
65 u8 PSMPAccessOnly:1;
66 u8 SrvIntGranularity:3;
67
68 u8 OptMode:2;
69 u8 NonGFDevPresent:1;
70 u8 Revd1:5;
71 u8 Revd2:8;
72
73 u8 Rsvd3:6;
74 u8 DualBeacon:1;
75 u8 DualCTSProtect:1;
76
77 u8 SecondaryBeacon:1;
78 u8 LSigTxopProtectFull:1;
79 u8 PcoActive:1;
80 u8 PcoPhase:1;
81 u8 Rsvd4:4;
82
83 u8 BasicMSC[16];
84 } __packed;
85
86 enum ht_spec_ver {
87 HT_SPEC_VER_IEEE = 0,
88 HT_SPEC_VER_EWC = 1,
89 };
90
91 enum ht_aggre_mode {
92 HT_AGG_AUTO = 0,
93 HT_AGG_FORCE_ENABLE = 1,
94 HT_AGG_FORCE_DISABLE = 2,
95 };
96
97
98 struct rt_hi_throughput {
99 u8 bEnableHT;
100 u8 bCurrentHTSupport;
101
102 u8 bRegBW40MHz;
103 u8 bCurBW40MHz;
104
105 u8 bRegShortGI40MHz;
106 u8 bCurShortGI40MHz;
107
108 u8 bRegShortGI20MHz;
109 u8 bCurShortGI20MHz;
110
111 u8 bRegSuppCCK;
112 u8 bCurSuppCCK;
113
114 enum ht_spec_ver ePeerHTSpecVer;
115
116
117 struct ht_capab_ele SelfHTCap;
118 struct ht_info_ele SelfHTInfo;
119
120 u8 PeerHTCapBuf[32];
121 u8 PeerHTInfoBuf[32];
122
123
124 u8 bAMSDU_Support;
125 u16 nAMSDU_MaxSize;
126 u8 bCurrent_AMSDU_Support;
127 u16 nCurrent_AMSDU_MaxSize;
128
129 u8 bAMPDUEnable;
130 u8 bCurrentAMPDUEnable;
131 u8 AMPDU_Factor;
132 u8 CurrentAMPDUFactor;
133 u8 MPDU_Density;
134 u8 CurrentMPDUDensity;
135
136 enum ht_aggre_mode ForcedAMPDUMode;
137 u8 ForcedAMPDUFactor;
138 u8 ForcedMPDUDensity;
139
140 enum ht_aggre_mode ForcedAMSDUMode;
141 u16 ForcedAMSDUMaxSize;
142
143 u8 bForcedShortGI;
144
145 u8 CurrentOpMode;
146
147 u8 SelfMimoPs;
148 u8 PeerMimoPs;
149
150 enum ht_extchnl_offset CurSTAExtChnlOffset;
151 u8 bCurTxBW40MHz;
152 u8 PeerBandwidth;
153
154 u8 bSwBwInProgress;
155 u8 SwBwStep;
156
157 u8 bRegRT2RTAggregation;
158 u8 RT2RT_HT_Mode;
159 u8 bCurrentRT2RTAggregation;
160 u8 bCurrentRT2RTLongSlotTime;
161 u8 szRT2RTAggBuffer[10];
162
163 u8 bRegRxReorderEnable;
164 u8 bCurRxReorderEnable;
165 u8 RxReorderWinSize;
166 u8 RxReorderPendingTime;
167 u16 RxReorderDropCounter;
168
169 u8 bIsPeerBcm;
170
171 u8 IOTPeer;
172 u32 IOTAction;
173 u8 IOTRaFunc;
174
175 u8 bWAIotBroadcom;
176 u8 WAIotTH;
177
178 u8 bAcceptAddbaReq;
179 } __packed;
180
181 struct bss_ht {
182
183 u8 bdSupportHT;
184
185 u8 bdHTCapBuf[32];
186 u16 bdHTCapLen;
187 u8 bdHTInfoBuf[32];
188 u16 bdHTInfoLen;
189
190 enum ht_spec_ver bdHTSpecVer;
191 enum ht_channel_width bdBandWidth;
192
193 u8 bdRT2RTAggregation;
194 u8 bdRT2RTLongSlotTime;
195 u8 RT2RT_HT_Mode;
196 u8 bdHT1R;
197 };
198
199 extern u8 MCS_FILTER_ALL[16];
200 extern u8 MCS_FILTER_1SS[16];
201
202 #define RATE_ADPT_1SS_MASK 0xFF
203 #define RATE_ADPT_2SS_MASK 0xF0
204 #define RATE_ADPT_MCS32_MASK 0x01
205
206 enum ht_aggre_size {
207 HT_AGG_SIZE_8K = 0,
208 HT_AGG_SIZE_16K = 1,
209 HT_AGG_SIZE_32K = 2,
210 HT_AGG_SIZE_64K = 3,
211 };
212
213 enum ht_iot_peer {
214 HT_IOT_PEER_UNKNOWN = 0,
215 HT_IOT_PEER_REALTEK = 1,
216 HT_IOT_PEER_REALTEK_92SE = 2,
217 HT_IOT_PEER_BROADCOM = 3,
218 HT_IOT_PEER_RALINK = 4,
219 HT_IOT_PEER_ATHEROS = 5,
220 HT_IOT_PEER_CISCO = 6,
221 HT_IOT_PEER_MARVELL = 7,
222 HT_IOT_PEER_92U_SOFTAP = 8,
223 HT_IOT_PEER_SELF_SOFTAP = 9,
224 HT_IOT_PEER_AIRGO = 10,
225 HT_IOT_PEER_MAX = 11,
226 };
227
228 enum ht_iot_action {
229 HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
230 HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
231 HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
232 HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
233 HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
234 HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
235 HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
236 HT_IOT_ACT_CDD_FSYNC = 0x00000080,
237 HT_IOT_ACT_PURE_N_MODE = 0x00000100,
238 HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
239 HT_IOT_ACT_FORCED_RTS = 0x00000400,
240 HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
241 HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
242 HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
243 HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
244
245 HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
246 HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
247 HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
248 HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
249 HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
250 HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
251
252 HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
253 HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
254
255 HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
256 HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
257 HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
258
259 HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
260
261 };
262
263 enum ht_iot_rafunc {
264 HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
265 HT_IOT_RAFUNC_PEER_1R = 0x01,
266 HT_IOT_RAFUNC_TX_AMSDU = 0x02,
267 };
268
269 enum rt_ht_capability {
270 RT_HT_CAP_USE_TURBO_AGGR = 0x01,
271 RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
272 RT_HT_CAP_USE_AMPDU = 0x04,
273 RT_HT_CAP_USE_WOW = 0x8,
274 RT_HT_CAP_USE_SOFTAP = 0x10,
275 RT_HT_CAP_USE_92SE = 0x20,
276 };
277
278 #endif