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7 #ifndef R8190P_DEF_H
8 #define R8190P_DEF_H
9
10 #include <linux/types.h>
11
12 #define MAX_SILENT_RESET_RX_SLOT_NUM 10
13
14 #define RX_MPDU_QUEUE 0
15
16 enum rtl819x_loopback {
17 RTL819X_NO_LOOPBACK = 0,
18 RTL819X_MAC_LOOPBACK = 1,
19 RTL819X_DMA_LOOPBACK = 2,
20 RTL819X_CCK_LOOPBACK = 3,
21 };
22
23 #define DESC90_RATE1M 0x00
24 #define DESC90_RATE2M 0x01
25 #define DESC90_RATE5_5M 0x02
26 #define DESC90_RATE11M 0x03
27 #define DESC90_RATE6M 0x04
28 #define DESC90_RATE9M 0x05
29 #define DESC90_RATE12M 0x06
30 #define DESC90_RATE18M 0x07
31 #define DESC90_RATE24M 0x08
32 #define DESC90_RATE36M 0x09
33 #define DESC90_RATE48M 0x0a
34 #define DESC90_RATE54M 0x0b
35 #define DESC90_RATEMCS0 0x00
36 #define DESC90_RATEMCS1 0x01
37 #define DESC90_RATEMCS2 0x02
38 #define DESC90_RATEMCS3 0x03
39 #define DESC90_RATEMCS4 0x04
40 #define DESC90_RATEMCS5 0x05
41 #define DESC90_RATEMCS6 0x06
42 #define DESC90_RATEMCS7 0x07
43 #define DESC90_RATEMCS8 0x08
44 #define DESC90_RATEMCS9 0x09
45 #define DESC90_RATEMCS10 0x0a
46 #define DESC90_RATEMCS11 0x0b
47 #define DESC90_RATEMCS12 0x0c
48 #define DESC90_RATEMCS13 0x0d
49 #define DESC90_RATEMCS14 0x0e
50 #define DESC90_RATEMCS15 0x0f
51 #define DESC90_RATEMCS32 0x20
52
53 #define SHORT_SLOT_TIME 9
54 #define NON_SHORT_SLOT_TIME 20
55
56 #define RX_SMOOTH 20
57
58 #define QSLT_BK 0x1
59 #define QSLT_BE 0x0
60 #define QSLT_VI 0x4
61 #define QSLT_VO 0x6
62 #define QSLT_BEACON 0x10
63 #define QSLT_HIGH 0x11
64 #define QSLT_MGNT 0x12
65 #define QSLT_CMD 0x13
66
67 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
68 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
69 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
70 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
71 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
72 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
73 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
74
75 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
76 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
77 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
78 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
79 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
80 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
81 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
82 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
83
84 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
85 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
86 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
87
88
89 enum version_8190_loopback {
90 VERSION_8190_BD = 0x3,
91 VERSION_8190_BE
92 };
93
94 #define IC_VersionCut_C 0x2
95 #define IC_VersionCut_D 0x3
96 #define IC_VersionCut_E 0x4
97
98 enum rf_optype {
99 RF_OP_By_SW_3wire = 0,
100 RF_OP_By_FW,
101 RF_OP_MAX
102 };
103
104 struct bb_reg_definition {
105 u32 rfintfs;
106 u32 rfintfi;
107 u32 rfintfo;
108 u32 rfintfe;
109 u32 rf3wireOffset;
110 u32 rfLSSI_Select;
111 u32 rfTxGainStage;
112 u32 rfHSSIPara1;
113 u32 rfHSSIPara2;
114 u32 rfSwitchControl;
115 u32 rfAGCControl1;
116 u32 rfAGCControl2;
117 u32 rfRxIQImbalance;
118 u32 rfRxAFE;
119 u32 rfTxIQImbalance;
120 u32 rfTxAFE;
121 u32 rfLSSIReadBack;
122 u32 rfLSSIReadBackPi;
123 };
124
125 struct tx_fwinfo_8190pci {
126 u8 TxRate:7;
127 u8 CtsEnable:1;
128 u8 RtsRate:7;
129 u8 RtsEnable:1;
130 u8 TxHT:1;
131 u8 Short:1;
132 u8 TxBandwidth:1;
133 u8 TxSubCarrier:2;
134 u8 STBC:2;
135 u8 AllowAggregation:1;
136 u8 RtsHT:1;
137 u8 RtsShort:1;
138 u8 RtsBandwidth:1;
139 u8 RtsSubcarrier:2;
140 u8 RtsSTBC:2;
141 u8 EnableCPUDur:1;
142
143 u32 RxMF:2;
144 u32 RxAMD:3;
145 u32 TxPerPktInfoFeedback:1;
146 u32 Reserved1:2;
147 u32 TxAGCOffset:4;
148 u32 TxAGCSign:1;
149 u32 RAW_TXD:1;
150 u32 Retry_Limit:4;
151 u32 Reserved2:1;
152 u32 PacketID:13;
153
154
155 };
156
157 struct log_int_8190 {
158 u32 nIMR_COMDOK;
159 u32 nIMR_MGNTDOK;
160 u32 nIMR_HIGH;
161 u32 nIMR_VODOK;
162 u32 nIMR_VIDOK;
163 u32 nIMR_BEDOK;
164 u32 nIMR_BKDOK;
165 u32 nIMR_ROK;
166 u32 nIMR_RCOK;
167 u32 nIMR_TBDOK;
168 u32 nIMR_BDOK;
169 u32 nIMR_RXFOVW;
170 };
171
172 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
173 u8 reserved:4;
174 u8 rxsc:2;
175 u8 sgi_en:1;
176 u8 ex_intf_flag:1;
177 };
178
179 struct phy_sts_ofdm_819xpci {
180 u8 trsw_gain_X[4];
181 u8 pwdb_all;
182 u8 cfosho_X[4];
183 u8 cfotail_X[4];
184 u8 rxevm_X[2];
185 u8 rxsnr_X[4];
186 u8 pdsnr_X[2];
187 u8 csi_current_X[2];
188 u8 csi_target_X[2];
189 u8 sigevm;
190 u8 max_ex_pwr;
191 u8 sgi_en;
192 u8 rxsc_sgien_exflg;
193 };
194
195 struct phy_sts_cck_819xpci {
196 u8 adc_pwdb_X[4];
197 u8 sq_rpt;
198 u8 cck_agc_rpt;
199 };
200
201
202 #define PHY_RSSI_SLID_WIN_MAX 100
203 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
204
205 struct tx_desc {
206 u16 PktSize;
207 u8 Offset;
208 u8 Reserved1:3;
209 u8 CmdInit:1;
210 u8 LastSeg:1;
211 u8 FirstSeg:1;
212 u8 LINIP:1;
213 u8 OWN:1;
214
215 u8 TxFWInfoSize;
216 u8 RATid:3;
217 u8 DISFB:1;
218 u8 USERATE:1;
219 u8 MOREFRAG:1;
220 u8 NoEnc:1;
221 u8 PIFS:1;
222 u8 QueueSelect:5;
223 u8 NoACM:1;
224 u8 Resv:2;
225 u8 SecCAMID:5;
226 u8 SecDescAssign:1;
227 u8 SecType:2;
228
229 u16 TxBufferSize;
230 u8 PktId:7;
231 u8 Resv1:1;
232 u8 Reserved2;
233
234 u32 TxBuffAddr;
235
236 u32 NextDescAddress;
237
238 u32 Reserved5;
239 u32 Reserved6;
240 u32 Reserved7;
241 };
242
243
244 struct tx_desc_cmd {
245 u16 PktSize;
246 u8 Reserved1;
247 u8 CmdType:3;
248 u8 CmdInit:1;
249 u8 LastSeg:1;
250 u8 FirstSeg:1;
251 u8 LINIP:1;
252 u8 OWN:1;
253
254 u16 ElementReport;
255 u16 Reserved2;
256
257 u16 TxBufferSize;
258 u16 Reserved3;
259
260 u32 TxBuffAddr;
261 u32 NextDescAddress;
262 u32 Reserved4;
263 u32 Reserved5;
264 u32 Reserved6;
265 };
266
267 struct rx_desc {
268 u16 Length:14;
269 u16 CRC32:1;
270 u16 ICV:1;
271 u8 RxDrvInfoSize;
272 u8 Shift:2;
273 u8 PHYStatus:1;
274 u8 SWDec:1;
275 u8 LastSeg:1;
276 u8 FirstSeg:1;
277 u8 EOR:1;
278 u8 OWN:1;
279
280 u32 Reserved2;
281
282 u32 Reserved3;
283
284 u32 BufferAddress;
285
286 };
287
288
289 struct rx_fwinfo {
290 u16 Reserved1:12;
291 u16 PartAggr:1;
292 u16 FirstAGGR:1;
293 u16 Reserved2:2;
294
295 u8 RxRate:7;
296 u8 RxHT:1;
297
298 u8 BW:1;
299 u8 SPLCP:1;
300 u8 Reserved3:2;
301 u8 PAM:1;
302 u8 Mcast:1;
303 u8 Bcast:1;
304 u8 Reserved4:1;
305
306 u32 TSFL;
307
308 };
309
310 #endif