root/drivers/staging/rtl8192u/r819xU_phyreg.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _R819XU_PHYREG_H
   3 #define _R819XU_PHYREG_H
   4 
   5 
   6 #define   RF_DATA                               0x1d4                                   /* FW will write RF data in the register.*/
   7 
   8 /* page8 */
   9 #define rFPGA0_RFMOD                            0x800  /* RF mode & CCK TxSC */
  10 #define rFPGA0_TxGainStage                      0x80c
  11 #define rFPGA0_XA_HSSIParameter1        0x820
  12 #define rFPGA0_XA_HSSIParameter2        0x824
  13 #define rFPGA0_XB_HSSIParameter1        0x828
  14 #define rFPGA0_XB_HSSIParameter2        0x82c
  15 #define rFPGA0_XC_HSSIParameter1        0x830
  16 #define rFPGA0_XC_HSSIParameter2        0x834
  17 #define rFPGA0_XD_HSSIParameter1        0x838
  18 #define rFPGA0_XD_HSSIParameter2        0x83c
  19 #define rFPGA0_XA_LSSIParameter         0x840
  20 #define rFPGA0_XB_LSSIParameter         0x844
  21 #define rFPGA0_XC_LSSIParameter         0x848
  22 #define rFPGA0_XD_LSSIParameter         0x84c
  23 #define rFPGA0_XAB_SwitchControl        0x858
  24 #define rFPGA0_XCD_SwitchControl        0x85c
  25 #define rFPGA0_XA_RFInterfaceOE         0x860
  26 #define rFPGA0_XB_RFInterfaceOE         0x864
  27 #define rFPGA0_XC_RFInterfaceOE         0x868
  28 #define rFPGA0_XD_RFInterfaceOE         0x86c
  29 #define rFPGA0_XAB_RFInterfaceSW        0x870
  30 #define rFPGA0_XCD_RFInterfaceSW        0x874
  31 #define rFPGA0_XAB_RFParameter          0x878
  32 #define rFPGA0_XCD_RFParameter          0x87c
  33 #define rFPGA0_AnalogParameter1         0x880
  34 #define rFPGA0_AnalogParameter4         0x88c
  35 #define rFPGA0_XA_LSSIReadBack          0x8a0
  36 #define rFPGA0_XB_LSSIReadBack          0x8a4
  37 #define rFPGA0_XC_LSSIReadBack          0x8a8
  38 #define rFPGA0_XD_LSSIReadBack          0x8ac
  39 #define rFPGA0_XAB_RFInterfaceRB        0x8e0
  40 #define rFPGA0_XCD_RFInterfaceRB        0x8e4
  41 
  42 /* page 9 */
  43 #define rFPGA1_RFMOD                            0x900  /* RF mode & OFDM TxSC */
  44 
  45 /* page a */
  46 #define rCCK0_System                            0xa00
  47 #define rCCK0_AFESetting                        0xa04
  48 #define rCCK0_CCA                                       0xa08
  49 #define rCCK0_TxFilter1                         0xa20
  50 #define rCCK0_TxFilter2                         0xa24
  51 #define rCCK0_DebugPort                         0xa28  /* debug port and Tx filter3 */
  52 
  53 /* page c */
  54 #define rOFDM0_TRxPathEnable            0xc04
  55 #define rOFDM0_XARxAFE                          0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
  56 #define rOFDM0_XARxIQImbalance          0xc14  /* RxIQ imbalance matrix */
  57 #define rOFDM0_XBRxAFE                          0xc18
  58 #define rOFDM0_XBRxIQImbalance          0xc1c
  59 #define rOFDM0_XCRxAFE                          0xc20
  60 #define rOFDM0_XCRxIQImbalance          0xc24
  61 #define rOFDM0_XDRxAFE                          0xc28
  62 #define rOFDM0_XDRxIQImbalance          0xc2c
  63 #define rOFDM0_RxDetector1                      0xc30  /* PD,BW & SBD */
  64 #define rOFDM0_RxDetector2                      0xc34  /* SBD & Fame Sync.*/
  65 #define rOFDM0_RxDetector3                      0xc38  /* Frame Sync.*/
  66 #define rOFDM0_ECCAThreshold            0xc4c /* energy CCA */
  67 #define rOFDM0_XAAGCCore1               0xc50
  68 #define rOFDM0_XAAGCCore2               0xc54
  69 #define rOFDM0_XBAGCCore1               0xc58
  70 #define rOFDM0_XBAGCCore2               0xc5c
  71 #define rOFDM0_XCAGCCore1               0xc60
  72 #define rOFDM0_XCAGCCore2               0xc64
  73 #define rOFDM0_XDAGCCore1               0xc68
  74 #define rOFDM0_XDAGCCore2               0xc6c
  75 #define rOFDM0_XATxIQImbalance          0xc80
  76 #define rOFDM0_XATxAFE                          0xc84
  77 #define rOFDM0_XBTxIQImbalance          0xc88
  78 #define rOFDM0_XBTxAFE                          0xc8c
  79 #define rOFDM0_XCTxIQImbalance          0xc90
  80 #define rOFDM0_XCTxAFE                          0xc94
  81 #define rOFDM0_XDTxIQImbalance          0xc98
  82 #define rOFDM0_XDTxAFE                          0xc9c
  83 
  84 
  85 /* page d */
  86 #define rOFDM1_LSTF                             0xd00
  87 #define rOFDM1_TRxPathEnable            0xd04
  88 
  89 /* page e */
  90 #define rTxAGC_Rate18_06                        0xe00
  91 #define rTxAGC_Rate54_24                        0xe04
  92 #define rTxAGC_CCK_Mcs32                        0xe08
  93 #define rTxAGC_Mcs03_Mcs00                      0xe10
  94 #define rTxAGC_Mcs07_Mcs04                      0xe14
  95 #define rTxAGC_Mcs11_Mcs08                      0xe18
  96 #define rTxAGC_Mcs15_Mcs12                      0xe1c
  97 
  98 
  99 /* RF
 100  * Zebra1
 101  */
 102 #define rZebra1_Channel                         0x7
 103 
 104 /* Zebra4 */
 105 #define rGlobalCtrl                             0
 106 
 107 /* Bit Mask
 108  * page-8
 109  */
 110 #define bRFMOD                                          0x1
 111 #define bCCKEn                                          0x1000000
 112 #define bOFDMEn                                         0x2000000
 113 #define bXBTxAGC                                        0xf00
 114 #define bXCTxAGC                                        0xf000
 115 #define b3WireDataLength                        0x800
 116 #define b3WireAddressLength                     0x400
 117 #define bRFSI_RFENV                             0x10
 118 #define bLSSIReadAddress                        0x3f000000   /* LSSI "Read" Address */
 119 #define bLSSIReadEdge                           0x80000000   /* LSSI "Read" edge signal */
 120 #define bLSSIReadBackData                       0xfff
 121 #define bXtalCap                                        0x0f000000
 122 
 123 /* page-a */
 124 #define bCCKSideBand                            0x10
 125 
 126 /* page e */
 127 #define bTxAGCRateCCK                   0x7f00
 128 
 129 /* RF
 130  * Zebra1
 131  */
 132 #define bZebra1_ChannelNum        0xf80
 133 
 134 /* RTL8258 */
 135 /* for PutRegsetting & GetRegSetting BitMask */
 136 #define bMaskByte0                0xff
 137 #define bMaskByte1                0xff00
 138 #define bMaskByte2                0xff0000
 139 #define bMaskHWord                0xffff0000
 140 #define bMaskLWord                0x0000ffff
 141 #define bMaskDWord                0xffffffff
 142 
 143 /* for PutRFRegsetting & GetRFRegSetting BitMask */
 144 #define bMask12Bits               0xfff
 145 
 146 #endif  /* __INC_HAL8190PCIPHYREG_H */