1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * This is part of rtl8187 OpenSource driver.
4 * Copyright (C) Andrea Merello 2004-2005 <andrea.merello@gmail.com>
5 *
6 * Parts of this driver are based on the GPL part of the
7 * official Realtek driver.
8 * Parts of this driver are based on the rtl8180 driver skeleton
9 * from Patric Schenke & Andres Salomon.
10 * Parts of this driver are based on the Intel Pro Wireless
11 * 2100 GPL driver.
12 *
13 * We want to thank the Authors of those projects
14 * and the Ndiswrapper project Authors.
15 */
16
17 /* Mariusz Matuszek added full registers definition with Realtek's name */
18
19 /* this file contains register definitions for the rtl8187 MAC controller */
20 #ifndef R8192_HW
21 #define R8192_HW
22
23 #define RTL8187_REQT_READ 0xc0
24 #define RTL8187_REQT_WRITE 0x40
25 #define RTL8187_REQ_GET_REGS 0x05
26 #define RTL8187_REQ_SET_REGS 0x05
27
28 #define MAX_TX_URB 5
29 #define MAX_RX_URB 16
30
31 #define R8180_MAX_RETRY 255
32
33 #define RX_URB_SIZE 9100
34
35 #define RTL8190_EEPROM_ID 0x8129
36 #define EEPROM_VID 0x02
37 #define EEPROM_PID 0x04
38 #define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
39
40 #define EEPROM_TX_POWER_DIFF 0x1F
41 #define EEPROM_THERMAL_METER 0x20
42 #define EEPROM_PW_DIFF 0x21 //0x21
43 #define EEPROM_CRYSTAL_CAP 0x22 //0x22
44
45 #define EEPROM_TX_PW_INDEX_CCK 0x23 //0x23
46 #define EEPROM_TX_PW_INDEX_OFDM_24G 0x24 //0x24~0x26
47 #define EEPROM_TX_PW_INDEX_CCK_V1 0x29 //0x29~0x2B
48 #define EEPROM_TX_PW_INDEX_OFDM_24G_V1 0x2C //0x2C~0x2E
49 #define EEPROM_TX_PW_INDEX_VER 0x27 //0x27
50
51 #define EEPROM_DEFAULT_THERNAL_METER 0x7
52 #define EEPROM_DEFAULT_PW_DIFF 0x4
53 #define EEPROM_DEFAULT_CRYSTAL_CAP 0x5
54 #define EEPROM_DEFAULT_TX_POWER 0x1010
55 #define EEPROM_CUSTOMER_ID 0x7B //0x7B:CustomerID
56 #define EEPROM_CHANNEL_PLAN 0x16 //0x7C
57
58 #define EEPROM_CID_RUNTOP 0x2
59 #define EEPROM_CID_DLINK 0x8
60
61 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
62 #define AC_PARAM_ECW_MAX_OFFSET 12
63 #define AC_PARAM_ECW_MIN_OFFSET 8
64 #define AC_PARAM_AIFS_OFFSET 0
65
66 //#endif
67 enum _RTL8192Usb_HW {
68 MAC0 = 0x000,
69 MAC4 = 0x004,
70
71 #define BB_GLOBAL_RESET_BIT 0x1
72 BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register
73 BSSIDR = 0x02E, // BSSID Register
74 CMDR = 0x037, // Command register
75 #define CR_RE 0x08
76 #define CR_TE 0x04
77 SIFS = 0x03E, // SIFS register
78
79 #define TCR_MXDMA_2048 7
80 #define TCR_LRL_OFFSET 0
81 #define TCR_SRL_OFFSET 8
82 #define TCR_MXDMA_OFFSET 21
83 #define TCR_SAT BIT(24) // Enable Rate depedent ack timeout timer
84 RCR = 0x044, // Receive Configuration Register
85 #define MAC_FILTER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | \
86 BIT(12) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \
87 BIT(22) | BIT(23))
88 #define RX_FIFO_THRESHOLD_MASK (BIT(13) | BIT(14) | BIT(15))
89 #define RX_FIFO_THRESHOLD_SHIFT 13
90 #define RX_FIFO_THRESHOLD_NONE 7
91 #define MAX_RX_DMA_MASK (BIT(8) | BIT(9) | BIT(10))
92 #define RCR_MXDMA_OFFSET 8
93 #define RCR_FIFO_OFFSET 13
94 #define RCR_ONLYERLPKT BIT(31) // Early Receiving based on Packet Size.
95 #define RCR_CBSSID BIT(23) // Accept BSSID match packet
96 #define RCR_APWRMGT BIT(22) // Accept power management packet
97 #define RCR_AMF BIT(20) // Accept management type frame
98 #define RCR_ACF BIT(19) // Accept control type frame
99 #define RCR_ADF BIT(18) // Accept data type frame
100 #define RCR_AICV BIT(12) // Accept ICV error packet
101 #define RCR_ACRC32 BIT(5) // Accept CRC32 error packet
102 #define RCR_AB BIT(3) // Accept broadcast packet
103 #define RCR_AM BIT(2) // Accept multicast packet
104 #define RCR_APM BIT(1) // Accept physical match packet
105 #define RCR_AAP BIT(0) // Accept all unicast packet
106 SLOT_TIME = 0x049, // Slot Time Register
107 ACK_TIMEOUT = 0x04c, // Ack Timeout Register
108 EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE
109 EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK
110 EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO
111 EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI
112 BCN_TCFG = 0x062, // Beacon Time Configuration
113 #define BCN_TCFG_CW_SHIFT 8
114 #define BCN_TCFG_IFS 0
115 BCN_INTERVAL = 0x070, // Beacon Interval (TU)
116 ATIMWND = 0x072, // ATIM Window Size (TU)
117 BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT
118 BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA
119 BCN_ERR_THRESH = 0x078, // Beacon Error Threshold
120 RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd
121 WCAMI = 0x0A4, // Software write CAM input content
122 SECR = 0x0B0, //Security Configuration Register
123 #define SCR_TxUseDK BIT(0) //Force Tx Use Default Key
124 #define SCR_RxUseDK BIT(1) //Force Rx Use Default Key
125 #define SCR_TxEncEnable BIT(2) //Enable Tx Encryption
126 #define SCR_RxDecEnable BIT(3) //Enable Rx Decryption
127 #define SCR_SKByA2 BIT(4) //Search kEY BY A2
128 #define SCR_NoSKMC BIT(5) //No Key Search for Multicast
129
130 //----------------------------------------------------------------------------
131 // 8190 CPU General Register (offset 0x100, 4 byte)
132 //----------------------------------------------------------------------------
133 #define CPU_CCK_LOOPBACK 0x00030000
134 #define CPU_GEN_SYSTEM_RESET 0x00000001
135 #define CPU_GEN_FIRMWARE_RESET 0x00000008
136 #define CPU_GEN_BOOT_RDY 0x00000010
137 #define CPU_GEN_FIRM_RDY 0x00000020
138 #define CPU_GEN_PUT_CODE_OK 0x00000080
139 #define CPU_GEN_BB_RST 0x00000100
140 #define CPU_GEN_PWR_STB_CPU 0x00000004
141 #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
142 #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
143 CPU_GEN = 0x100, // CPU Reset Register
144
145 AcmHwCtrl = 0x171, // ACM Hardware Control Register
146 //----------------------------------------------------------------------------
147 ////
148 //// 8190 AcmHwCtrl bits (offset 0x171, 1 byte)
149 ////----------------------------------------------------------------------------
150 //
151 #define AcmHw_BeqEn BIT(1)
152
153 RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk
154 RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High
155 RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public,
156 QPNR = 0x1D0, //0x1F0, // Queue Packet Number report per TID
157
158 #define BW_OPMODE_5G BIT(1)
159 #define BW_OPMODE_20MHZ BIT(2)
160 BW_OPMODE = 0x300, // Bandwidth operation mode
161 MSR = 0x303, // Media Status register
162 #define MSR_LINK_MASK (BIT(0)|BIT(1))
163 #define MSR_LINK_MANAGED 2
164 #define MSR_LINK_NONE 0
165 #define MSR_LINK_SHIFT 0
166 #define MSR_LINK_ADHOC 1
167 #define MSR_LINK_MASTER 3
168 RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long
169 #define RETRY_LIMIT_SHORT_SHIFT 8
170 #define RETRY_LIMIT_LONG_SHIFT 0
171 RRSR = 0x310, // Response Rate Set
172 #define RRSR_1M BIT(0)
173 #define RRSR_2M BIT(1)
174 #define RRSR_5_5M BIT(2)
175 #define RRSR_11M BIT(3)
176 #define RRSR_6M BIT(4)
177 #define RRSR_9M BIT(5)
178 #define RRSR_12M BIT(6)
179 #define RRSR_18M BIT(7)
180 #define RRSR_24M BIT(8)
181 #define RRSR_36M BIT(9)
182 #define RRSR_48M BIT(10)
183 #define RRSR_54M BIT(11)
184 #define BRSR_AckShortPmb BIT(23) // CCK ACK: use Short Preamble or not.
185 UFWP = 0x318,
186 RATR0 = 0x320, // Rate Adaptive Table register1
187 DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI
188 //----------------------------------------------------------------------------
189 // 8190 Rate Adaptive Table Register (offset 0x320, 4 byte)
190 //----------------------------------------------------------------------------
191 //CCK
192 #define RATR_1M 0x00000001
193 #define RATR_2M 0x00000002
194 #define RATR_55M 0x00000004
195 #define RATR_11M 0x00000008
196 //OFDM
197 #define RATR_6M 0x00000010
198 #define RATR_9M 0x00000020
199 #define RATR_12M 0x00000040
200 #define RATR_18M 0x00000080
201 #define RATR_24M 0x00000100
202 #define RATR_36M 0x00000200
203 #define RATR_48M 0x00000400
204 #define RATR_54M 0x00000800
205 //MCS 1 Spatial Stream
206 #define RATR_MCS0 0x00001000
207 #define RATR_MCS1 0x00002000
208 #define RATR_MCS2 0x00004000
209 #define RATR_MCS3 0x00008000
210 #define RATR_MCS4 0x00010000
211 #define RATR_MCS5 0x00020000
212 #define RATR_MCS6 0x00040000
213 #define RATR_MCS7 0x00080000
214 //MCS 2 Spatial Stream
215 #define RATR_MCS8 0x00100000
216 #define RATR_MCS9 0x00200000
217 #define RATR_MCS10 0x00400000
218 #define RATR_MCS11 0x00800000
219 #define RATR_MCS12 0x01000000
220 #define RATR_MCS13 0x02000000
221 #define RATR_MCS14 0x04000000
222 #define RATR_MCS15 0x08000000
223 // ALL CCK Rate
224 #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
225 #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\
226 |RATR_36M|RATR_48M|RATR_54M
227 #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \
228 RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7
229 #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \
230 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
231
232 EPROM_CMD = 0xfe58,
233 #define Cmd9346CR_9356SEL BIT(4)
234 #define EPROM_CMD_OPERATING_MODE_SHIFT 6
235 #define EPROM_CMD_NORMAL 0
236 #define EPROM_CMD_PROGRAM 2
237 #define EPROM_CS_BIT BIT(3)
238 #define EPROM_CK_BIT BIT(2)
239 #define EPROM_W_BIT BIT(1)
240 #define EPROM_R_BIT BIT(0)
241 };
242 //----------------------------------------------------------------------------
243 // 818xB AnaParm & AnaParm2 Register
244 //----------------------------------------------------------------------------
245 #define GPI 0x108
246 #endif