root/drivers/staging/most/dim2/reg.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * reg.h - Definitions for registers of DIM2
   4  * (MediaLB, Device Interface Macro IP, OS62420)
   5  *
   6  * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG
   7  */
   8 
   9 #ifndef DIM2_OS62420_H
  10 #define DIM2_OS62420_H
  11 
  12 #include <linux/types.h>
  13 
  14 struct dim2_regs {
  15         u32 MLBC0;       /* 0x00 */
  16         u32 rsvd0[1];    /* 0x01 */
  17         u32 MLBPC0;      /* 0x02 */
  18         u32 MS0;         /* 0x03 */
  19         u32 rsvd1[1];    /* 0x04 */
  20         u32 MS1;         /* 0x05 */
  21         u32 rsvd2[2];    /* 0x06 */
  22         u32 MSS;         /* 0x08 */
  23         u32 MSD;         /* 0x09 */
  24         u32 rsvd3[1];    /* 0x0A */
  25         u32 MIEN;        /* 0x0B */
  26         u32 rsvd4[1];    /* 0x0C */
  27         u32 MLBPC2;      /* 0x0D */
  28         u32 MLBPC1;      /* 0x0E */
  29         u32 MLBC1;       /* 0x0F */
  30         u32 rsvd5[0x10]; /* 0x10 */
  31         u32 HCTL;        /* 0x20 */
  32         u32 rsvd6[1];    /* 0x21 */
  33         u32 HCMR0;       /* 0x22 */
  34         u32 HCMR1;       /* 0x23 */
  35         u32 HCER0;       /* 0x24 */
  36         u32 HCER1;       /* 0x25 */
  37         u32 HCBR0;       /* 0x26 */
  38         u32 HCBR1;       /* 0x27 */
  39         u32 rsvd7[8];    /* 0x28 */
  40         u32 MDAT0;       /* 0x30 */
  41         u32 MDAT1;       /* 0x31 */
  42         u32 MDAT2;       /* 0x32 */
  43         u32 MDAT3;       /* 0x33 */
  44         u32 MDWE0;       /* 0x34 */
  45         u32 MDWE1;       /* 0x35 */
  46         u32 MDWE2;       /* 0x36 */
  47         u32 MDWE3;       /* 0x37 */
  48         u32 MCTL;        /* 0x38 */
  49         u32 MADR;        /* 0x39 */
  50         u32 rsvd8[0xb6]; /* 0x3A */
  51         u32 ACTL;        /* 0xF0 */
  52         u32 rsvd9[3];    /* 0xF1 */
  53         u32 ACSR0;       /* 0xF4 */
  54         u32 ACSR1;       /* 0xF5 */
  55         u32 ACMR0;       /* 0xF6 */
  56         u32 ACMR1;       /* 0xF7 */
  57 };
  58 
  59 #define DIM2_MASK(n)  (~((~(u32)0) << (n)))
  60 
  61 enum {
  62         MLBC0_MLBLK_BIT = 7,
  63 
  64         MLBC0_MLBPEN_BIT = 5,
  65 
  66         MLBC0_MLBCLK_SHIFT = 2,
  67         MLBC0_MLBCLK_VAL_256FS = 0,
  68         MLBC0_MLBCLK_VAL_512FS = 1,
  69         MLBC0_MLBCLK_VAL_1024FS = 2,
  70         MLBC0_MLBCLK_VAL_2048FS = 3,
  71 
  72         MLBC0_FCNT_SHIFT = 15,
  73         MLBC0_FCNT_MASK = 7,
  74         MLBC0_FCNT_MAX_VAL = 6,
  75 
  76         MLBC0_MLBEN_BIT = 0,
  77 
  78         MIEN_CTX_BREAK_BIT = 29,
  79         MIEN_CTX_PE_BIT = 28,
  80         MIEN_CTX_DONE_BIT = 27,
  81 
  82         MIEN_CRX_BREAK_BIT = 26,
  83         MIEN_CRX_PE_BIT = 25,
  84         MIEN_CRX_DONE_BIT = 24,
  85 
  86         MIEN_ATX_BREAK_BIT = 22,
  87         MIEN_ATX_PE_BIT = 21,
  88         MIEN_ATX_DONE_BIT = 20,
  89 
  90         MIEN_ARX_BREAK_BIT = 19,
  91         MIEN_ARX_PE_BIT = 18,
  92         MIEN_ARX_DONE_BIT = 17,
  93 
  94         MIEN_SYNC_PE_BIT = 16,
  95 
  96         MIEN_ISOC_BUFO_BIT = 1,
  97         MIEN_ISOC_PE_BIT = 0,
  98 
  99         MLBC1_NDA_SHIFT = 8,
 100         MLBC1_NDA_MASK = 0xFF,
 101 
 102         MLBC1_CLKMERR_BIT = 7,
 103         MLBC1_LOCKERR_BIT = 6,
 104 
 105         ACTL_DMA_MODE_BIT = 2,
 106         ACTL_DMA_MODE_VAL_DMA_MODE_0 = 0,
 107         ACTL_DMA_MODE_VAL_DMA_MODE_1 = 1,
 108         ACTL_SCE_BIT = 0,
 109 
 110         HCTL_EN_BIT = 15
 111 };
 112 
 113 enum {
 114         CDT0_RPC_SHIFT = 16 + 11,
 115         CDT0_RPC_MASK = DIM2_MASK(5),
 116 
 117         CDT1_BS_ISOC_SHIFT = 0,
 118         CDT1_BS_ISOC_MASK = DIM2_MASK(9),
 119 
 120         CDT3_BD_SHIFT = 0,
 121         CDT3_BD_MASK = DIM2_MASK(12),
 122         CDT3_BD_ISOC_MASK = DIM2_MASK(13),
 123         CDT3_BA_SHIFT = 16,
 124 
 125         ADT0_CE_BIT = 15,
 126         ADT0_LE_BIT = 14,
 127         ADT0_PG_BIT = 13,
 128 
 129         ADT1_RDY_BIT = 15,
 130         ADT1_DNE_BIT = 14,
 131         ADT1_ERR_BIT = 13,
 132         ADT1_PS_BIT = 12,
 133         ADT1_MEP_BIT = 11,
 134         ADT1_BD_SHIFT = 0,
 135         ADT1_CTRL_ASYNC_BD_MASK = DIM2_MASK(11),
 136         ADT1_ISOC_SYNC_BD_MASK = DIM2_MASK(13),
 137 
 138         CAT_FCE_BIT = 14,
 139         CAT_MFE_BIT = 14,
 140 
 141         CAT_MT_BIT = 13,
 142 
 143         CAT_RNW_BIT = 12,
 144 
 145         CAT_CE_BIT = 11,
 146 
 147         CAT_CT_SHIFT = 8,
 148         CAT_CT_VAL_SYNC = 0,
 149         CAT_CT_VAL_CONTROL = 1,
 150         CAT_CT_VAL_ASYNC = 2,
 151         CAT_CT_VAL_ISOC = 3,
 152 
 153         CAT_CL_SHIFT = 0,
 154         CAT_CL_MASK = DIM2_MASK(6)
 155 };
 156 
 157 #endif  /* DIM2_OS62420_H */