root/drivers/staging/gs_fpgaboot/io.c

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DEFINITIONS

This source file includes following definitions.
  1. xl_shift_cclk
  2. xl_supported_prog_bus_width
  3. xl_shift_bytes_out
  4. xl_program_b
  5. xl_rdwr_b
  6. xl_csi_b
  7. xl_get_init_b
  8. xl_get_done_b
  9. byte0_out
  10. byte1_out
  11. xl_cclk_b
  12. xl_init_io

   1 // SPDX-License-Identifier: GPL-2.0+
   2 
   3 #include <linux/kernel.h>
   4 #include <linux/init.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/device.h>
   8 #include <linux/string.h>
   9 #include <linux/slab.h>
  10 #include <linux/fs.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/firmware.h>
  15 #include <linux/io.h>
  16 
  17 #include "io.h"
  18 
  19 static inline void byte0_out(unsigned char data);
  20 static inline void byte1_out(unsigned char data);
  21 static inline void xl_cclk_b(int32_t i);
  22 
  23 /* Assert and Deassert CCLK */
  24 void xl_shift_cclk(int count)
  25 {
  26         int i;
  27 
  28         for (i = 0; i < count; i++) {
  29                 xl_cclk_b(1);
  30                 xl_cclk_b(0);
  31         }
  32 }
  33 
  34 int xl_supported_prog_bus_width(enum wbus bus_bytes)
  35 {
  36         switch (bus_bytes) {
  37         case bus_1byte:
  38                 break;
  39         case bus_2byte:
  40                 break;
  41         default:
  42                 pr_err("unsupported program bus width %d\n", bus_bytes);
  43                 return 0;
  44         }
  45 
  46         return 1;
  47 }
  48 
  49 /* Serialize byte and clock each bit on target's DIN and CCLK pins */
  50 void xl_shift_bytes_out(enum wbus bus_byte, unsigned char *pdata)
  51 {
  52         /*
  53          * supports 1 and 2 bytes programming mode
  54          */
  55         if (likely(bus_byte == bus_2byte))
  56                 byte0_out(pdata[0]);
  57 
  58         byte1_out(pdata[1]);
  59         xl_shift_cclk(1);
  60 }
  61 
  62 /*
  63  * generic bit swap for xilinx SYSTEMMAP FPGA programming
  64  */
  65 void xl_program_b(int32_t i)
  66 {
  67 }
  68 
  69 void xl_rdwr_b(int32_t i)
  70 {
  71 }
  72 
  73 void xl_csi_b(int32_t i)
  74 {
  75 }
  76 
  77 int xl_get_init_b(void)
  78 {
  79         return -1;
  80 }
  81 
  82 int xl_get_done_b(void)
  83 {
  84         return -1;
  85 }
  86 
  87 static inline void byte0_out(unsigned char data)
  88 {
  89 }
  90 
  91 static inline void byte1_out(unsigned char data)
  92 {
  93 }
  94 
  95 static inline void xl_cclk_b(int32_t i)
  96 {
  97 }
  98 
  99 /*
 100  * configurable per device type for different I/O config
 101  */
 102 int xl_init_io(void)
 103 {
 104         return -1;
 105 }

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