drivers/staging/vt6655/rf.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
s_bAL7230Init
s_bAL7230SelectChannel
IFRFbWriteEmbedded
RFbAL2230Init
RFbAL2230SelectChannel
RFbInit
RFbSelectChannel
RFvWriteWakeProgSyn
RFbSetPower
RFbRawSetPower
RFvRSSITodBm
RFbAL7230SelectChannelPostProcess
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * File: rf.c
   7  *
   8  * Purpose: rf function code
   9  *
  10  * Author: Jerry Chen
  11  *
  12  * Date: Feb. 19, 2004
  13  *
  14  * Functions:
  15  *      IFRFbWriteEmbedded      - Embedded write RF register via MAC
  16  *
  17  * Revision History:
  18  *      RobertYu 2005
  19  *      chester 2008
  20  *
  21  */
  22 
  23 #include "mac.h"
  24 #include "srom.h"
  25 #include "rf.h"
  26 #include "baseband.h"
  27 
  28 #define BY_AL2230_REG_LEN     23 /* 24bit */
  29 #define CB_AL2230_INIT_SEQ    15
  30 #define SWITCH_CHANNEL_DELAY_AL2230 200 /* us */
  31 #define AL2230_PWR_IDX_LEN    64
  32 
  33 #define BY_AL7230_REG_LEN     23 /* 24bit */
  34 #define CB_AL7230_INIT_SEQ    16
  35 #define SWITCH_CHANNEL_DELAY_AL7230 200 /* us */
  36 #define AL7230_PWR_IDX_LEN    64
  37 
  38 static const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = {
  39         0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  40         0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  41         0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  42         0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  43         0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  44         0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  45         0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  46         0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  47         0x00068800 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  48         0x0403B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  49         0x00DBBA00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  50         0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  51         0x0BDFFC00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  52         0x00000D00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  53         0x00580F00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
  54 };
  55 
  56 static const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = {
  57         0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
  58         0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
  59         0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
  60         0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
  61         0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
  62         0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
  63         0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
  64         0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
  65         0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
  66         0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
  67         0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
  68         0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
  69         0x03F7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
  70         0x03E7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW  /* channel = 14, Tf = 2412M */
  71 };
  72 
  73 static const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = {
  74         0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
  75         0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
  76         0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
  77         0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
  78         0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
  79         0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
  80         0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
  81         0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
  82         0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
  83         0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
  84         0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
  85         0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
  86         0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
  87         0x06666100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW  /* channel = 14, Tf = 2412M */
  88 };
  89 
  90 static unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = {
  91         0x04040900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  92         0x04041900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  93         0x04042900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  94         0x04043900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  95         0x04044900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  96         0x04045900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  97         0x04046900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  98         0x04047900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
  99         0x04048900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 100         0x04049900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 101         0x0404A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 102         0x0404B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 103         0x0404C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 104         0x0404D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 105         0x0404E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 106         0x0404F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 107         0x04050900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 108         0x04051900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 109         0x04052900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 110         0x04053900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 111         0x04054900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 112         0x04055900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 113         0x04056900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 114         0x04057900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 115         0x04058900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 116         0x04059900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 117         0x0405A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 118         0x0405B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 119         0x0405C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 120         0x0405D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 121         0x0405E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 122         0x0405F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 123         0x04060900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 124         0x04061900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 125         0x04062900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 126         0x04063900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 127         0x04064900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 128         0x04065900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 129         0x04066900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 130         0x04067900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 131         0x04068900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 132         0x04069900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 133         0x0406A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 134         0x0406B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 135         0x0406C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 136         0x0406D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 137         0x0406E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 138         0x0406F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 139         0x04070900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 140         0x04071900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 141         0x04072900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 142         0x04073900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 143         0x04074900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 144         0x04075900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 145         0x04076900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 146         0x04077900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 147         0x04078900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 148         0x04079900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 149         0x0407A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 150         0x0407B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 151         0x0407C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 152         0x0407D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 153         0x0407E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
 154         0x0407F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
 155 };
 156 
 157 /* 40MHz reference frequency
 158  * Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
 159  */
 160 static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = {
 161         0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel1 // Need modify for 11a */
 162         0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel1 // Need modify for 11a */
 163         0x841FF200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 451FE2 */
 164         0x3FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 5FDFA3 */
 165         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11b/g    // Need modify for 11a */
 166         /* RoberYu:20050113, Rev0.47 Register Setting Guide */
 167         0x802B5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 8D1B55 */
 168         0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 169         0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 860207 */
 170         0x6EBC0800 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 171         0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 172         0xE0000A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: E0600A */
 173         0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */
 174         /* RoberYu:20050113, Rev0.47 Register Setting Guide */
 175         0x000A3C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 00143C */
 176         0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 177         0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 178         0x1ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW  /* Need modify for 11a: 12BACF */
 179 };
 180 
 181 static const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = {
 182         0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */
 183         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */
 184         0x451FE200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
 185         0x5FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
 186         0x67F78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11a    // Need modify for 11b/g */
 187         0x853F5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g, RoberYu:20050113 */
 188         0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 189         0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
 190         0x6EBC0800 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 191         0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 192         0xE0600A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
 193         0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */
 194         0x00147C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
 195         0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 196         0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
 197         0x12BACF00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW  /* Need modify for 11b/g */
 198 };
 199 
 200 static const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = {
 201         0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  1, Tf = 2412MHz */
 202         0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  2, Tf = 2417MHz */
 203         0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  3, Tf = 2422MHz */
 204         0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  4, Tf = 2427MHz */
 205         0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  5, Tf = 2432MHz */
 206         0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  6, Tf = 2437MHz */
 207         0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  7, Tf = 2442MHz */
 208         0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 */
 209         0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 */
 210         0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 */
 211         0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 */
 212         0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 */
 213         0x0037C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 */
 214         0x0037C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */
 215 
 216         /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22) */
 217         0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */
 218         0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */
 219         0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */
 220         0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */
 221         0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */
 222         0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */
 223         0x0FF53000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */
 224         0x0FF53000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */
 225 
 226         /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 227          * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 228          */
 229 
 230         0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   7, Tf = 5035MHz (23) */
 231         0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   8, Tf = 5040MHz (24) */
 232         0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   9, Tf = 5045MHz (25) */
 233         0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  11, Tf = 5055MHz (26) */
 234         0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  12, Tf = 5060MHz (27) */
 235         0x0FF55000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  16, Tf = 5080MHz (28) */
 236         0x0FF56000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  34, Tf = 5170MHz (29) */
 237         0x0FF56000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  36, Tf = 5180MHz (30) */
 238         0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 */
 239         0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  40, Tf = 5200MHz (32) */
 240         0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  42, Tf = 5210MHz (33) */
 241         0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  44, Tf = 5220MHz (34) */
 242         0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  46, Tf = 5230MHz (35) */
 243         0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  48, Tf = 5240MHz (36) */
 244         0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  52, Tf = 5260MHz (37) */
 245         0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  56, Tf = 5280MHz (38) */
 246         0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  60, Tf = 5300MHz (39) */
 247         0x0FF59000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  64, Tf = 5320MHz (40) */
 248 
 249         0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */
 250         0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */
 251         0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */
 252         0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */
 253         0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */
 254         0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */
 255         0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */
 256         0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */
 257         0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */
 258         0x0FF5F000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */
 259         0x0FF5F000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */
 260         0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */
 261         0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */
 262         0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */
 263         0x0FF61000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */
 264         0x0FF61000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW  /* channel = 165, Tf = 5825MHz (56) */
 265 };
 266 
 267 static const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = {
 268         0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  1, Tf = 2412MHz */
 269         0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  2, Tf = 2417MHz */
 270         0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  3, Tf = 2422MHz */
 271         0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  4, Tf = 2427MHz */
 272         0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  5, Tf = 2432MHz */
 273         0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  6, Tf = 2437MHz */
 274         0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  7, Tf = 2442MHz */
 275         0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  8, Tf = 2447MHz */
 276         0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  9, Tf = 2452MHz */
 277         0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
 278         0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
 279         0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
 280         0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
 281         0x06666100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */
 282 
 283         /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22) */
 284         0x1D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */
 285         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */
 286         0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */
 287         0x08000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */
 288         0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */
 289         0x0D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */
 290         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */
 291         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */
 292 
 293         /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 294          * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 295          */
 296         0x1D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   7, Tf = 5035MHz (23) */
 297         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   8, Tf = 5040MHz (24) */
 298         0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   9, Tf = 5045MHz (25) */
 299         0x08000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  11, Tf = 5055MHz (26) */
 300         0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  12, Tf = 5060MHz (27) */
 301         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  16, Tf = 5080MHz (28) */
 302         0x05555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  34, Tf = 5170MHz (29) */
 303         0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  36, Tf = 5180MHz (30) */
 304         0x10000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  38, Tf = 5190MHz (31) */
 305         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  40, Tf = 5200MHz (32) */
 306         0x1AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  42, Tf = 5210MHz (33) */
 307         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  44, Tf = 5220MHz (34) */
 308         0x05555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  46, Tf = 5230MHz (35) */
 309         0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  48, Tf = 5240MHz (36) */
 310         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  52, Tf = 5260MHz (37) */
 311         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  56, Tf = 5280MHz (38) */
 312         0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  60, Tf = 5300MHz (39) */
 313         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  64, Tf = 5320MHz (40) */
 314         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */
 315         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */
 316         0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */
 317         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */
 318         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */
 319         0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */
 320         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */
 321         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */
 322         0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */
 323         0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */
 324         0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */
 325         0x18000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */
 326         0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */
 327         0x0D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */
 328         0x18000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */
 329         0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW  /* channel = 165, Tf = 5825MHz (56) */
 330 };
 331 
 332 static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = {
 333         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  1, Tf = 2412MHz */
 334         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  2, Tf = 2417MHz */
 335         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  3, Tf = 2422MHz */
 336         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  4, Tf = 2427MHz */
 337         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  5, Tf = 2432MHz */
 338         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  6, Tf = 2437MHz */
 339         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  7, Tf = 2442MHz */
 340         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  8, Tf = 2447MHz */
 341         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  9, Tf = 2452MHz */
 342         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
 343         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
 344         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
 345         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
 346         0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */
 347 
 348         /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22) */
 349         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */
 350         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */
 351         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */
 352         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */
 353         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */
 354         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */
 355         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */
 356         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */
 357 
 358         /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
 359          * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
 360          */
 361         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   7, Tf = 5035MHz (23) */
 362         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   8, Tf = 5040MHz (24) */
 363         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =   9, Tf = 5045MHz (25) */
 364         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  11, Tf = 5055MHz (26) */
 365         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  12, Tf = 5060MHz (27) */
 366         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  16, Tf = 5080MHz (28) */
 367         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  34, Tf = 5170MHz (29) */
 368         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  36, Tf = 5180MHz (30) */
 369         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  38, Tf = 5190MHz (31) */
 370         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  40, Tf = 5200MHz (32) */
 371         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  42, Tf = 5210MHz (33) */
 372         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  44, Tf = 5220MHz (34) */
 373         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  46, Tf = 5230MHz (35) */
 374         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  48, Tf = 5240MHz (36) */
 375         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  52, Tf = 5260MHz (37) */
 376         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  56, Tf = 5280MHz (38) */
 377         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  60, Tf = 5300MHz (39) */
 378         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel =  64, Tf = 5320MHz (40) */
 379         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */
 380         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */
 381         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */
 382         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */
 383         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */
 384         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */
 385         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */
 386         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */
 387         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */
 388         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */
 389         0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */
 390         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */
 391         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */
 392         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */
 393         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */
 394         0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW  /* channel = 165, Tf = 5825MHz (56) */
 395 };
 396 
 397 /*
 398  * Description: AIROHA IFRF chip init function
 399  *
 400  * Parameters:
 401  *  In:
 402  *      iobase      - I/O base address
 403  *  Out:
 404  *      none
 405  *
 406  * Return Value: true if succeeded; false if failed.
 407  *
 408  */
 409 static bool s_bAL7230Init(struct vnt_private *priv)
 410 {
 411         void __iomem *iobase = priv->PortOffset;
 412         int     ii;
 413         bool ret;
 414 
 415         ret = true;
 416 
 417         /* 3-wire control for normal mode */
 418         VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0);
 419 
 420         MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI  |
 421                                                          SOFTPWRCTL_TXPEINV));
 422         BBvPowerSaveModeOFF(priv); /* RobertYu:20050106, have DC value for Calibration */
 423 
 424         for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
 425                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[ii]);
 426 
 427         /* PLL On */
 428         MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 429 
 430         /* Calibration */
 431         MACvTimer0MicroSDelay(priv, 150);/* 150us */
 432         /* TXDCOC:active, RCK:disable */
 433         ret &= IFRFbWriteEmbedded(priv, (0x9ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW));
 434         MACvTimer0MicroSDelay(priv, 30);/* 30us */
 435         /* TXDCOC:disable, RCK:active */
 436         ret &= IFRFbWriteEmbedded(priv, (0x3ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW));
 437         MACvTimer0MicroSDelay(priv, 30);/* 30us */
 438         /* TXDCOC:disable, RCK:disable */
 439         ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]);
 440 
 441         MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |
 442                                                          SOFTPWRCTL_SWPE2    |
 443                                                          SOFTPWRCTL_SWPECTI  |
 444                                                          SOFTPWRCTL_TXPEINV));
 445 
 446         BBvPowerSaveModeON(priv); /* RobertYu:20050106 */
 447 
 448         /* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */
 449         /* 3-wire control for power saving mode */
 450         VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */
 451 
 452         return ret;
 453 }
 454 
 455 /* Need to Pull PLLON low when writing channel registers through
 456  * 3-wire interface
 457  */
 458 static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byChannel)
 459 {
 460         void __iomem *iobase = priv->PortOffset;
 461         bool ret;
 462 
 463         ret = true;
 464 
 465         /* PLLON Off */
 466         MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 467 
 468         ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable0[byChannel - 1]);
 469         ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable1[byChannel - 1]);
 470         ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable2[byChannel - 1]);
 471 
 472         /* PLLOn On */
 473         MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 474 
 475         /* Set Channel[7] = 0 to tell H/W channel is changing now. */
 476         VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F));
 477         MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL7230);
 478         /* Set Channel[7] = 1 to tell H/W channel change is done. */
 479         VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80));
 480 
 481         return ret;
 482 }
 483 
 484 /*
 485  * Description: Write to IF/RF, by embedded programming
 486  *
 487  * Parameters:
 488  *  In:
 489  *      iobase      - I/O base address
 490  *      dwData      - data to write
 491  *  Out:
 492  *      none
 493  *
 494  * Return Value: true if succeeded; false if failed.
 495  *
 496  */
 497 bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData)
 498 {
 499         void __iomem *iobase = priv->PortOffset;
 500         unsigned short ww;
 501         unsigned long dwValue;
 502 
 503         VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData);
 504 
 505         /* W_MAX_TIMEOUT is the timeout period */
 506         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 507                 VNSvInPortD(iobase + MAC_REG_IFREGCTL, &dwValue);
 508                 if (dwValue & IFREGCTL_DONE)
 509                         break;
 510         }
 511 
 512         if (ww == W_MAX_TIMEOUT)
 513                 return false;
 514 
 515         return true;
 516 }
 517 
 518 /*
 519  * Description: AIROHA IFRF chip init function
 520  *
 521  * Parameters:
 522  *  In:
 523  *      iobase      - I/O base address
 524  *  Out:
 525  *      none
 526  *
 527  * Return Value: true if succeeded; false if failed.
 528  *
 529  */
 530 static bool RFbAL2230Init(struct vnt_private *priv)
 531 {
 532         void __iomem *iobase = priv->PortOffset;
 533         int     ii;
 534         bool ret;
 535 
 536         ret = true;
 537 
 538         /* 3-wire control for normal mode */
 539         VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0);
 540 
 541         MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI  |
 542                                                          SOFTPWRCTL_TXPEINV));
 543         /* PLL  Off */
 544         MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 545 
 546         /* patch abnormal AL2230 frequency output */
 547         IFRFbWriteEmbedded(priv, (0x07168700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
 548 
 549         for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
 550                 ret &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[ii]);
 551         MACvTimer0MicroSDelay(priv, 30); /* delay 30 us */
 552 
 553         /* PLL On */
 554         MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
 555 
 556         MACvTimer0MicroSDelay(priv, 150);/* 150us */
 557         ret &= IFRFbWriteEmbedded(priv, (0x00d80f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
 558         MACvTimer0MicroSDelay(priv, 30);/* 30us */
 559         ret &= IFRFbWriteEmbedded(priv, (0x00780f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
 560         MACvTimer0MicroSDelay(priv, 30);/* 30us */
 561         ret &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]);
 562 
 563         MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |
 564                                                          SOFTPWRCTL_SWPE2    |
 565                                                          SOFTPWRCTL_SWPECTI  |
 566                                                          SOFTPWRCTL_TXPEINV));
 567 
 568         /* 3-wire control for power saving mode */
 569         VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */
 570 
 571         return ret;
 572 }
 573 
 574 static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel)
 575 {
 576         void __iomem *iobase = priv->PortOffset;
 577         bool ret;
 578 
 579         ret = true;
 580 
 581         ret &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable0[byChannel - 1]);
 582         ret &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable1[byChannel - 1]);
 583 
 584         /* Set Channel[7] = 0 to tell H/W channel is changing now. */
 585         VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F));
 586         MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL2230);
 587         /* Set Channel[7] = 1 to tell H/W channel change is done. */
 588         VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80));
 589 
 590         return ret;
 591 }
 592 
 593 /*
 594  * Description: RF init function
 595  *
 596  * Parameters:
 597  *  In:
 598  *      byBBType
 599  *      byRFType
 600  *  Out:
 601  *      none
 602  *
 603  * Return Value: true if succeeded; false if failed.
 604  *
 605  */
 606 bool RFbInit(struct vnt_private *priv)
 607 {
 608         bool ret = true;
 609 
 610         switch (priv->byRFType) {
 611         case RF_AIROHA:
 612         case RF_AL2230S:
 613                 priv->byMaxPwrLevel = AL2230_PWR_IDX_LEN;
 614                 ret = RFbAL2230Init(priv);
 615                 break;
 616         case RF_AIROHA7230:
 617                 priv->byMaxPwrLevel = AL7230_PWR_IDX_LEN;
 618                 ret = s_bAL7230Init(priv);
 619                 break;
 620         case RF_NOTHING:
 621                 ret = true;
 622                 break;
 623         default:
 624                 ret = false;
 625                 break;
 626         }
 627         return ret;
 628 }
 629 
 630 /*
 631  * Description: Select channel
 632  *
 633  * Parameters:
 634  *  In:
 635  *      byRFType
 636  *      byChannel    - Channel number
 637  *  Out:
 638  *      none
 639  *
 640  * Return Value: true if succeeded; false if failed.
 641  *
 642  */
 643 bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType,
 644                       u16 byChannel)
 645 {
 646         bool ret = true;
 647 
 648         switch (byRFType) {
 649         case RF_AIROHA:
 650         case RF_AL2230S:
 651                 ret = RFbAL2230SelectChannel(priv, byChannel);
 652                 break;
 653                 /*{{ RobertYu: 20050104 */
 654         case RF_AIROHA7230:
 655                 ret = s_bAL7230SelectChannel(priv, byChannel);
 656                 break;
 657                 /*}} RobertYu */
 658         case RF_NOTHING:
 659                 ret = true;
 660                 break;
 661         default:
 662                 ret = false;
 663                 break;
 664         }
 665         return ret;
 666 }
 667 
 668 /*
 669  * Description: Write WakeProgSyn
 670  *
 671  * Parameters:
 672  *  In:
 673  *      iobase      - I/O base address
 674  *      uChannel    - channel number
 675  *      bySleepCnt  - SleepProgSyn count
 676  *
 677  * Return Value: None.
 678  *
 679  */
 680 bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType,
 681                          u16 uChannel)
 682 {
 683         void __iomem *iobase = priv->PortOffset;
 684         int   ii;
 685         unsigned char byInitCount = 0;
 686         unsigned char bySleepCount = 0;
 687 
 688         VNSvOutPortW(iobase + MAC_REG_MISCFFNDEX, 0);
 689         switch (byRFType) {
 690         case RF_AIROHA:
 691         case RF_AL2230S:
 692 
 693                 if (uChannel > CB_MAX_CHANNEL_24G)
 694                         return false;
 695 
 696                  /* Init Reg + Channel Reg (2) */
 697                 byInitCount = CB_AL2230_INIT_SEQ + 2;
 698                 bySleepCount = 0;
 699                 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount))
 700                         return false;
 701 
 702                 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
 703                         MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
 704 
 705                 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel - 1]);
 706                 ii++;
 707                 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel - 1]);
 708                 break;
 709 
 710                 /* Need to check, PLLON need to be low for channel setting */
 711         case RF_AIROHA7230:
 712                  /* Init Reg + Channel Reg (3) */
 713                 byInitCount = CB_AL7230_INIT_SEQ + 3;
 714                 bySleepCount = 0;
 715                 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount))
 716                         return false;
 717 
 718                 if (uChannel <= CB_MAX_CHANNEL_24G) {
 719                         for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
 720                                 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]);
 721                 } else {
 722                         for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
 723                                 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
 724                 }
 725 
 726                 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel - 1]);
 727                 ii++;
 728                 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel - 1]);
 729                 ii++;
 730                 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel - 1]);
 731                 break;
 732 
 733         case RF_NOTHING:
 734                 return true;
 735 
 736         default:
 737                 return false;
 738         }
 739 
 740         MACvSetMISCFifo(priv, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(bySleepCount, byInitCount));
 741 
 742         return true;
 743 }
 744 
 745 /*
 746  * Description: Set Tx power
 747  *
 748  * Parameters:
 749  *  In:
 750  *      iobase         - I/O base address
 751  *      dwRFPowerTable - RF Tx Power Setting
 752  *  Out:
 753  *      none
 754  *
 755  * Return Value: true if succeeded; false if failed.
 756  *
 757  */
 758 bool RFbSetPower(struct vnt_private *priv, unsigned int rate, u16 uCH)
 759 {
 760         bool ret = true;
 761         unsigned char byPwr = 0;
 762         unsigned char byDec = 0;
 763 
 764         if (priv->dwDiagRefCount != 0)
 765                 return true;
 766 
 767         if ((uCH < 1) || (uCH > CB_MAX_CHANNEL))
 768                 return false;
 769 
 770         switch (rate) {
 771         case RATE_1M:
 772         case RATE_2M:
 773         case RATE_5M:
 774         case RATE_11M:
 775                 if (uCH > CB_MAX_CHANNEL_24G)
 776                         return false;
 777 
 778                 byPwr = priv->abyCCKPwrTbl[uCH];
 779                 break;
 780         case RATE_6M:
 781         case RATE_9M:
 782         case RATE_12M:
 783         case RATE_18M:
 784                 byPwr = priv->abyOFDMPwrTbl[uCH];
 785                 if (priv->byRFType == RF_UW2452)
 786                         byDec = byPwr + 14;
 787                 else
 788                         byDec = byPwr + 10;
 789 
 790                 if (byDec >= priv->byMaxPwrLevel)
 791                         byDec = priv->byMaxPwrLevel - 1;
 792 
 793                 byPwr = byDec;
 794                 break;
 795         case RATE_24M:
 796         case RATE_36M:
 797         case RATE_48M:
 798         case RATE_54M:
 799                 byPwr = priv->abyOFDMPwrTbl[uCH];
 800                 break;
 801         }
 802 
 803         if (priv->byCurPwr == byPwr)
 804                 return true;
 805 
 806         ret = RFbRawSetPower(priv, byPwr, rate);
 807         if (ret)
 808                 priv->byCurPwr = byPwr;
 809 
 810         return ret;
 811 }
 812 
 813 /*
 814  * Description: Set Tx power
 815  *
 816  * Parameters:
 817  *  In:
 818  *      iobase         - I/O base address
 819  *      dwRFPowerTable - RF Tx Power Setting
 820  *  Out:
 821  *      none
 822  *
 823  * Return Value: true if succeeded; false if failed.
 824  *
 825  */
 826 
 827 bool RFbRawSetPower(struct vnt_private *priv, unsigned char byPwr,
 828                     unsigned int rate)
 829 {
 830         bool ret = true;
 831         unsigned long dwMax7230Pwr = 0;
 832 
 833         if (byPwr >=  priv->byMaxPwrLevel)
 834                 return false;
 835 
 836         switch (priv->byRFType) {
 837         case RF_AIROHA:
 838                 ret &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]);
 839                 if (rate <= RATE_11M)
 840                         ret &= IFRFbWriteEmbedded(priv, 0x0001B400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 841                 else
 842                         ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 843 
 844                 break;
 845 
 846         case RF_AL2230S:
 847                 ret &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]);
 848                 if (rate <= RATE_11M) {
 849                         ret &= IFRFbWriteEmbedded(priv, 0x040C1400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 850                         ret &= IFRFbWriteEmbedded(priv, 0x00299B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 851                 } else {
 852                         ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 853                         ret &= IFRFbWriteEmbedded(priv, 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
 854                 }
 855 
 856                 break;
 857 
 858         case RF_AIROHA7230:
 859                 /* 0x080F1B00 for 3 wire control TxGain(D10)
 860                  * and 0x31 as TX Gain value
 861                  */
 862                 dwMax7230Pwr = 0x080C0B00 | ((byPwr) << 12) |
 863                         (BY_AL7230_REG_LEN << 3)  | IFREGCTL_REGW;
 864 
 865                 ret &= IFRFbWriteEmbedded(priv, dwMax7230Pwr);
 866                 break;
 867 
 868         default:
 869                 break;
 870         }
 871         return ret;
 872 }
 873 
 874 /*
 875  *
 876  * Routine Description:
 877  *     Translate RSSI to dBm
 878  *
 879  * Parameters:
 880  *  In:
 881  *      priv         - The adapter to be translated
 882  *      byCurrRSSI      - RSSI to be translated
 883  *  Out:
 884  *      pdwdbm          - Translated dbm number
 885  *
 886  * Return Value: none
 887  *
 888  */
 889 void
 890 RFvRSSITodBm(struct vnt_private *priv, unsigned char byCurrRSSI, long *pldBm)
 891 {
 892         unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
 893         long b = (byCurrRSSI & 0x3F);
 894         long a = 0;
 895         unsigned char abyAIROHARF[4] = {0, 18, 0, 40};
 896 
 897         switch (priv->byRFType) {
 898         case RF_AIROHA:
 899         case RF_AL2230S:
 900         case RF_AIROHA7230:
 901                 a = abyAIROHARF[byIdx];
 902                 break;
 903         default:
 904                 break;
 905         }
 906 
 907         *pldBm = -1 * (a + b * 2);
 908 }
 909 
 910 /* Post processing for the 11b/g and 11a.
 911  * for save time on changing Reg2,3,5,7,10,12,15
 912  */
 913 bool RFbAL7230SelectChannelPostProcess(struct vnt_private *priv,
 914                                        u16 byOldChannel,
 915                                        u16 byNewChannel)
 916 {
 917         bool ret;
 918 
 919         ret = true;
 920 
 921         /* if change between 11 b/g and 11a need to update the following
 922          * register
 923          * Channel Index 1~14
 924          */
 925         if ((byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G)) {
 926                 /* Change from 2.4G to 5G [Reg] */
 927                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[2]);
 928                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[3]);
 929                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[5]);
 930                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[7]);
 931                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[10]);
 932                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[12]);
 933                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[15]);
 934         } else if ((byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G)) {
 935                 /* Change from 5G to 2.4G [Reg] */
 936                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[2]);
 937                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[3]);
 938                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[5]);
 939                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[7]);
 940                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[10]);
 941                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[12]);
 942                 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[15]);
 943         }
 944 
 945         return ret;
 946 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/staging/vt6655/rf.c

DEFINITIONS
