This source file includes following definitions.
- mipi_csis_dump_regs
- mipi_sd_to_csis_state
- find_csis_format
- mipi_csis_enable_interrupts
- mipi_csis_sw_reset
- mipi_csis_phy_init
- mipi_csis_phy_reset
- mipi_csis_system_enable
- __mipi_csis_set_format
- mipi_csis_set_hsync_settle
- mipi_csis_set_params
- mipi_csis_clk_enable
- mipi_csis_clk_disable
- mipi_csis_clk_get
- mipi_csis_start_stream
- mipi_csis_stop_stream
- mipi_csis_clear_counters
- mipi_csis_log_counters
- mipi_csis_s_stream
- mipi_csis_link_setup
- mipi_csis_init_cfg
- mipi_csis_try_format
- mipi_csis_get_format
- mipi_csis_set_fmt
- mipi_csis_get_fmt
- mipi_csis_log_status
- mipi_csis_irq_handler
- mipi_csis_registered
- mipi_csis_parse_dt
- mipi_csis_parse_endpoint
- mipi_csis_subdev_init
- mipi_csis_dump_regs_show
- mipi_csis_debugfs_init
- mipi_csis_debugfs_exit
- mipi_csis_probe
- mipi_csis_pm_suspend
- mipi_csis_pm_resume
- mipi_csis_suspend
- mipi_csis_resume
- mipi_csis_runtime_suspend
- mipi_csis_runtime_resume
- mipi_csis_remove
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11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_graph.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/reset.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-subdev.h>
31
32 #include "imx-media.h"
33
34 #define CSIS_DRIVER_NAME "imx7-mipi-csis"
35 #define CSIS_SUBDEV_NAME CSIS_DRIVER_NAME
36
37 #define CSIS_PAD_SINK 0
38 #define CSIS_PAD_SOURCE 1
39 #define CSIS_PADS_NUM 2
40
41 #define MIPI_CSIS_DEF_PIX_WIDTH 640
42 #define MIPI_CSIS_DEF_PIX_HEIGHT 480
43
44
45
46
47 #define MIPI_CSIS_CMN_CTRL 0x04
48 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16)
49 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10)
50 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2)
51 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1)
52 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0)
53
54 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8
55 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8)
56
57
58 #define MIPI_CSIS_CLK_CTRL 0x08
59 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
60 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
61 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
62 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
63 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4)
64 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0)
65
66
67 #define MIPI_CSIS_INTMSK 0x10
68 #define MIPI_CSIS_INTMSK_EVEN_BEFORE BIT(31)
69 #define MIPI_CSIS_INTMSK_EVEN_AFTER BIT(30)
70 #define MIPI_CSIS_INTMSK_ODD_BEFORE BIT(29)
71 #define MIPI_CSIS_INTMSK_ODD_AFTER BIT(28)
72 #define MIPI_CSIS_INTMSK_FRAME_START BIT(24)
73 #define MIPI_CSIS_INTMSK_FRAME_END BIT(20)
74 #define MIPI_CSIS_INTMSK_ERR_SOT_HS BIT(16)
75 #define MIPI_CSIS_INTMSK_ERR_LOST_FS BIT(12)
76 #define MIPI_CSIS_INTMSK_ERR_LOST_FE BIT(8)
77 #define MIPI_CSIS_INTMSK_ERR_OVER BIT(4)
78 #define MIPI_CSIS_INTMSK_ERR_WRONG_CFG BIT(3)
79 #define MIPI_CSIS_INTMSK_ERR_ECC BIT(2)
80 #define MIPI_CSIS_INTMSK_ERR_CRC BIT(1)
81 #define MIPI_CSIS_INTMSK_ERR_UNKNOWN BIT(0)
82
83
84 #define MIPI_CSIS_INTSRC 0x14
85 #define MIPI_CSIS_INTSRC_EVEN_BEFORE BIT(31)
86 #define MIPI_CSIS_INTSRC_EVEN_AFTER BIT(30)
87 #define MIPI_CSIS_INTSRC_EVEN BIT(30)
88 #define MIPI_CSIS_INTSRC_ODD_BEFORE BIT(29)
89 #define MIPI_CSIS_INTSRC_ODD_AFTER BIT(28)
90 #define MIPI_CSIS_INTSRC_ODD (0x3 << 28)
91 #define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28)
92 #define MIPI_CSIS_INTSRC_FRAME_START BIT(24)
93 #define MIPI_CSIS_INTSRC_FRAME_END BIT(20)
94 #define MIPI_CSIS_INTSRC_ERR_SOT_HS BIT(16)
95 #define MIPI_CSIS_INTSRC_ERR_LOST_FS BIT(12)
96 #define MIPI_CSIS_INTSRC_ERR_LOST_FE BIT(8)
97 #define MIPI_CSIS_INTSRC_ERR_OVER BIT(4)
98 #define MIPI_CSIS_INTSRC_ERR_WRONG_CFG BIT(3)
99 #define MIPI_CSIS_INTSRC_ERR_ECC BIT(2)
100 #define MIPI_CSIS_INTSRC_ERR_CRC BIT(1)
101 #define MIPI_CSIS_INTSRC_ERR_UNKNOWN BIT(0)
102 #define MIPI_CSIS_INTSRC_ERRORS 0xfffff
103
104
105 #define MIPI_CSIS_DPHYSTATUS 0x20
106 #define MIPI_CSIS_DPHYSTATUS_ULPS_DAT BIT(8)
107 #define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT BIT(4)
108 #define MIPI_CSIS_DPHYSTATUS_ULPS_CLK BIT(1)
109 #define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK BIT(0)
110
111
112 #define MIPI_CSIS_DPHYCTRL 0x24
113 #define MIPI_CSIS_DPHYCTRL_HSS_MASK (0xff << 24)
114 #define MIPI_CSIS_DPHYCTRL_HSS_OFFSET 24
115 #define MIPI_CSIS_DPHYCTRL_SCLKS_MASK (0x3 << 22)
116 #define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET 22
117 #define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK BIT(6)
118 #define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT BIT(5)
119 #define MIPI_CSIS_DPHYCTRL_ENABLE_DAT BIT(1)
120 #define MIPI_CSIS_DPHYCTRL_ENABLE_CLK BIT(0)
121 #define MIPI_CSIS_DPHYCTRL_ENABLE (0x1f << 0)
122
123
124 #define MIPI_CSIS_DPHYBCTRL_L 0x30
125
126 #define MIPI_CSIS_DPHYBCTRL_H 0x34
127
128 #define MIPI_CSIS_DPHYSCTRL_L 0x38
129
130 #define MIPI_CSIS_DPHYSCTRL_H 0x3c
131
132
133 #define MIPI_CSIS_ISPCONFIG_CH0 0x40
134 #define MIPI_CSIS_ISPCONFIG_CH1 0x50
135 #define MIPI_CSIS_ISPCONFIG_CH2 0x60
136 #define MIPI_CSIS_ISPCONFIG_CH3 0x70
137
138 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24)
139 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24)
140 #define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT BIT(12)
141 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
142 #define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT (0x1e << 2)
143 #define MIPI_CSIS_ISPCFG_FMT_RAW8 (0x2a << 2)
144 #define MIPI_CSIS_ISPCFG_FMT_RAW10 (0x2b << 2)
145 #define MIPI_CSIS_ISPCFG_FMT_RAW12 (0x2c << 2)
146
147
148 #define MIPI_CSIS_ISPCFG_FMT_USER(x) ((0x30 + (x) - 1) << 2)
149 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
150
151
152 #define MIPI_CSIS_ISPRESOL_CH0 0x44
153 #define MIPI_CSIS_ISPRESOL_CH1 0x54
154 #define MIPI_CSIS_ISPRESOL_CH2 0x64
155 #define MIPI_CSIS_ISPRESOL_CH3 0x74
156 #define CSIS_MAX_PIX_WIDTH 0xffff
157 #define CSIS_MAX_PIX_HEIGHT 0xffff
158
159
160 #define MIPI_CSIS_ISPSYNC_CH0 0x48
161 #define MIPI_CSIS_ISPSYNC_CH1 0x58
162 #define MIPI_CSIS_ISPSYNC_CH2 0x68
163 #define MIPI_CSIS_ISPSYNC_CH3 0x78
164
165 #define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET 18
166 #define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET 12
167 #define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET 0
168
169
170 #define MIPI_CSIS_PKTDATA_ODD 0x2000
171 #define MIPI_CSIS_PKTDATA_EVEN 0x3000
172 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K
173
174 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL
175
176 enum {
177 ST_POWERED = 1,
178 ST_STREAMING = 2,
179 ST_SUSPENDED = 4,
180 };
181
182 struct mipi_csis_event {
183 u32 mask;
184 const char * const name;
185 unsigned int counter;
186 };
187
188 static const struct mipi_csis_event mipi_csis_events[] = {
189
190 { MIPI_CSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
191 { MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
192 { MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
193 { MIPI_CSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
194 { MIPI_CSIS_INTSRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
195 { MIPI_CSIS_INTSRC_ERR_ECC, "ECC Error" },
196 { MIPI_CSIS_INTSRC_ERR_CRC, "CRC Error" },
197 { MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
198
199 { MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
200 { MIPI_CSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
201 { MIPI_CSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
202 { MIPI_CSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
203
204 { MIPI_CSIS_INTSRC_FRAME_START, "Frame Start" },
205 { MIPI_CSIS_INTSRC_FRAME_END, "Frame End" },
206 };
207
208 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
209
210 static const char * const mipi_csis_clk_id[] = {"pclk", "wrap", "phy"};
211
212 struct csis_hw_reset {
213 struct regmap *src;
214 u8 req_src;
215 u8 rst_bit;
216 };
217
218 struct csi_state {
219
220 struct mutex lock;
221
222 spinlock_t slock;
223 struct device *dev;
224 struct media_pad pads[CSIS_PADS_NUM];
225 struct v4l2_subdev mipi_sd;
226 struct v4l2_subdev *src_sd;
227
228 u8 index;
229 struct platform_device *pdev;
230 struct phy *phy;
231 void __iomem *regs;
232 struct clk *wrap_clk;
233 int irq;
234 u32 flags;
235
236 struct dentry *debugfs_root;
237 bool debug;
238
239 int num_clks;
240 struct clk_bulk_data *clks;
241
242 u32 clk_frequency;
243 u32 hs_settle;
244
245 struct reset_control *mrst;
246
247 const struct csis_pix_format *csis_fmt;
248 struct v4l2_mbus_framefmt format_mbus;
249
250 struct v4l2_fwnode_bus_mipi_csi2 bus;
251
252 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
253
254 struct v4l2_async_notifier subdev_notifier;
255
256 struct csis_hw_reset hw_reset;
257 struct regulator *mipi_phy_regulator;
258 bool sink_linked;
259 };
260
261 struct csis_pix_format {
262 unsigned int pix_width_alignment;
263 u32 code;
264 u32 fmt_reg;
265 u8 data_alignment;
266 };
267
268 static const struct csis_pix_format mipi_csis_formats[] = {
269 {
270 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
271 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
272 .data_alignment = 16,
273 }, {
274 .code = MEDIA_BUS_FMT_VYUY8_2X8,
275 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
276 .data_alignment = 16,
277 }, {
278 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
279 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
280 .data_alignment = 8,
281 }, {
282 .code = MEDIA_BUS_FMT_YUYV8_2X8,
283 .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
284 .data_alignment = 16,
285 }
286 };
287
288 #define mipi_csis_write(__csis, __r, __v) writel(__v, (__csis)->regs + (__r))
289 #define mipi_csis_read(__csis, __r) readl((__csis)->regs + (__r))
290
291 static int mipi_csis_dump_regs(struct csi_state *state)
292 {
293 struct device *dev = &state->pdev->dev;
294 unsigned int i;
295 u32 cfg;
296 struct {
297 u32 offset;
298 const char * const name;
299 } registers[] = {
300 { 0x04, "CTRL" },
301 { 0x24, "DPHYCTRL" },
302 { 0x08, "CLKCTRL" },
303 { 0x20, "DPHYSTS" },
304 { 0x10, "INTMSK" },
305 { 0x40, "CONFIG_CH0" },
306 { 0xC0, "DBG_CONFIG" },
307 { 0x38, "DPHYSLAVE_L" },
308 { 0x3C, "DPHYSLAVE_H" },
309 };
310
311 dev_info(dev, "--- REGISTERS ---\n");
312
313 for (i = 0; i < ARRAY_SIZE(registers); i++) {
314 cfg = mipi_csis_read(state, registers[i].offset);
315 dev_info(dev, "%12s: 0x%08x\n", registers[i].name, cfg);
316 }
317
318 return 0;
319 }
320
321 static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev)
322 {
323 return container_of(sdev, struct csi_state, mipi_sd);
324 }
325
326 static const struct csis_pix_format *find_csis_format(u32 code)
327 {
328 unsigned int i;
329
330 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
331 if (code == mipi_csis_formats[i].code)
332 return &mipi_csis_formats[i];
333 return NULL;
334 }
335
336 static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
337 {
338 mipi_csis_write(state, MIPI_CSIS_INTMSK, on ? 0xffffffff : 0);
339 }
340
341 static void mipi_csis_sw_reset(struct csi_state *state)
342 {
343 u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
344
345 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
346 val | MIPI_CSIS_CMN_CTRL_RESET);
347 usleep_range(10, 20);
348 }
349
350 static int mipi_csis_phy_init(struct csi_state *state)
351 {
352 state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy");
353 if (IS_ERR(state->mipi_phy_regulator))
354 return PTR_ERR(state->mipi_phy_regulator);
355
356 return regulator_set_voltage(state->mipi_phy_regulator, 1000000,
357 1000000);
358 }
359
360 static void mipi_csis_phy_reset(struct csi_state *state)
361 {
362 reset_control_assert(state->mrst);
363
364 msleep(20);
365
366 reset_control_deassert(state->mrst);
367 }
368
369 static void mipi_csis_system_enable(struct csi_state *state, int on)
370 {
371 u32 val, mask;
372
373 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
374 if (on)
375 val |= MIPI_CSIS_CMN_CTRL_ENABLE;
376 else
377 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
378 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
379
380 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
381 val &= ~MIPI_CSIS_DPHYCTRL_ENABLE;
382 if (on) {
383 mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
384 val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE);
385 }
386 mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
387 }
388
389
390 static void __mipi_csis_set_format(struct csi_state *state)
391 {
392 struct v4l2_mbus_framefmt *mf = &state->format_mbus;
393 u32 val;
394
395
396 val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
397 val = (val & ~MIPI_CSIS_ISPCFG_FMT_MASK) | state->csis_fmt->fmt_reg;
398 mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
399
400
401 val = mf->width | (mf->height << 16);
402 mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val);
403 }
404
405 static void mipi_csis_set_hsync_settle(struct csi_state *state, int hs_settle)
406 {
407 u32 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
408
409 val = ((val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | (hs_settle << 24));
410
411 mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
412 }
413
414 static void mipi_csis_set_params(struct csi_state *state)
415 {
416 int lanes = state->bus.num_data_lanes;
417 u32 val;
418
419 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
420 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
421 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
422 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
423
424 __mipi_csis_set_format(state);
425
426 mipi_csis_set_hsync_settle(state, state->hs_settle);
427
428 val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
429 if (state->csis_fmt->data_alignment == 32)
430 val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT;
431 else
432 val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT;
433 mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
434
435 val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
436 (0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
437 (0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);
438 mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH0, val);
439
440 val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
441 val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
442 if (state->wrap_clk)
443 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
444 else
445 val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
446
447 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
448 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
449 mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val);
450
451 mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_L, 0x1f4);
452 mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_H, 0);
453
454
455 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
456 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
457 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
458 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
459 }
460
461 static int mipi_csis_clk_enable(struct csi_state *state)
462 {
463 return clk_bulk_prepare_enable(state->num_clks, state->clks);
464 }
465
466 static void mipi_csis_clk_disable(struct csi_state *state)
467 {
468 clk_bulk_disable_unprepare(state->num_clks, state->clks);
469 }
470
471 static int mipi_csis_clk_get(struct csi_state *state)
472 {
473 struct device *dev = &state->pdev->dev;
474 unsigned int i;
475 int ret;
476
477 state->num_clks = ARRAY_SIZE(mipi_csis_clk_id);
478 state->clks = devm_kcalloc(dev, state->num_clks, sizeof(*state->clks),
479 GFP_KERNEL);
480
481 if (!state->clks)
482 return -ENOMEM;
483
484 for (i = 0; i < state->num_clks; i++)
485 state->clks[i].id = mipi_csis_clk_id[i];
486
487 ret = devm_clk_bulk_get(dev, state->num_clks, state->clks);
488 if (ret < 0)
489 return ret;
490
491 state->wrap_clk = devm_clk_get(dev, "wrap");
492 if (IS_ERR(state->wrap_clk))
493 return PTR_ERR(state->wrap_clk);
494
495
496 ret = clk_set_rate(state->wrap_clk, state->clk_frequency);
497 if (ret < 0)
498 dev_err(dev, "set rate=%d failed: %d\n", state->clk_frequency,
499 ret);
500
501 return ret;
502 }
503
504 static void mipi_csis_start_stream(struct csi_state *state)
505 {
506 mipi_csis_sw_reset(state);
507 mipi_csis_set_params(state);
508 mipi_csis_system_enable(state, true);
509 mipi_csis_enable_interrupts(state, true);
510 }
511
512 static void mipi_csis_stop_stream(struct csi_state *state)
513 {
514 mipi_csis_enable_interrupts(state, false);
515 mipi_csis_system_enable(state, false);
516 }
517
518 static void mipi_csis_clear_counters(struct csi_state *state)
519 {
520 unsigned long flags;
521 unsigned int i;
522
523 spin_lock_irqsave(&state->slock, flags);
524 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
525 state->events[i].counter = 0;
526 spin_unlock_irqrestore(&state->slock, flags);
527 }
528
529 static void mipi_csis_log_counters(struct csi_state *state, bool non_errors)
530 {
531 int i = non_errors ? MIPI_CSIS_NUM_EVENTS : MIPI_CSIS_NUM_EVENTS - 4;
532 struct device *dev = &state->pdev->dev;
533 unsigned long flags;
534
535 spin_lock_irqsave(&state->slock, flags);
536
537 for (i--; i >= 0; i--) {
538 if (state->events[i].counter > 0 || state->debug)
539 dev_info(dev, "%s events: %d\n", state->events[i].name,
540 state->events[i].counter);
541 }
542 spin_unlock_irqrestore(&state->slock, flags);
543 }
544
545
546
547
548 static int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable)
549 {
550 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
551 int ret = 0;
552
553 if (enable) {
554 mipi_csis_clear_counters(state);
555 ret = pm_runtime_get_sync(&state->pdev->dev);
556 if (ret < 0) {
557 pm_runtime_put_noidle(&state->pdev->dev);
558 return ret;
559 }
560 ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
561 if (ret < 0)
562 return ret;
563 }
564
565 mutex_lock(&state->lock);
566 if (enable) {
567 if (state->flags & ST_SUSPENDED) {
568 ret = -EBUSY;
569 goto unlock;
570 }
571
572 mipi_csis_start_stream(state);
573 ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
574 if (ret < 0)
575 goto unlock;
576
577 mipi_csis_log_counters(state, true);
578
579 state->flags |= ST_STREAMING;
580 } else {
581 v4l2_subdev_call(state->src_sd, video, s_stream, 0);
582 ret = v4l2_subdev_call(state->src_sd, core, s_power, 0);
583 mipi_csis_stop_stream(state);
584 state->flags &= ~ST_STREAMING;
585 if (state->debug)
586 mipi_csis_log_counters(state, true);
587 }
588
589 unlock:
590 mutex_unlock(&state->lock);
591 if (!enable)
592 pm_runtime_put(&state->pdev->dev);
593
594 return ret;
595 }
596
597 static int mipi_csis_link_setup(struct media_entity *entity,
598 const struct media_pad *local_pad,
599 const struct media_pad *remote_pad, u32 flags)
600 {
601 struct v4l2_subdev *mipi_sd = media_entity_to_v4l2_subdev(entity);
602 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
603 struct v4l2_subdev *remote_sd;
604 int ret = 0;
605
606 dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name,
607 local_pad->entity->name);
608
609 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
610
611 mutex_lock(&state->lock);
612
613 if (local_pad->flags & MEDIA_PAD_FL_SOURCE) {
614 if (flags & MEDIA_LNK_FL_ENABLED) {
615 if (state->sink_linked) {
616 ret = -EBUSY;
617 goto out;
618 }
619 state->sink_linked = true;
620 } else {
621 state->sink_linked = false;
622 }
623 } else {
624 if (flags & MEDIA_LNK_FL_ENABLED) {
625 if (state->src_sd) {
626 ret = -EBUSY;
627 goto out;
628 }
629 state->src_sd = remote_sd;
630 } else {
631 state->src_sd = NULL;
632 }
633 }
634
635 out:
636 mutex_unlock(&state->lock);
637 return ret;
638 }
639
640 static int mipi_csis_init_cfg(struct v4l2_subdev *mipi_sd,
641 struct v4l2_subdev_pad_config *cfg)
642 {
643 struct v4l2_mbus_framefmt *mf;
644 unsigned int i;
645 int ret;
646
647 for (i = 0; i < CSIS_PADS_NUM; i++) {
648 mf = v4l2_subdev_get_try_format(mipi_sd, cfg, i);
649
650 ret = imx_media_init_mbus_fmt(mf, MIPI_CSIS_DEF_PIX_HEIGHT,
651 MIPI_CSIS_DEF_PIX_WIDTH, 0,
652 V4L2_FIELD_NONE, NULL);
653 if (ret < 0)
654 return ret;
655 }
656
657 return 0;
658 }
659
660 static struct csis_pix_format const *
661 mipi_csis_try_format(struct v4l2_subdev *mipi_sd, struct v4l2_mbus_framefmt *mf)
662 {
663 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
664 struct csis_pix_format const *csis_fmt;
665
666 csis_fmt = find_csis_format(mf->code);
667 if (!csis_fmt)
668 csis_fmt = &mipi_csis_formats[0];
669
670 v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
671 csis_fmt->pix_width_alignment,
672 &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
673 0);
674
675 state->format_mbus.code = csis_fmt->code;
676 state->format_mbus.width = mf->width;
677 state->format_mbus.height = mf->height;
678
679 return csis_fmt;
680 }
681
682 static struct v4l2_mbus_framefmt *
683 mipi_csis_get_format(struct csi_state *state,
684 struct v4l2_subdev_pad_config *cfg,
685 enum v4l2_subdev_format_whence which,
686 unsigned int pad)
687 {
688 if (which == V4L2_SUBDEV_FORMAT_TRY)
689 return v4l2_subdev_get_try_format(&state->mipi_sd, cfg, pad);
690
691 return &state->format_mbus;
692 }
693
694 static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd,
695 struct v4l2_subdev_pad_config *cfg,
696 struct v4l2_subdev_format *sdformat)
697 {
698 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
699 struct csis_pix_format const *csis_fmt;
700 struct v4l2_mbus_framefmt *fmt;
701
702 if (sdformat->pad >= CSIS_PADS_NUM)
703 return -EINVAL;
704
705 fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
706
707 mutex_lock(&state->lock);
708 if (sdformat->pad == CSIS_PAD_SOURCE) {
709 sdformat->format = *fmt;
710 goto unlock;
711 }
712
713 csis_fmt = mipi_csis_try_format(mipi_sd, &sdformat->format);
714
715 sdformat->format = *fmt;
716
717 if (csis_fmt && sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
718 state->csis_fmt = csis_fmt;
719 else
720 cfg->try_fmt = sdformat->format;
721
722 unlock:
723 mutex_unlock(&state->lock);
724
725 return 0;
726 }
727
728 static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd,
729 struct v4l2_subdev_pad_config *cfg,
730 struct v4l2_subdev_format *sdformat)
731 {
732 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
733 struct v4l2_mbus_framefmt *fmt;
734
735 mutex_lock(&state->lock);
736
737 fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
738
739 sdformat->format = *fmt;
740
741 mutex_unlock(&state->lock);
742
743 return 0;
744 }
745
746 static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd)
747 {
748 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
749
750 mutex_lock(&state->lock);
751 mipi_csis_log_counters(state, true);
752 if (state->debug && (state->flags & ST_POWERED))
753 mipi_csis_dump_regs(state);
754 mutex_unlock(&state->lock);
755
756 return 0;
757 }
758
759 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
760 {
761 struct csi_state *state = dev_id;
762 unsigned long flags;
763 unsigned int i;
764 u32 status;
765
766 status = mipi_csis_read(state, MIPI_CSIS_INTSRC);
767
768 spin_lock_irqsave(&state->slock, flags);
769
770
771 if ((status & MIPI_CSIS_INTSRC_ERRORS) || state->debug) {
772 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
773 if (!(status & state->events[i].mask))
774 continue;
775 state->events[i].counter++;
776 }
777 }
778 spin_unlock_irqrestore(&state->slock, flags);
779
780 mipi_csis_write(state, MIPI_CSIS_INTSRC, status);
781
782 return IRQ_HANDLED;
783 }
784
785 static int mipi_csis_registered(struct v4l2_subdev *mipi_sd)
786 {
787 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
788
789 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
790 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
791
792 return media_entity_pads_init(&state->mipi_sd.entity, CSIS_PADS_NUM,
793 state->pads);
794 }
795
796 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
797 .log_status = mipi_csis_log_status,
798 };
799
800 static const struct media_entity_operations mipi_csis_entity_ops = {
801 .link_setup = mipi_csis_link_setup,
802 .link_validate = v4l2_subdev_link_validate,
803 };
804
805 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
806 .s_stream = mipi_csis_s_stream,
807 };
808
809 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
810 .init_cfg = mipi_csis_init_cfg,
811 .get_fmt = mipi_csis_get_fmt,
812 .set_fmt = mipi_csis_set_fmt,
813 };
814
815 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
816 .core = &mipi_csis_core_ops,
817 .video = &mipi_csis_video_ops,
818 .pad = &mipi_csis_pad_ops,
819 };
820
821 static const struct v4l2_subdev_internal_ops mipi_csis_internal_ops = {
822 .registered = mipi_csis_registered,
823 };
824
825 static int mipi_csis_parse_dt(struct platform_device *pdev,
826 struct csi_state *state)
827 {
828 struct device_node *node = pdev->dev.of_node;
829
830 if (of_property_read_u32(node, "clock-frequency",
831 &state->clk_frequency))
832 state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
833
834
835 state->mrst = devm_reset_control_get_exclusive(&pdev->dev, "mrst");
836 if (IS_ERR(state->mrst))
837 return PTR_ERR(state->mrst);
838
839
840 of_property_read_u32(node, "fsl,csis-hs-settle", &state->hs_settle);
841
842 return 0;
843 }
844
845 static int mipi_csis_pm_resume(struct device *dev, bool runtime);
846
847 static int mipi_csis_parse_endpoint(struct device *dev,
848 struct v4l2_fwnode_endpoint *ep,
849 struct v4l2_async_subdev *asd)
850 {
851 struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
852 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
853
854 if (ep->bus_type != V4L2_MBUS_CSI2_DPHY) {
855 dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
856 return -EINVAL;
857 }
858
859 state->bus = ep->bus.mipi_csi2;
860
861 dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes);
862 dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags);
863
864 return 0;
865 }
866
867 static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd,
868 struct platform_device *pdev,
869 const struct v4l2_subdev_ops *ops)
870 {
871 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
872 unsigned int sink_port = 0;
873 int ret;
874
875 v4l2_subdev_init(mipi_sd, ops);
876 mipi_sd->owner = THIS_MODULE;
877 snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d",
878 CSIS_SUBDEV_NAME, state->index);
879
880 mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
881 mipi_sd->ctrl_handler = NULL;
882
883 mipi_sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
884 mipi_sd->entity.ops = &mipi_csis_entity_ops;
885 mipi_sd->internal_ops = &mipi_csis_internal_ops;
886
887 mipi_sd->dev = &pdev->dev;
888
889 state->csis_fmt = &mipi_csis_formats[0];
890 state->format_mbus.code = mipi_csis_formats[0].code;
891 state->format_mbus.width = MIPI_CSIS_DEF_PIX_WIDTH;
892 state->format_mbus.height = MIPI_CSIS_DEF_PIX_HEIGHT;
893 state->format_mbus.field = V4L2_FIELD_NONE;
894
895 v4l2_set_subdevdata(mipi_sd, &pdev->dev);
896
897 ret = v4l2_async_register_fwnode_subdev(mipi_sd,
898 sizeof(struct v4l2_async_subdev),
899 &sink_port, 1,
900 mipi_csis_parse_endpoint);
901 if (ret < 0)
902 dev_err(&pdev->dev, "async fwnode register failed: %d\n", ret);
903
904 return ret;
905 }
906
907 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
908 {
909 struct csi_state *state = m->private;
910
911 return mipi_csis_dump_regs(state);
912 }
913 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
914
915 static int mipi_csis_debugfs_init(struct csi_state *state)
916 {
917 struct dentry *d;
918
919 if (!debugfs_initialized())
920 return -ENODEV;
921
922 state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL);
923 if (!state->debugfs_root)
924 return -ENOMEM;
925
926 d = debugfs_create_bool("debug_enable", 0600, state->debugfs_root,
927 &state->debug);
928 if (!d)
929 goto remove_debugfs;
930
931 d = debugfs_create_file("dump_regs", 0600, state->debugfs_root,
932 state, &mipi_csis_dump_regs_fops);
933 if (!d)
934 goto remove_debugfs;
935
936 return 0;
937
938 remove_debugfs:
939 debugfs_remove_recursive(state->debugfs_root);
940
941 return -ENOMEM;
942 }
943
944 static void mipi_csis_debugfs_exit(struct csi_state *state)
945 {
946 debugfs_remove_recursive(state->debugfs_root);
947 }
948
949 static int mipi_csis_probe(struct platform_device *pdev)
950 {
951 struct device *dev = &pdev->dev;
952 struct resource *mem_res;
953 struct csi_state *state;
954 int ret;
955
956 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
957 if (!state)
958 return -ENOMEM;
959
960 spin_lock_init(&state->slock);
961
962 state->pdev = pdev;
963 state->dev = dev;
964
965 ret = mipi_csis_parse_dt(pdev, state);
966 if (ret < 0) {
967 dev_err(dev, "Failed to parse device tree: %d\n", ret);
968 return ret;
969 }
970
971 ret = mipi_csis_phy_init(state);
972 if (ret < 0)
973 return ret;
974
975 mipi_csis_phy_reset(state);
976
977 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
978 state->regs = devm_ioremap_resource(dev, mem_res);
979 if (IS_ERR(state->regs))
980 return PTR_ERR(state->regs);
981
982 state->irq = platform_get_irq(pdev, 0);
983 if (state->irq < 0)
984 return state->irq;
985
986 ret = mipi_csis_clk_get(state);
987 if (ret < 0)
988 return ret;
989
990 ret = mipi_csis_clk_enable(state);
991 if (ret < 0) {
992 dev_err(state->dev, "failed to enable clocks: %d\n", ret);
993 return ret;
994 }
995
996 ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler,
997 0, dev_name(dev), state);
998 if (ret) {
999 dev_err(dev, "Interrupt request failed\n");
1000 goto disable_clock;
1001 }
1002
1003 platform_set_drvdata(pdev, &state->mipi_sd);
1004
1005 mutex_init(&state->lock);
1006 ret = mipi_csis_subdev_init(&state->mipi_sd, pdev,
1007 &mipi_csis_subdev_ops);
1008 if (ret < 0)
1009 goto disable_clock;
1010
1011 memcpy(state->events, mipi_csis_events, sizeof(state->events));
1012
1013 mipi_csis_debugfs_init(state);
1014 pm_runtime_enable(dev);
1015 if (!pm_runtime_enabled(dev)) {
1016 ret = mipi_csis_pm_resume(dev, true);
1017 if (ret < 0)
1018 goto unregister_all;
1019 }
1020
1021 dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
1022 state->bus.num_data_lanes, state->hs_settle,
1023 state->wrap_clk ? 1 : 0, state->clk_frequency);
1024
1025 return 0;
1026
1027 unregister_all:
1028 mipi_csis_debugfs_exit(state);
1029 media_entity_cleanup(&state->mipi_sd.entity);
1030 v4l2_async_unregister_subdev(&state->mipi_sd);
1031 disable_clock:
1032 mipi_csis_clk_disable(state);
1033 mutex_destroy(&state->lock);
1034
1035 return ret;
1036 }
1037
1038 static int mipi_csis_pm_suspend(struct device *dev, bool runtime)
1039 {
1040 struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1041 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1042 int ret = 0;
1043
1044 mutex_lock(&state->lock);
1045 if (state->flags & ST_POWERED) {
1046 mipi_csis_stop_stream(state);
1047 ret = regulator_disable(state->mipi_phy_regulator);
1048 if (ret)
1049 goto unlock;
1050 mipi_csis_clk_disable(state);
1051 state->flags &= ~ST_POWERED;
1052 if (!runtime)
1053 state->flags |= ST_SUSPENDED;
1054 }
1055
1056 unlock:
1057 mutex_unlock(&state->lock);
1058
1059 return ret ? -EAGAIN : 0;
1060 }
1061
1062 static int mipi_csis_pm_resume(struct device *dev, bool runtime)
1063 {
1064 struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1065 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1066 int ret = 0;
1067
1068 mutex_lock(&state->lock);
1069 if (!runtime && !(state->flags & ST_SUSPENDED))
1070 goto unlock;
1071
1072 if (!(state->flags & ST_POWERED)) {
1073 ret = regulator_enable(state->mipi_phy_regulator);
1074 if (ret)
1075 goto unlock;
1076
1077 state->flags |= ST_POWERED;
1078 mipi_csis_clk_enable(state);
1079 }
1080 if (state->flags & ST_STREAMING)
1081 mipi_csis_start_stream(state);
1082
1083 state->flags &= ~ST_SUSPENDED;
1084
1085 unlock:
1086 mutex_unlock(&state->lock);
1087
1088 return ret ? -EAGAIN : 0;
1089 }
1090
1091 static int __maybe_unused mipi_csis_suspend(struct device *dev)
1092 {
1093 return mipi_csis_pm_suspend(dev, false);
1094 }
1095
1096 static int __maybe_unused mipi_csis_resume(struct device *dev)
1097 {
1098 return mipi_csis_pm_resume(dev, false);
1099 }
1100
1101 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1102 {
1103 return mipi_csis_pm_suspend(dev, true);
1104 }
1105
1106 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1107 {
1108 return mipi_csis_pm_resume(dev, true);
1109 }
1110
1111 static int mipi_csis_remove(struct platform_device *pdev)
1112 {
1113 struct v4l2_subdev *mipi_sd = platform_get_drvdata(pdev);
1114 struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1115
1116 mipi_csis_debugfs_exit(state);
1117 v4l2_async_unregister_subdev(&state->mipi_sd);
1118 v4l2_async_notifier_unregister(&state->subdev_notifier);
1119
1120 pm_runtime_disable(&pdev->dev);
1121 mipi_csis_pm_suspend(&pdev->dev, true);
1122 mipi_csis_clk_disable(state);
1123 media_entity_cleanup(&state->mipi_sd.entity);
1124 mutex_destroy(&state->lock);
1125 pm_runtime_set_suspended(&pdev->dev);
1126
1127 return 0;
1128 }
1129
1130 static const struct dev_pm_ops mipi_csis_pm_ops = {
1131 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1132 NULL)
1133 SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume)
1134 };
1135
1136 static const struct of_device_id mipi_csis_of_match[] = {
1137 { .compatible = "fsl,imx7-mipi-csi2", },
1138 { },
1139 };
1140 MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1141
1142 static struct platform_driver mipi_csis_driver = {
1143 .probe = mipi_csis_probe,
1144 .remove = mipi_csis_remove,
1145 .driver = {
1146 .of_match_table = mipi_csis_of_match,
1147 .name = CSIS_DRIVER_NAME,
1148 .pm = &mipi_csis_pm_ops,
1149 },
1150 };
1151
1152 module_platform_driver(mipi_csis_driver);
1153
1154 MODULE_DESCRIPTION("i.MX7 MIPI CSI-2 Receiver driver");
1155 MODULE_LICENSE("GPL v2");
1156 MODULE_ALIAS("platform:imx7-mipi-csi2");