root/drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c

DEFINITIONS

1. rk3399_vpu_set_src_img_ctrl
2. rk3399_vpu_jpeg_enc_set_buffers
3. rk3399_vpu_jpeg_enc_set_qtable
4. rk3399_vpu_jpeg_enc_run

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hantro VPU codec driver
   4  *
   5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
   6  *
   7  * JPEG encoder
   8  * ------------
   9  * The VPU JPEG encoder produces JPEG baseline sequential format.
  10  * The quantization coefficients are 8-bit values, complying with
  11  * the baseline specification. Therefore, it requires
  12  * luma and chroma quantization tables. The hardware does entropy
  13  * encoding using internal Huffman tables, as specified in the JPEG
  14  * specification.
  15  *
  16  * In other words, only the luma and chroma quantization tables are
  17  * required for the encoding operation.
  18  *
  19  * Quantization luma table values are written to registers
  20  * VEPU_swreg_0-VEPU_swreg_15, and chroma table values to
  21  * VEPU_swreg_16-VEPU_swreg_31.
  22  *
  23  * JPEG zigzag order is expected on the quantization tables.
  24  */
  25 
  26 #include <asm/unaligned.h>
  27 #include <media/v4l2-mem2mem.h>
  28 #include "hantro_jpeg.h"
  29 #include "hantro.h"
  30 #include "hantro_v4l2.h"
  31 #include "hantro_hw.h"
  32 #include "rk3399_vpu_regs.h"
  33 
  34 #define VEPU_JPEG_QUANT_TABLE_COUNT 16
  35 
  36 static void rk3399_vpu_set_src_img_ctrl(struct hantro_dev *vpu,
  37                                         struct hantro_ctx *ctx)
  38 {
  39         struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
  40         u32 reg;
  41 
  42         /*
  43          * The pix fmt width/height are already macroblock aligned
  44          * by .vidioc_s_fmt_vid_cap_mplane() callback
  45          */
  46         reg = VEPU_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width);
  47         vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO);
  48 
  49         reg = VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(0) |
  50               VEPU_REG_IN_IMG_CTRL_OVRFLB(0);
  51         /*
  52          * This register controls the input crop, as the offset
  53          * from the right/bottom within the last macroblock. The offset from the
  54          * right must be divided by 4 and so the crop must be aligned to 4 pixels
  55          * horizontally.
  56          */
  57         vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET);
  58 
  59         reg = VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
  60         vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1);
  61 }
  62 
  63 static void rk3399_vpu_jpeg_enc_set_buffers(struct hantro_dev *vpu,
  64                                             struct hantro_ctx *ctx,
  65                                             struct vb2_buffer *src_buf)
  66 {
  67         struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
  68         dma_addr_t src[3];
  69 
  70         WARN_ON(pix_fmt->num_planes > 3);
  71 
  72         vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma,
  73                            VEPU_REG_ADDR_OUTPUT_STREAM);
  74         vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size,
  75                            VEPU_REG_STR_BUF_LIMIT);
  76 
  77         if (pix_fmt->num_planes == 1) {
  78                 src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  79                 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
  80         } else if (pix_fmt->num_planes == 2) {
  81                 src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  82                 src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
  83                 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
  84                 vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);
  85         } else {
  86                 src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  87                 src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
  88                 src[2] = vb2_dma_contig_plane_dma_addr(src_buf, 2);
  89                 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
  90                 vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);
  91                 vepu_write_relaxed(vpu, src[2], VEPU_REG_ADDR_IN_PLANE_2);
  92         }
  93 }
  94 
  95 static void
  96 rk3399_vpu_jpeg_enc_set_qtable(struct hantro_dev *vpu,
  97                                unsigned char *luma_qtable,
  98                                unsigned char *chroma_qtable)
  99 {
 100         u32 reg, i;
 101         __be32 *luma_qtable_p;
 102         __be32 *chroma_qtable_p;
 103 
 104         luma_qtable_p = (__be32 *)luma_qtable;
 105         chroma_qtable_p = (__be32 *)chroma_qtable;
 106 
 107         for (i = 0; i < VEPU_JPEG_QUANT_TABLE_COUNT; i++) {
 108                 reg = get_unaligned_be32(&luma_qtable_p[i]);
 109                 vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_LUMA_QUAT(i));
 110 
 111                 reg = get_unaligned_be32(&chroma_qtable_p[i]);
 112                 vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_CHROMA_QUAT(i));
 113         }
 114 }
 115 
 116 void rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx)
 117 {
 118         struct hantro_dev *vpu = ctx->dev;
 119         struct vb2_v4l2_buffer *src_buf, *dst_buf;
 120         struct hantro_jpeg_ctx jpeg_ctx;
 121         u32 reg;
 122 
 123         src_buf = hantro_get_src_buf(ctx);
 124         dst_buf = hantro_get_dst_buf(ctx);
 125 
 126         hantro_prepare_run(ctx);
 127 
 128         memset(&jpeg_ctx, 0, sizeof(jpeg_ctx));
 129         jpeg_ctx.buffer = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
 130         jpeg_ctx.width = ctx->dst_fmt.width;
 131         jpeg_ctx.height = ctx->dst_fmt.height;
 132         jpeg_ctx.quality = ctx->jpeg_quality;
 133         hantro_jpeg_header_assemble(&jpeg_ctx);
 134 
 135         /* Switch to JPEG encoder mode before writing registers */
 136         vepu_write_relaxed(vpu, VEPU_REG_ENCODE_FORMAT_JPEG,
 137                            VEPU_REG_ENCODE_START);
 138 
 139         rk3399_vpu_set_src_img_ctrl(vpu, ctx);
 140         rk3399_vpu_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);
 141         rk3399_vpu_jpeg_enc_set_qtable(vpu,
 142                                        hantro_jpeg_get_qtable(&jpeg_ctx, 0),
 143                                        hantro_jpeg_get_qtable(&jpeg_ctx, 1));
 144 
 145         reg = VEPU_REG_OUTPUT_SWAP32
 146                 | VEPU_REG_OUTPUT_SWAP16
 147                 | VEPU_REG_OUTPUT_SWAP8
 148                 | VEPU_REG_INPUT_SWAP8
 149                 | VEPU_REG_INPUT_SWAP16
 150                 | VEPU_REG_INPUT_SWAP32;
 151         /* Make sure that all registers are written at this point. */
 152         vepu_write(vpu, reg, VEPU_REG_DATA_ENDIAN);
 153 
 154         reg = VEPU_REG_AXI_CTRL_BURST_LEN(16);
 155         vepu_write_relaxed(vpu, reg, VEPU_REG_AXI_CTRL);
 156 
 157         reg = VEPU_REG_MB_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width))
 158                 | VEPU_REG_MB_HEIGHT(JPEG_MB_HEIGHT(ctx->src_fmt.height))
 159                 | VEPU_REG_FRAME_TYPE_INTRA
 160                 | VEPU_REG_ENCODE_FORMAT_JPEG
 161                 | VEPU_REG_ENCODE_ENABLE;
 162 
 163         /* Kick the watchdog and start encoding */
 164         hantro_finish_run(ctx);
 165         vepu_write(vpu, reg, VEPU_REG_ENCODE_START);
 166 }