This source file includes following definitions.
- allegro_set_state
- allegro_get_state
- msg_type_name
- allegro_next_user_id
- allegro_find_channel_by_user_id
- allegro_find_channel_by_channel_id
- channel_exists
- estimate_stream_size
- select_minimum_h264_level
- maximum_bitrate
- maximum_cpb_size
- allegro_get_firmware_info
- allegro_alloc_buffer
- allegro_free_buffer
- allegro_mbox_init
- allegro_mbox_write
- allegro_mbox_read
- allegro_mcu_interrupt
- allegro_mcu_send_init
- v4l2_pixelformat_to_mcu_format
- v4l2_colorspace_to_mcu_colorspace
- v4l2_pixelformat_to_mcu_codec
- v4l2_profile_to_mcu_profile
- v4l2_level_to_mcu_level
- v4l2_bitrate_mode_to_mcu_mode
- allegro_mcu_send_create_channel
- allegro_mcu_send_destroy_channel
- allegro_mcu_send_put_stream_buffer
- allegro_mcu_send_encode_frame
- allegro_mcu_wait_for_init_timeout
- allegro_mcu_push_buffer_internal
- allegro_mcu_push_buffer_intermediate
- allegro_mcu_push_buffer_reference
- allocate_buffers_internal
- destroy_buffers_internal
- destroy_reference_buffers
- destroy_intermediate_buffers
- allocate_intermediate_buffers
- allocate_reference_buffers
- allegro_h264_write_sps
- allegro_h264_write_pps
- allegro_channel_is_at_eos
- allegro_channel_buf_done
- allegro_channel_finish_frame
- allegro_handle_init
- allegro_handle_create_channel
- allegro_handle_destroy_channel
- allegro_handle_encode_frame
- allegro_receive_message
- allegro_hardirq
- allegro_irq_thread
- allegro_copy_firmware
- allegro_copy_fw_codec
- allegro_free_fw_codec
- allegro_mcu_enable_interrupts
- allegro_mcu_disable_interrupts
- allegro_mcu_wait_for_sleep
- allegro_mcu_start
- allegro_mcu_reset
- allegro_destroy_channel
- allegro_create_channel
- allegro_set_default_params
- allegro_queue_setup
- allegro_buf_prepare
- allegro_buf_queue
- allegro_start_streaming
- allegro_stop_streaming
- allegro_queue_init
- allegro_s_ctrl
- allegro_open
- allegro_release
- allegro_querycap
- allegro_enum_fmt_vid
- allegro_g_fmt_vid_cap
- allegro_try_fmt_vid_cap
- allegro_g_fmt_vid_out
- allegro_try_fmt_vid_out
- allegro_s_fmt_vid_out
- allegro_channel_cmd_stop
- allegro_channel_cmd_start
- allegro_encoder_cmd
- allegro_enum_framesizes
- allegro_ioctl_streamon
- allegro_subscribe_event
- allegro_register_device
- allegro_device_run
- allegro_mcu_hw_init
- allegro_mcu_hw_deinit
- allegro_fw_callback
- allegro_firmware_request_nowait
- allegro_probe
- allegro_remove
1
2
3
4
5
6
7
8 #include <linux/firmware.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/log2.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
18 #include <linux/sizes.h>
19 #include <linux/slab.h>
20 #include <linux/videodev2.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-event.h>
24 #include <media/v4l2-ioctl.h>
25 #include <media/v4l2-mem2mem.h>
26 #include <media/videobuf2-dma-contig.h>
27 #include <media/videobuf2-v4l2.h>
28
29 #include "nal-h264.h"
30
31
32
33
34
35
36 #define ALLEGRO_WIDTH_MIN 128
37 #define ALLEGRO_WIDTH_DEFAULT 1920
38 #define ALLEGRO_WIDTH_MAX 3840
39 #define ALLEGRO_HEIGHT_MIN 64
40 #define ALLEGRO_HEIGHT_DEFAULT 1080
41 #define ALLEGRO_HEIGHT_MAX 2160
42
43 #define ALLEGRO_GOP_SIZE_DEFAULT 25
44 #define ALLEGRO_GOP_SIZE_MAX 1000
45
46
47
48
49
50
51
52
53
54 #define AL5_MCU_RESET 0x0000
55 #define AL5_MCU_RESET_SOFT BIT(0)
56 #define AL5_MCU_RESET_REGS BIT(1)
57 #define AL5_MCU_RESET_MODE 0x0004
58 #define AL5_MCU_RESET_MODE_SLEEP BIT(0)
59 #define AL5_MCU_RESET_MODE_HALT BIT(1)
60 #define AL5_MCU_STA 0x0008
61 #define AL5_MCU_STA_SLEEP BIT(0)
62 #define AL5_MCU_WAKEUP 0x000c
63
64 #define AL5_ICACHE_ADDR_OFFSET_MSB 0x0010
65 #define AL5_ICACHE_ADDR_OFFSET_LSB 0x0014
66 #define AL5_DCACHE_ADDR_OFFSET_MSB 0x0018
67 #define AL5_DCACHE_ADDR_OFFSET_LSB 0x001c
68
69 #define AL5_MCU_INTERRUPT 0x0100
70 #define AL5_ITC_CPU_IRQ_MSK 0x0104
71 #define AL5_ITC_CPU_IRQ_CLR 0x0108
72 #define AL5_ITC_CPU_IRQ_STA 0x010C
73 #define AL5_ITC_CPU_IRQ_STA_TRIGGERED BIT(0)
74
75 #define AXI_ADDR_OFFSET_IP 0x0208
76
77
78
79
80
81 #define MCU_CACHE_OFFSET SZ_2G
82
83
84
85
86
87
88 #define ENCODER_STREAM_OFFSET SZ_64
89
90 #define SIZE_MACROBLOCK 16
91
92 static int debug;
93 module_param(debug, int, 0644);
94 MODULE_PARM_DESC(debug, "Debug level (0-2)");
95
96 struct allegro_buffer {
97 void *vaddr;
98 dma_addr_t paddr;
99 size_t size;
100 struct list_head head;
101 };
102
103 struct allegro_channel;
104
105 struct allegro_mbox {
106 unsigned int head;
107 unsigned int tail;
108 unsigned int data;
109 size_t size;
110
111 struct mutex lock;
112 };
113
114 struct allegro_dev {
115 struct v4l2_device v4l2_dev;
116 struct video_device video_dev;
117 struct v4l2_m2m_dev *m2m_dev;
118 struct platform_device *plat_dev;
119
120
121 struct mutex lock;
122
123 struct regmap *regmap;
124 struct regmap *sram;
125
126 struct allegro_buffer firmware;
127 struct allegro_buffer suballocator;
128
129 struct completion init_complete;
130
131
132 struct allegro_mbox mbox_command;
133 struct allegro_mbox mbox_status;
134
135
136
137
138
139
140 unsigned long channel_user_ids;
141 struct list_head channels;
142 };
143
144 static struct regmap_config allegro_regmap_config = {
145 .name = "regmap",
146 .reg_bits = 32,
147 .val_bits = 32,
148 .reg_stride = 4,
149 .max_register = 0xfff,
150 .cache_type = REGCACHE_NONE,
151 };
152
153 static struct regmap_config allegro_sram_config = {
154 .name = "sram",
155 .reg_bits = 32,
156 .val_bits = 32,
157 .reg_stride = 4,
158 .max_register = 0x7fff,
159 .cache_type = REGCACHE_NONE,
160 };
161
162 enum allegro_state {
163 ALLEGRO_STATE_ENCODING,
164 ALLEGRO_STATE_DRAIN,
165 ALLEGRO_STATE_WAIT_FOR_BUFFER,
166 ALLEGRO_STATE_STOPPED,
167 };
168
169 #define fh_to_channel(__fh) container_of(__fh, struct allegro_channel, fh)
170
171 struct allegro_channel {
172 struct allegro_dev *dev;
173 struct v4l2_fh fh;
174 struct v4l2_ctrl_handler ctrl_handler;
175
176 unsigned int width;
177 unsigned int height;
178 unsigned int stride;
179
180 enum v4l2_colorspace colorspace;
181 enum v4l2_ycbcr_encoding ycbcr_enc;
182 enum v4l2_quantization quantization;
183 enum v4l2_xfer_func xfer_func;
184
185 u32 pixelformat;
186 unsigned int sizeimage_raw;
187 unsigned int osequence;
188
189 u32 codec;
190 enum v4l2_mpeg_video_h264_profile profile;
191 enum v4l2_mpeg_video_h264_level level;
192 unsigned int sizeimage_encoded;
193 unsigned int csequence;
194
195 enum v4l2_mpeg_video_bitrate_mode bitrate_mode;
196 unsigned int bitrate;
197 unsigned int bitrate_peak;
198 unsigned int cpb_size;
199 unsigned int gop_size;
200
201 struct v4l2_ctrl *mpeg_video_h264_profile;
202 struct v4l2_ctrl *mpeg_video_h264_level;
203 struct v4l2_ctrl *mpeg_video_bitrate_mode;
204 struct v4l2_ctrl *mpeg_video_bitrate;
205 struct v4l2_ctrl *mpeg_video_bitrate_peak;
206 struct v4l2_ctrl *mpeg_video_cpb_size;
207 struct v4l2_ctrl *mpeg_video_gop_size;
208
209
210
211 int user_id;
212
213 int mcu_channel_id;
214
215 struct list_head buffers_reference;
216 struct list_head buffers_intermediate;
217
218 struct list_head list;
219 struct completion completion;
220
221 unsigned int error;
222 enum allegro_state state;
223 };
224
225 static inline int
226 allegro_set_state(struct allegro_channel *channel, enum allegro_state state)
227 {
228 channel->state = state;
229
230 return 0;
231 }
232
233 static inline enum allegro_state
234 allegro_get_state(struct allegro_channel *channel)
235 {
236 return channel->state;
237 }
238
239 struct fw_info {
240 unsigned int id;
241 unsigned int id_codec;
242 char *version;
243 unsigned int mailbox_cmd;
244 unsigned int mailbox_status;
245 size_t mailbox_size;
246 size_t suballocator_size;
247 };
248
249 static const struct fw_info supported_firmware[] = {
250 {
251 .id = 18296,
252 .id_codec = 96272,
253 .version = "v2018.2",
254 .mailbox_cmd = 0x7800,
255 .mailbox_status = 0x7c00,
256 .mailbox_size = 0x400 - 0x8,
257 .suballocator_size = SZ_16M,
258 },
259 };
260
261 enum mcu_msg_type {
262 MCU_MSG_TYPE_INIT = 0x0000,
263 MCU_MSG_TYPE_CREATE_CHANNEL = 0x0005,
264 MCU_MSG_TYPE_DESTROY_CHANNEL = 0x0006,
265 MCU_MSG_TYPE_ENCODE_FRAME = 0x0007,
266 MCU_MSG_TYPE_PUT_STREAM_BUFFER = 0x0012,
267 MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE = 0x000e,
268 MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE = 0x000f,
269 };
270
271 static const char *msg_type_name(enum mcu_msg_type type)
272 {
273 static char buf[9];
274
275 switch (type) {
276 case MCU_MSG_TYPE_INIT:
277 return "INIT";
278 case MCU_MSG_TYPE_CREATE_CHANNEL:
279 return "CREATE_CHANNEL";
280 case MCU_MSG_TYPE_DESTROY_CHANNEL:
281 return "DESTROY_CHANNEL";
282 case MCU_MSG_TYPE_ENCODE_FRAME:
283 return "ENCODE_FRAME";
284 case MCU_MSG_TYPE_PUT_STREAM_BUFFER:
285 return "PUT_STREAM_BUFFER";
286 case MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE:
287 return "PUSH_BUFFER_INTERMEDIATE";
288 case MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE:
289 return "PUSH_BUFFER_REFERENCE";
290 default:
291 snprintf(buf, sizeof(buf), "(0x%04x)", type);
292 return buf;
293 }
294 }
295
296 struct mcu_msg_header {
297 u16 length;
298 u16 type;
299 } __attribute__ ((__packed__));
300
301 struct mcu_msg_init_request {
302 struct mcu_msg_header header;
303 u32 reserved0;
304 u32 suballoc_dma;
305 u32 suballoc_size;
306 s32 l2_cache[3];
307 } __attribute__ ((__packed__));
308
309 struct mcu_msg_init_response {
310 struct mcu_msg_header header;
311 u32 reserved0;
312 } __attribute__ ((__packed__));
313
314 struct mcu_msg_create_channel {
315 struct mcu_msg_header header;
316 u32 user_id;
317 u16 width;
318 u16 height;
319 u32 format;
320 u32 colorspace;
321 u32 src_mode;
322 u8 profile;
323 u16 constraint_set_flags;
324 s8 codec;
325 u16 level;
326 u16 tier;
327 u32 sps_param;
328 u32 pps_param;
329
330 u32 enc_option;
331 #define AL_OPT_WPP BIT(0)
332 #define AL_OPT_TILE BIT(1)
333 #define AL_OPT_LF BIT(2)
334 #define AL_OPT_LF_X_SLICE BIT(3)
335 #define AL_OPT_LF_X_TILE BIT(4)
336 #define AL_OPT_SCL_LST BIT(5)
337 #define AL_OPT_CONST_INTRA_PRED BIT(6)
338 #define AL_OPT_QP_TAB_RELATIVE BIT(7)
339 #define AL_OPT_FIX_PREDICTOR BIT(8)
340 #define AL_OPT_CUSTOM_LDA BIT(9)
341 #define AL_OPT_ENABLE_AUTO_QP BIT(10)
342 #define AL_OPT_ADAPT_AUTO_QP BIT(11)
343 #define AL_OPT_TRANSFO_SKIP BIT(13)
344 #define AL_OPT_FORCE_REC BIT(15)
345 #define AL_OPT_FORCE_MV_OUT BIT(16)
346 #define AL_OPT_FORCE_MV_CLIP BIT(17)
347 #define AL_OPT_LOWLAT_SYNC BIT(18)
348 #define AL_OPT_LOWLAT_INT BIT(19)
349 #define AL_OPT_RDO_COST_MODE BIT(20)
350
351 s8 beta_offset;
352 s8 tc_offset;
353 u16 reserved10;
354 u32 unknown11;
355 u32 unknown12;
356 u16 num_slices;
357 u16 prefetch_auto;
358 u32 prefetch_mem_offset;
359 u32 prefetch_mem_size;
360 u16 clip_hrz_range;
361 u16 clip_vrt_range;
362 u16 me_range[4];
363 u8 max_cu_size;
364 u8 min_cu_size;
365 u8 max_tu_size;
366 u8 min_tu_size;
367 u8 max_transfo_depth_inter;
368 u8 max_transfo_depth_intra;
369 u16 reserved20;
370 u32 entropy_mode;
371 u32 wp_mode;
372
373
374 u32 rate_control_mode;
375 u32 initial_rem_delay;
376 u32 cpb_size;
377 u16 framerate;
378 u16 clk_ratio;
379 u32 target_bitrate;
380 u32 max_bitrate;
381 u16 initial_qp;
382 u16 min_qp;
383 u16 max_qp;
384 s16 ip_delta;
385 s16 pb_delta;
386 u16 golden_ref;
387 u16 golden_delta;
388 u16 golden_ref_frequency;
389 u32 rate_control_option;
390
391
392 u32 gop_ctrl_mode;
393 u32 freq_ird;
394 u32 freq_lt;
395 u32 gdr_mode;
396 u16 gop_length;
397 u8 num_b;
398 u8 freq_golden_ref;
399
400 u32 unknown39;
401
402 u32 subframe_latency;
403 u32 lda_control_mode;
404 } __attribute__ ((__packed__));
405
406 struct mcu_msg_create_channel_response {
407 struct mcu_msg_header header;
408 u32 channel_id;
409 u32 user_id;
410 u32 options;
411 u32 num_core;
412 u32 pps_param;
413 u32 int_buffers_count;
414 u32 int_buffers_size;
415 u32 rec_buffers_count;
416 u32 rec_buffers_size;
417 u32 reserved;
418 u32 error_code;
419 } __attribute__ ((__packed__));
420
421 struct mcu_msg_destroy_channel {
422 struct mcu_msg_header header;
423 u32 channel_id;
424 } __attribute__ ((__packed__));
425
426 struct mcu_msg_destroy_channel_response {
427 struct mcu_msg_header header;
428 u32 channel_id;
429 } __attribute__ ((__packed__));
430
431 struct mcu_msg_push_buffers_internal_buffer {
432 u32 dma_addr;
433 u32 mcu_addr;
434 u32 size;
435 } __attribute__ ((__packed__));
436
437 struct mcu_msg_push_buffers_internal {
438 struct mcu_msg_header header;
439 u32 channel_id;
440 struct mcu_msg_push_buffers_internal_buffer buffer[0];
441 } __attribute__ ((__packed__));
442
443 struct mcu_msg_put_stream_buffer {
444 struct mcu_msg_header header;
445 u32 channel_id;
446 u32 dma_addr;
447 u32 mcu_addr;
448 u32 size;
449 u32 offset;
450 u64 stream_id;
451 } __attribute__ ((__packed__));
452
453 struct mcu_msg_encode_frame {
454 struct mcu_msg_header header;
455 u32 channel_id;
456 u32 reserved;
457
458 u32 encoding_options;
459 #define AL_OPT_USE_QP_TABLE BIT(0)
460 #define AL_OPT_FORCE_LOAD BIT(1)
461 #define AL_OPT_USE_L2 BIT(2)
462 #define AL_OPT_DISABLE_INTRA BIT(3)
463 #define AL_OPT_DEPENDENT_SLICES BIT(4)
464
465 s16 pps_qp;
466 u16 padding;
467 u64 user_param;
468 u64 src_handle;
469
470 u32 request_options;
471 #define AL_OPT_SCENE_CHANGE BIT(0)
472 #define AL_OPT_RESTART_GOP BIT(1)
473 #define AL_OPT_USE_LONG_TERM BIT(2)
474 #define AL_OPT_UPDATE_PARAMS BIT(3)
475
476
477
478
479 u32 src_y;
480 u32 src_uv;
481 u32 stride;
482 u32 ep2;
483 u64 ep2_v;
484 } __attribute__ ((__packed__));
485
486 struct mcu_msg_encode_frame_response {
487 struct mcu_msg_header header;
488 u32 channel_id;
489 u64 stream_id;
490 u64 user_param;
491 u64 src_handle;
492 u16 skip;
493 u16 is_ref;
494 u32 initial_removal_delay;
495 u32 dpb_output_delay;
496 u32 size;
497 u32 frame_tag_size;
498 s32 stuffing;
499 s32 filler;
500 u16 num_column;
501 u16 num_row;
502 u16 qp;
503 u8 num_ref_idx_l0;
504 u8 num_ref_idx_l1;
505 u32 partition_table_offset;
506 s32 partition_table_size;
507 u32 sum_complex;
508 s32 tile_width[4];
509 s32 tile_height[22];
510 u32 error_code;
511
512 u32 slice_type;
513 #define AL_ENC_SLICE_TYPE_B 0
514 #define AL_ENC_SLICE_TYPE_P 1
515 #define AL_ENC_SLICE_TYPE_I 2
516
517 u32 pic_struct;
518 u8 is_idr;
519 u8 is_first_slice;
520 u8 is_last_slice;
521 u8 reserved;
522 u16 pps_qp;
523 u16 reserved1;
524 u32 reserved2;
525 } __attribute__ ((__packed__));
526
527 union mcu_msg_response {
528 struct mcu_msg_header header;
529 struct mcu_msg_init_response init;
530 struct mcu_msg_create_channel_response create_channel;
531 struct mcu_msg_destroy_channel_response destroy_channel;
532 struct mcu_msg_encode_frame_response encode_frame;
533 };
534
535
536
537 static unsigned long allegro_next_user_id(struct allegro_dev *dev)
538 {
539 if (dev->channel_user_ids == ~0UL)
540 return -EBUSY;
541
542 return ffz(dev->channel_user_ids);
543 }
544
545 static struct allegro_channel *
546 allegro_find_channel_by_user_id(struct allegro_dev *dev,
547 unsigned int user_id)
548 {
549 struct allegro_channel *channel;
550
551 list_for_each_entry(channel, &dev->channels, list) {
552 if (channel->user_id == user_id)
553 return channel;
554 }
555
556 return ERR_PTR(-EINVAL);
557 }
558
559 static struct allegro_channel *
560 allegro_find_channel_by_channel_id(struct allegro_dev *dev,
561 unsigned int channel_id)
562 {
563 struct allegro_channel *channel;
564
565 list_for_each_entry(channel, &dev->channels, list) {
566 if (channel->mcu_channel_id == channel_id)
567 return channel;
568 }
569
570 return ERR_PTR(-EINVAL);
571 }
572
573 static inline bool channel_exists(struct allegro_channel *channel)
574 {
575 return channel->mcu_channel_id != -1;
576 }
577
578 static unsigned int estimate_stream_size(unsigned int width,
579 unsigned int height)
580 {
581 unsigned int offset = ENCODER_STREAM_OFFSET;
582 unsigned int num_blocks = DIV_ROUND_UP(width, SIZE_MACROBLOCK) *
583 DIV_ROUND_UP(height, SIZE_MACROBLOCK);
584 unsigned int pcm_size = SZ_256;
585 unsigned int partition_table = SZ_256;
586
587 return round_up(offset + num_blocks * pcm_size + partition_table, 32);
588 }
589
590 static enum v4l2_mpeg_video_h264_level
591 select_minimum_h264_level(unsigned int width, unsigned int height)
592 {
593 unsigned int pic_width_in_mb = DIV_ROUND_UP(width, SIZE_MACROBLOCK);
594 unsigned int frame_height_in_mb = DIV_ROUND_UP(height, SIZE_MACROBLOCK);
595 unsigned int frame_size_in_mb = pic_width_in_mb * frame_height_in_mb;
596 enum v4l2_mpeg_video_h264_level level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
597
598
599
600
601
602
603
604
605 if (frame_size_in_mb <= 99)
606 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
607 else if (frame_size_in_mb <= 396)
608 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
609 else if (frame_size_in_mb <= 792)
610 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
611 else if (frame_size_in_mb <= 1620)
612 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
613 else if (frame_size_in_mb <= 3600)
614 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
615 else if (frame_size_in_mb <= 5120)
616 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
617 else if (frame_size_in_mb <= 8192)
618 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
619 else if (frame_size_in_mb <= 8704)
620 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
621 else if (frame_size_in_mb <= 22080)
622 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_0;
623 else
624 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_1;
625
626 return level;
627 }
628
629 static unsigned int maximum_bitrate(enum v4l2_mpeg_video_h264_level level)
630 {
631 switch (level) {
632 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
633 return 64000;
634 case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
635 return 128000;
636 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
637 return 192000;
638 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
639 return 384000;
640 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
641 return 768000;
642 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
643 return 2000000;
644 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
645 return 4000000;
646 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
647 return 4000000;
648 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
649 return 10000000;
650 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
651 return 14000000;
652 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
653 return 20000000;
654 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
655 return 20000000;
656 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
657 return 50000000;
658 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
659 return 50000000;
660 case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
661 return 135000000;
662 case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
663 default:
664 return 240000000;
665 }
666 }
667
668 static unsigned int maximum_cpb_size(enum v4l2_mpeg_video_h264_level level)
669 {
670 switch (level) {
671 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
672 return 175;
673 case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
674 return 350;
675 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
676 return 500;
677 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
678 return 1000;
679 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
680 return 2000;
681 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
682 return 2000;
683 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
684 return 4000;
685 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
686 return 4000;
687 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
688 return 10000;
689 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
690 return 14000;
691 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
692 return 20000;
693 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
694 return 25000;
695 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
696 return 62500;
697 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
698 return 62500;
699 case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
700 return 135000;
701 case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
702 default:
703 return 240000;
704 }
705 }
706
707 static const struct fw_info *
708 allegro_get_firmware_info(struct allegro_dev *dev,
709 const struct firmware *fw,
710 const struct firmware *fw_codec)
711 {
712 int i;
713 unsigned int id = fw->size;
714 unsigned int id_codec = fw_codec->size;
715
716 for (i = 0; i < ARRAY_SIZE(supported_firmware); i++)
717 if (supported_firmware[i].id == id &&
718 supported_firmware[i].id_codec == id_codec)
719 return &supported_firmware[i];
720
721 return NULL;
722 }
723
724
725
726
727
728 static int allegro_alloc_buffer(struct allegro_dev *dev,
729 struct allegro_buffer *buffer, size_t size)
730 {
731 buffer->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size,
732 &buffer->paddr, GFP_KERNEL);
733 if (!buffer->vaddr)
734 return -ENOMEM;
735 buffer->size = size;
736
737 return 0;
738 }
739
740 static void allegro_free_buffer(struct allegro_dev *dev,
741 struct allegro_buffer *buffer)
742 {
743 if (buffer->vaddr) {
744 dma_free_coherent(&dev->plat_dev->dev, buffer->size,
745 buffer->vaddr, buffer->paddr);
746 buffer->vaddr = NULL;
747 buffer->size = 0;
748 }
749 }
750
751
752
753
754
755 static int allegro_mbox_init(struct allegro_dev *dev,
756 struct allegro_mbox *mbox,
757 unsigned int base, size_t size)
758 {
759 if (!mbox)
760 return -EINVAL;
761
762 mbox->head = base;
763 mbox->tail = base + 0x4;
764 mbox->data = base + 0x8;
765 mbox->size = size;
766 mutex_init(&mbox->lock);
767
768 regmap_write(dev->sram, mbox->head, 0);
769 regmap_write(dev->sram, mbox->tail, 0);
770
771 return 0;
772 }
773
774 static int allegro_mbox_write(struct allegro_dev *dev,
775 struct allegro_mbox *mbox, void *src, size_t size)
776 {
777 struct mcu_msg_header *header = src;
778 unsigned int tail;
779 size_t size_no_wrap;
780 int err = 0;
781
782 if (!src)
783 return -EINVAL;
784
785 if (size > mbox->size) {
786 v4l2_err(&dev->v4l2_dev,
787 "message (%zu bytes) to large for mailbox (%zu bytes)\n",
788 size, mbox->size);
789 return -EINVAL;
790 }
791
792 if (header->length != size - sizeof(*header)) {
793 v4l2_err(&dev->v4l2_dev,
794 "invalid message length: %u bytes (expected %zu bytes)\n",
795 header->length, size - sizeof(*header));
796 return -EINVAL;
797 }
798
799 v4l2_dbg(2, debug, &dev->v4l2_dev,
800 "write command message: type %s, body length %d\n",
801 msg_type_name(header->type), header->length);
802
803 mutex_lock(&mbox->lock);
804 regmap_read(dev->sram, mbox->tail, &tail);
805 if (tail > mbox->size) {
806 v4l2_err(&dev->v4l2_dev,
807 "invalid tail (0x%x): must be smaller than mailbox size (0x%zx)\n",
808 tail, mbox->size);
809 err = -EIO;
810 goto out;
811 }
812 size_no_wrap = min(size, mbox->size - (size_t)tail);
813 regmap_bulk_write(dev->sram, mbox->data + tail, src, size_no_wrap / 4);
814 regmap_bulk_write(dev->sram, mbox->data,
815 src + size_no_wrap, (size - size_no_wrap) / 4);
816 regmap_write(dev->sram, mbox->tail, (tail + size) % mbox->size);
817
818 out:
819 mutex_unlock(&mbox->lock);
820
821 return err;
822 }
823
824 static ssize_t allegro_mbox_read(struct allegro_dev *dev,
825 struct allegro_mbox *mbox,
826 void *dst, size_t nbyte)
827 {
828 struct mcu_msg_header *header;
829 unsigned int head;
830 ssize_t size;
831 size_t body_no_wrap;
832
833 regmap_read(dev->sram, mbox->head, &head);
834 if (head > mbox->size) {
835 v4l2_err(&dev->v4l2_dev,
836 "invalid head (0x%x): must be smaller than mailbox size (0x%zx)\n",
837 head, mbox->size);
838 return -EIO;
839 }
840
841
842 regmap_bulk_read(dev->sram, mbox->data + head,
843 dst, sizeof(*header) / 4);
844 header = dst;
845 size = header->length + sizeof(*header);
846 if (size > mbox->size || size & 0x3) {
847 v4l2_err(&dev->v4l2_dev,
848 "invalid message length: %zu bytes (maximum %zu bytes)\n",
849 header->length + sizeof(*header), mbox->size);
850 return -EIO;
851 }
852 if (size > nbyte) {
853 v4l2_err(&dev->v4l2_dev,
854 "destination buffer too small: %zu bytes (need %zu bytes)\n",
855 nbyte, size);
856 return -EINVAL;
857 }
858
859
860
861
862
863
864
865
866
867
868 body_no_wrap = min((size_t)header->length,
869 (size_t)(mbox->size - (head + sizeof(*header))));
870 regmap_bulk_read(dev->sram, mbox->data + head + sizeof(*header),
871 dst + sizeof(*header), body_no_wrap / 4);
872 regmap_bulk_read(dev->sram, mbox->data,
873 dst + sizeof(*header) + body_no_wrap,
874 (header->length - body_no_wrap) / 4);
875
876 regmap_write(dev->sram, mbox->head, (head + size) % mbox->size);
877
878 v4l2_dbg(2, debug, &dev->v4l2_dev,
879 "read status message: type %s, body length %d\n",
880 msg_type_name(header->type), header->length);
881
882 return size;
883 }
884
885 static void allegro_mcu_interrupt(struct allegro_dev *dev)
886 {
887 regmap_write(dev->regmap, AL5_MCU_INTERRUPT, BIT(0));
888 }
889
890 static void allegro_mcu_send_init(struct allegro_dev *dev,
891 dma_addr_t suballoc_dma, size_t suballoc_size)
892 {
893 struct mcu_msg_init_request msg;
894
895 memset(&msg, 0, sizeof(msg));
896
897 msg.header.type = MCU_MSG_TYPE_INIT;
898 msg.header.length = sizeof(msg) - sizeof(msg.header);
899
900 msg.suballoc_dma = lower_32_bits(suballoc_dma) | MCU_CACHE_OFFSET;
901 msg.suballoc_size = suballoc_size;
902
903
904 msg.l2_cache[0] = -1;
905 msg.l2_cache[1] = -1;
906 msg.l2_cache[2] = -1;
907
908 allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
909 allegro_mcu_interrupt(dev);
910 }
911
912 static u32 v4l2_pixelformat_to_mcu_format(u32 pixelformat)
913 {
914 switch (pixelformat) {
915 case V4L2_PIX_FMT_NV12:
916
917 return 0x100 | 0x88;
918 default:
919 return -EINVAL;
920 }
921 }
922
923 static u32 v4l2_colorspace_to_mcu_colorspace(enum v4l2_colorspace colorspace)
924 {
925 switch (colorspace) {
926 case V4L2_COLORSPACE_REC709:
927 return 2;
928 case V4L2_COLORSPACE_SMPTE170M:
929 return 3;
930 case V4L2_COLORSPACE_SMPTE240M:
931 return 4;
932 case V4L2_COLORSPACE_SRGB:
933 return 7;
934 default:
935
936 return 0;
937 }
938 }
939
940 static s8 v4l2_pixelformat_to_mcu_codec(u32 pixelformat)
941 {
942 switch (pixelformat) {
943 case V4L2_PIX_FMT_H264:
944 default:
945 return 1;
946 }
947 }
948
949 static u8 v4l2_profile_to_mcu_profile(enum v4l2_mpeg_video_h264_profile profile)
950 {
951 switch (profile) {
952 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
953 default:
954 return 66;
955 }
956 }
957
958 static u16 v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level)
959 {
960 switch (level) {
961 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
962 return 10;
963 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
964 return 11;
965 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
966 return 12;
967 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
968 return 13;
969 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
970 return 20;
971 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
972 return 21;
973 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
974 return 22;
975 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
976 return 30;
977 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
978 return 31;
979 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
980 return 32;
981 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
982 return 40;
983 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
984 return 41;
985 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
986 return 42;
987 case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
988 return 50;
989 case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
990 default:
991 return 51;
992 }
993 }
994
995 static u32
996 v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode)
997 {
998 switch (mode) {
999 case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
1000 return 2;
1001 case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
1002 default:
1003 return 1;
1004 }
1005 }
1006
1007 static int allegro_mcu_send_create_channel(struct allegro_dev *dev,
1008 struct allegro_channel *channel)
1009 {
1010 struct mcu_msg_create_channel msg;
1011
1012 memset(&msg, 0, sizeof(msg));
1013
1014 msg.header.type = MCU_MSG_TYPE_CREATE_CHANNEL;
1015 msg.header.length = sizeof(msg) - sizeof(msg.header);
1016
1017 msg.user_id = channel->user_id;
1018 msg.width = channel->width;
1019 msg.height = channel->height;
1020 msg.format = v4l2_pixelformat_to_mcu_format(channel->pixelformat);
1021 msg.colorspace = v4l2_colorspace_to_mcu_colorspace(channel->colorspace);
1022 msg.src_mode = 0x0;
1023 msg.profile = v4l2_profile_to_mcu_profile(channel->profile);
1024 msg.constraint_set_flags = BIT(1);
1025 msg.codec = v4l2_pixelformat_to_mcu_codec(channel->codec);
1026 msg.level = v4l2_level_to_mcu_level(channel->level);
1027 msg.tier = 0;
1028 msg.sps_param = BIT(20) | 0x4a;
1029 msg.pps_param = BIT(2);
1030 msg.enc_option = AL_OPT_RDO_COST_MODE | AL_OPT_LF_X_TILE |
1031 AL_OPT_LF_X_SLICE | AL_OPT_LF;
1032 msg.beta_offset = -1;
1033 msg.tc_offset = -1;
1034 msg.num_slices = 1;
1035 msg.me_range[0] = 8;
1036 msg.me_range[1] = 8;
1037 msg.me_range[2] = 16;
1038 msg.me_range[3] = 16;
1039 msg.max_cu_size = ilog2(SIZE_MACROBLOCK);
1040 msg.min_cu_size = ilog2(8);
1041 msg.max_tu_size = 2;
1042 msg.min_tu_size = 2;
1043 msg.max_transfo_depth_intra = 1;
1044 msg.max_transfo_depth_inter = 1;
1045
1046 msg.rate_control_mode =
1047 v4l2_bitrate_mode_to_mcu_mode(channel->bitrate_mode);
1048
1049 msg.initial_rem_delay =
1050 ((channel->cpb_size * 1000) / channel->bitrate_peak) * 90000;
1051
1052 msg.cpb_size =
1053 ((channel->cpb_size * 1000) / channel->bitrate_peak) * 90000;
1054 msg.framerate = 25;
1055 msg.clk_ratio = 1000;
1056 msg.target_bitrate = channel->bitrate;
1057 msg.max_bitrate = channel->bitrate_peak;
1058 msg.initial_qp = 25;
1059 msg.min_qp = 10;
1060 msg.max_qp = 51;
1061 msg.ip_delta = -1;
1062 msg.pb_delta = -1;
1063 msg.golden_ref = 0;
1064 msg.golden_delta = 2;
1065 msg.golden_ref_frequency = 10;
1066 msg.rate_control_option = 0x00000000;
1067
1068 msg.gop_ctrl_mode = 0x00000000;
1069 msg.freq_ird = 0x7fffffff;
1070 msg.freq_lt = 0;
1071 msg.gdr_mode = 0x00000000;
1072 msg.gop_length = channel->gop_size;
1073 msg.subframe_latency = 0x00000000;
1074 msg.lda_control_mode = 0x700d0000;
1075
1076 allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
1077 allegro_mcu_interrupt(dev);
1078
1079 return 0;
1080 }
1081
1082 static int allegro_mcu_send_destroy_channel(struct allegro_dev *dev,
1083 struct allegro_channel *channel)
1084 {
1085 struct mcu_msg_destroy_channel msg;
1086
1087 memset(&msg, 0, sizeof(msg));
1088
1089 msg.header.type = MCU_MSG_TYPE_DESTROY_CHANNEL;
1090 msg.header.length = sizeof(msg) - sizeof(msg.header);
1091
1092 msg.channel_id = channel->mcu_channel_id;
1093
1094 allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
1095 allegro_mcu_interrupt(dev);
1096
1097 return 0;
1098 }
1099
1100 static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev,
1101 struct allegro_channel *channel,
1102 dma_addr_t paddr,
1103 unsigned long size)
1104 {
1105 struct mcu_msg_put_stream_buffer msg;
1106
1107 memset(&msg, 0, sizeof(msg));
1108
1109 msg.header.type = MCU_MSG_TYPE_PUT_STREAM_BUFFER;
1110 msg.header.length = sizeof(msg) - sizeof(msg.header);
1111
1112 msg.channel_id = channel->mcu_channel_id;
1113 msg.dma_addr = paddr;
1114 msg.mcu_addr = paddr | MCU_CACHE_OFFSET;
1115 msg.size = size;
1116 msg.offset = ENCODER_STREAM_OFFSET;
1117 msg.stream_id = 0;
1118
1119 allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
1120 allegro_mcu_interrupt(dev);
1121
1122 return 0;
1123 }
1124
1125 static int allegro_mcu_send_encode_frame(struct allegro_dev *dev,
1126 struct allegro_channel *channel,
1127 dma_addr_t src_y, dma_addr_t src_uv)
1128 {
1129 struct mcu_msg_encode_frame msg;
1130
1131 memset(&msg, 0, sizeof(msg));
1132
1133 msg.header.type = MCU_MSG_TYPE_ENCODE_FRAME;
1134 msg.header.length = sizeof(msg) - sizeof(msg.header);
1135
1136 msg.channel_id = channel->mcu_channel_id;
1137 msg.encoding_options = AL_OPT_FORCE_LOAD;
1138 msg.pps_qp = 26;
1139 msg.user_param = 0;
1140 msg.src_handle = 0;
1141 msg.src_y = src_y;
1142 msg.src_uv = src_uv;
1143 msg.stride = channel->stride;
1144 msg.ep2 = 0x0;
1145 msg.ep2_v = msg.ep2 | MCU_CACHE_OFFSET;
1146
1147 allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
1148 allegro_mcu_interrupt(dev);
1149
1150 return 0;
1151 }
1152
1153 static int allegro_mcu_wait_for_init_timeout(struct allegro_dev *dev,
1154 unsigned long timeout_ms)
1155 {
1156 unsigned long tmo;
1157
1158 tmo = wait_for_completion_timeout(&dev->init_complete,
1159 msecs_to_jiffies(timeout_ms));
1160 if (tmo == 0)
1161 return -ETIMEDOUT;
1162
1163 reinit_completion(&dev->init_complete);
1164 return 0;
1165 }
1166
1167 static int allegro_mcu_push_buffer_internal(struct allegro_channel *channel,
1168 enum mcu_msg_type type)
1169 {
1170 struct allegro_dev *dev = channel->dev;
1171 struct mcu_msg_push_buffers_internal *msg;
1172 struct mcu_msg_push_buffers_internal_buffer *buffer;
1173 unsigned int num_buffers = 0;
1174 size_t size;
1175 struct allegro_buffer *al_buffer;
1176 struct list_head *list;
1177 int err;
1178
1179 switch (type) {
1180 case MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE:
1181 list = &channel->buffers_reference;
1182 break;
1183 case MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE:
1184 list = &channel->buffers_intermediate;
1185 break;
1186 default:
1187 return -EINVAL;
1188 }
1189
1190 list_for_each_entry(al_buffer, list, head)
1191 num_buffers++;
1192 size = struct_size(msg, buffer, num_buffers);
1193
1194 msg = kmalloc(size, GFP_KERNEL);
1195 if (!msg)
1196 return -ENOMEM;
1197
1198 msg->header.length = size - sizeof(msg->header);
1199 msg->header.type = type;
1200 msg->channel_id = channel->mcu_channel_id;
1201
1202 buffer = msg->buffer;
1203 list_for_each_entry(al_buffer, list, head) {
1204 buffer->dma_addr = lower_32_bits(al_buffer->paddr);
1205 buffer->mcu_addr =
1206 lower_32_bits(al_buffer->paddr) | MCU_CACHE_OFFSET;
1207 buffer->size = al_buffer->size;
1208 buffer++;
1209 }
1210
1211 err = allegro_mbox_write(dev, &dev->mbox_command, msg, size);
1212 if (err)
1213 goto out;
1214 allegro_mcu_interrupt(dev);
1215
1216 out:
1217 kfree(msg);
1218 return err;
1219 }
1220
1221 static int allegro_mcu_push_buffer_intermediate(struct allegro_channel *channel)
1222 {
1223 enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE;
1224
1225 return allegro_mcu_push_buffer_internal(channel, type);
1226 }
1227
1228 static int allegro_mcu_push_buffer_reference(struct allegro_channel *channel)
1229 {
1230 enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE;
1231
1232 return allegro_mcu_push_buffer_internal(channel, type);
1233 }
1234
1235 static int allocate_buffers_internal(struct allegro_channel *channel,
1236 struct list_head *list,
1237 size_t n, size_t size)
1238 {
1239 struct allegro_dev *dev = channel->dev;
1240 unsigned int i;
1241 int err;
1242 struct allegro_buffer *buffer, *tmp;
1243
1244 for (i = 0; i < n; i++) {
1245 buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
1246 if (!buffer) {
1247 err = -ENOMEM;
1248 goto err;
1249 }
1250 INIT_LIST_HEAD(&buffer->head);
1251
1252 err = allegro_alloc_buffer(dev, buffer, size);
1253 if (err)
1254 goto err;
1255 list_add(&buffer->head, list);
1256 }
1257
1258 return 0;
1259
1260 err:
1261 list_for_each_entry_safe(buffer, tmp, list, head) {
1262 list_del(&buffer->head);
1263 allegro_free_buffer(dev, buffer);
1264 kfree(buffer);
1265 }
1266 return err;
1267 }
1268
1269 static void destroy_buffers_internal(struct allegro_channel *channel,
1270 struct list_head *list)
1271 {
1272 struct allegro_dev *dev = channel->dev;
1273 struct allegro_buffer *buffer, *tmp;
1274
1275 list_for_each_entry_safe(buffer, tmp, list, head) {
1276 list_del(&buffer->head);
1277 allegro_free_buffer(dev, buffer);
1278 kfree(buffer);
1279 }
1280 }
1281
1282 static void destroy_reference_buffers(struct allegro_channel *channel)
1283 {
1284 return destroy_buffers_internal(channel, &channel->buffers_reference);
1285 }
1286
1287 static void destroy_intermediate_buffers(struct allegro_channel *channel)
1288 {
1289 return destroy_buffers_internal(channel,
1290 &channel->buffers_intermediate);
1291 }
1292
1293 static int allocate_intermediate_buffers(struct allegro_channel *channel,
1294 size_t n, size_t size)
1295 {
1296 return allocate_buffers_internal(channel,
1297 &channel->buffers_intermediate,
1298 n, size);
1299 }
1300
1301 static int allocate_reference_buffers(struct allegro_channel *channel,
1302 size_t n, size_t size)
1303 {
1304 return allocate_buffers_internal(channel,
1305 &channel->buffers_reference,
1306 n, PAGE_ALIGN(size));
1307 }
1308
1309 static ssize_t allegro_h264_write_sps(struct allegro_channel *channel,
1310 void *dest, size_t n)
1311 {
1312 struct allegro_dev *dev = channel->dev;
1313 struct nal_h264_sps *sps;
1314 ssize_t size;
1315 unsigned int size_mb = SIZE_MACROBLOCK;
1316
1317 unsigned int crop_unit_x = 2;
1318 unsigned int crop_unit_y = 2;
1319
1320 sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1321 if (!sps)
1322 return -ENOMEM;
1323
1324 sps->profile_idc = nal_h264_profile_from_v4l2(channel->profile);
1325 sps->constraint_set0_flag = 0;
1326 sps->constraint_set1_flag = 1;
1327 sps->constraint_set2_flag = 0;
1328 sps->constraint_set3_flag = 0;
1329 sps->constraint_set4_flag = 0;
1330 sps->constraint_set5_flag = 0;
1331 sps->level_idc = nal_h264_level_from_v4l2(channel->level);
1332 sps->seq_parameter_set_id = 0;
1333 sps->log2_max_frame_num_minus4 = 0;
1334 sps->pic_order_cnt_type = 0;
1335 sps->log2_max_pic_order_cnt_lsb_minus4 = 6;
1336 sps->max_num_ref_frames = 3;
1337 sps->gaps_in_frame_num_value_allowed_flag = 0;
1338 sps->pic_width_in_mbs_minus1 =
1339 DIV_ROUND_UP(channel->width, size_mb) - 1;
1340 sps->pic_height_in_map_units_minus1 =
1341 DIV_ROUND_UP(channel->height, size_mb) - 1;
1342 sps->frame_mbs_only_flag = 1;
1343 sps->mb_adaptive_frame_field_flag = 0;
1344 sps->direct_8x8_inference_flag = 1;
1345 sps->frame_cropping_flag =
1346 (channel->width % size_mb) || (channel->height % size_mb);
1347 if (sps->frame_cropping_flag) {
1348 sps->crop_left = 0;
1349 sps->crop_right = (round_up(channel->width, size_mb) - channel->width) / crop_unit_x;
1350 sps->crop_top = 0;
1351 sps->crop_bottom = (round_up(channel->height, size_mb) - channel->height) / crop_unit_y;
1352 }
1353 sps->vui_parameters_present_flag = 1;
1354 sps->vui.aspect_ratio_info_present_flag = 0;
1355 sps->vui.overscan_info_present_flag = 0;
1356 sps->vui.video_signal_type_present_flag = 1;
1357 sps->vui.video_format = 1;
1358 sps->vui.video_full_range_flag = 0;
1359 sps->vui.colour_description_present_flag = 1;
1360 sps->vui.colour_primaries = 5;
1361 sps->vui.transfer_characteristics = 5;
1362 sps->vui.matrix_coefficients = 5;
1363 sps->vui.chroma_loc_info_present_flag = 1;
1364 sps->vui.chroma_sample_loc_type_top_field = 0;
1365 sps->vui.chroma_sample_loc_type_bottom_field = 0;
1366 sps->vui.timing_info_present_flag = 1;
1367 sps->vui.num_units_in_tick = 1;
1368 sps->vui.time_scale = 50;
1369 sps->vui.fixed_frame_rate_flag = 1;
1370 sps->vui.nal_hrd_parameters_present_flag = 0;
1371 sps->vui.vcl_hrd_parameters_present_flag = 1;
1372 sps->vui.vcl_hrd_parameters.cpb_cnt_minus1 = 0;
1373 sps->vui.vcl_hrd_parameters.bit_rate_scale = 0;
1374 sps->vui.vcl_hrd_parameters.cpb_size_scale = 1;
1375
1376 sps->vui.vcl_hrd_parameters.bit_rate_value_minus1[0] =
1377 channel->bitrate_peak / (1 << (6 + sps->vui.vcl_hrd_parameters.bit_rate_scale)) - 1;
1378
1379 sps->vui.vcl_hrd_parameters.cpb_size_value_minus1[0] =
1380 (channel->cpb_size * 1000) / (1 << (4 + sps->vui.vcl_hrd_parameters.cpb_size_scale)) - 1;
1381 sps->vui.vcl_hrd_parameters.cbr_flag[0] = 1;
1382 sps->vui.vcl_hrd_parameters.initial_cpb_removal_delay_length_minus1 = 31;
1383 sps->vui.vcl_hrd_parameters.cpb_removal_delay_length_minus1 = 31;
1384 sps->vui.vcl_hrd_parameters.dpb_output_delay_length_minus1 = 31;
1385 sps->vui.vcl_hrd_parameters.time_offset_length = 0;
1386 sps->vui.low_delay_hrd_flag = 0;
1387 sps->vui.pic_struct_present_flag = 1;
1388 sps->vui.bitstream_restriction_flag = 0;
1389
1390 size = nal_h264_write_sps(&dev->plat_dev->dev, dest, n, sps);
1391
1392 kfree(sps);
1393
1394 return size;
1395 }
1396
1397 static ssize_t allegro_h264_write_pps(struct allegro_channel *channel,
1398 void *dest, size_t n)
1399 {
1400 struct allegro_dev *dev = channel->dev;
1401 struct nal_h264_pps *pps;
1402 ssize_t size;
1403
1404 pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1405 if (!pps)
1406 return -ENOMEM;
1407
1408 pps->pic_parameter_set_id = 0;
1409 pps->seq_parameter_set_id = 0;
1410 pps->entropy_coding_mode_flag = 0;
1411 pps->bottom_field_pic_order_in_frame_present_flag = 0;
1412 pps->num_slice_groups_minus1 = 0;
1413 pps->num_ref_idx_l0_default_active_minus1 = 2;
1414 pps->num_ref_idx_l1_default_active_minus1 = 2;
1415 pps->weighted_pred_flag = 0;
1416 pps->weighted_bipred_idc = 0;
1417 pps->pic_init_qp_minus26 = 0;
1418 pps->pic_init_qs_minus26 = 0;
1419 pps->chroma_qp_index_offset = 0;
1420 pps->deblocking_filter_control_present_flag = 1;
1421 pps->constrained_intra_pred_flag = 0;
1422 pps->redundant_pic_cnt_present_flag = 0;
1423 pps->transform_8x8_mode_flag = 0;
1424 pps->pic_scaling_matrix_present_flag = 0;
1425 pps->second_chroma_qp_index_offset = 0;
1426
1427 size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps);
1428
1429 kfree(pps);
1430
1431 return size;
1432 }
1433
1434 static bool allegro_channel_is_at_eos(struct allegro_channel *channel)
1435 {
1436 bool is_at_eos = false;
1437
1438 switch (allegro_get_state(channel)) {
1439 case ALLEGRO_STATE_STOPPED:
1440 is_at_eos = true;
1441 break;
1442 case ALLEGRO_STATE_DRAIN:
1443 case ALLEGRO_STATE_WAIT_FOR_BUFFER:
1444 if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) == 0)
1445 is_at_eos = true;
1446 break;
1447 default:
1448 break;
1449 }
1450
1451 return is_at_eos;
1452 }
1453
1454 static void allegro_channel_buf_done(struct allegro_channel *channel,
1455 struct vb2_v4l2_buffer *buf,
1456 enum vb2_buffer_state state)
1457 {
1458 const struct v4l2_event eos_event = {
1459 .type = V4L2_EVENT_EOS
1460 };
1461
1462 if (allegro_channel_is_at_eos(channel)) {
1463 buf->flags |= V4L2_BUF_FLAG_LAST;
1464 v4l2_event_queue_fh(&channel->fh, &eos_event);
1465
1466 allegro_set_state(channel, ALLEGRO_STATE_STOPPED);
1467 }
1468
1469 v4l2_m2m_buf_done(buf, state);
1470 }
1471
1472 static void allegro_channel_finish_frame(struct allegro_channel *channel,
1473 struct mcu_msg_encode_frame_response *msg)
1474 {
1475 struct allegro_dev *dev = channel->dev;
1476 struct vb2_v4l2_buffer *src_buf;
1477 struct vb2_v4l2_buffer *dst_buf;
1478 struct {
1479 u32 offset;
1480 u32 size;
1481 } *partition;
1482 enum vb2_buffer_state state = VB2_BUF_STATE_ERROR;
1483 char *curr;
1484 ssize_t len;
1485 ssize_t free;
1486
1487 src_buf = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx);
1488
1489 dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
1490 dst_buf->sequence = channel->csequence++;
1491
1492 if (msg->error_code) {
1493 v4l2_err(&dev->v4l2_dev,
1494 "channel %d: error while encoding frame: %x\n",
1495 channel->mcu_channel_id, msg->error_code);
1496 goto err;
1497 }
1498
1499 if (msg->partition_table_size != 1) {
1500 v4l2_warn(&dev->v4l2_dev,
1501 "channel %d: only handling first partition table entry (%d entries)\n",
1502 channel->mcu_channel_id, msg->partition_table_size);
1503 }
1504
1505 if (msg->partition_table_offset +
1506 msg->partition_table_size * sizeof(*partition) >
1507 vb2_plane_size(&dst_buf->vb2_buf, 0)) {
1508 v4l2_err(&dev->v4l2_dev,
1509 "channel %d: partition table outside of dst_buf\n",
1510 channel->mcu_channel_id);
1511 goto err;
1512 }
1513
1514 partition =
1515 vb2_plane_vaddr(&dst_buf->vb2_buf, 0) + msg->partition_table_offset;
1516 if (partition->offset + partition->size >
1517 vb2_plane_size(&dst_buf->vb2_buf, 0)) {
1518 v4l2_err(&dev->v4l2_dev,
1519 "channel %d: encoded frame is outside of dst_buf (offset 0x%x, size 0x%x)\n",
1520 channel->mcu_channel_id, partition->offset,
1521 partition->size);
1522 goto err;
1523 }
1524
1525 v4l2_dbg(2, debug, &dev->v4l2_dev,
1526 "channel %d: encoded frame of size %d is at offset 0x%x\n",
1527 channel->mcu_channel_id, partition->size, partition->offset);
1528
1529
1530
1531
1532
1533 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
1534 partition->offset + partition->size);
1535
1536 curr = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
1537 free = partition->offset;
1538 if (msg->is_idr) {
1539 len = allegro_h264_write_sps(channel, curr, free);
1540 if (len < 0) {
1541 v4l2_err(&dev->v4l2_dev,
1542 "not enough space for sequence parameter set: %zd left\n",
1543 free);
1544 goto err;
1545 }
1546 curr += len;
1547 free -= len;
1548 v4l2_dbg(1, debug, &dev->v4l2_dev,
1549 "channel %d: wrote %zd byte SPS nal unit\n",
1550 channel->mcu_channel_id, len);
1551 }
1552
1553 if (msg->slice_type == AL_ENC_SLICE_TYPE_I) {
1554 len = allegro_h264_write_pps(channel, curr, free);
1555 if (len < 0) {
1556 v4l2_err(&dev->v4l2_dev,
1557 "not enough space for picture parameter set: %zd left\n",
1558 free);
1559 goto err;
1560 }
1561 curr += len;
1562 free -= len;
1563 v4l2_dbg(1, debug, &dev->v4l2_dev,
1564 "channel %d: wrote %zd byte PPS nal unit\n",
1565 channel->mcu_channel_id, len);
1566 }
1567
1568 len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free);
1569 if (len < 0) {
1570 v4l2_err(&dev->v4l2_dev,
1571 "failed to write %zd filler data\n", free);
1572 goto err;
1573 }
1574 curr += len;
1575 free -= len;
1576 v4l2_dbg(2, debug, &dev->v4l2_dev,
1577 "channel %d: wrote %zd bytes filler nal unit\n",
1578 channel->mcu_channel_id, len);
1579
1580 if (free != 0) {
1581 v4l2_err(&dev->v4l2_dev,
1582 "non-VCL NAL units do not fill space until VCL NAL unit: %zd bytes left\n",
1583 free);
1584 goto err;
1585 }
1586
1587 state = VB2_BUF_STATE_DONE;
1588
1589 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, false);
1590 if (msg->is_idr)
1591 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1592 else
1593 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1594
1595 v4l2_dbg(1, debug, &dev->v4l2_dev,
1596 "channel %d: encoded frame #%03d (%s%s, %d bytes)\n",
1597 channel->mcu_channel_id,
1598 dst_buf->sequence,
1599 msg->is_idr ? "IDR, " : "",
1600 msg->slice_type == AL_ENC_SLICE_TYPE_I ? "I slice" :
1601 msg->slice_type == AL_ENC_SLICE_TYPE_P ? "P slice" : "unknown",
1602 partition->size);
1603
1604 err:
1605 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1606
1607 allegro_channel_buf_done(channel, dst_buf, state);
1608
1609 v4l2_m2m_job_finish(dev->m2m_dev, channel->fh.m2m_ctx);
1610 }
1611
1612 static int allegro_handle_init(struct allegro_dev *dev,
1613 struct mcu_msg_init_response *msg)
1614 {
1615 complete(&dev->init_complete);
1616
1617 return 0;
1618 }
1619
1620 static int
1621 allegro_handle_create_channel(struct allegro_dev *dev,
1622 struct mcu_msg_create_channel_response *msg)
1623 {
1624 struct allegro_channel *channel;
1625 int err = 0;
1626
1627 channel = allegro_find_channel_by_user_id(dev, msg->user_id);
1628 if (IS_ERR(channel)) {
1629 v4l2_warn(&dev->v4l2_dev,
1630 "received %s for unknown user %d\n",
1631 msg_type_name(msg->header.type),
1632 msg->user_id);
1633 return -EINVAL;
1634 }
1635
1636 if (msg->error_code) {
1637 v4l2_err(&dev->v4l2_dev,
1638 "user %d: mcu failed to create channel: error %x\n",
1639 channel->user_id, msg->error_code);
1640 err = -EIO;
1641 goto out;
1642 }
1643
1644 channel->mcu_channel_id = msg->channel_id;
1645 v4l2_dbg(1, debug, &dev->v4l2_dev,
1646 "user %d: channel has channel id %d\n",
1647 channel->user_id, channel->mcu_channel_id);
1648
1649 v4l2_dbg(1, debug, &dev->v4l2_dev,
1650 "channel %d: intermediate buffers: %d x %d bytes\n",
1651 channel->mcu_channel_id,
1652 msg->int_buffers_count, msg->int_buffers_size);
1653 err = allocate_intermediate_buffers(channel, msg->int_buffers_count,
1654 msg->int_buffers_size);
1655 if (err) {
1656 v4l2_err(&dev->v4l2_dev,
1657 "channel %d: failed to allocate intermediate buffers\n",
1658 channel->mcu_channel_id);
1659 goto out;
1660 }
1661 err = allegro_mcu_push_buffer_intermediate(channel);
1662 if (err)
1663 goto out;
1664
1665 v4l2_dbg(1, debug, &dev->v4l2_dev,
1666 "channel %d: reference buffers: %d x %d bytes\n",
1667 channel->mcu_channel_id,
1668 msg->rec_buffers_count, msg->rec_buffers_size);
1669 err = allocate_reference_buffers(channel, msg->rec_buffers_count,
1670 msg->rec_buffers_size);
1671 if (err) {
1672 v4l2_err(&dev->v4l2_dev,
1673 "channel %d: failed to allocate reference buffers\n",
1674 channel->mcu_channel_id);
1675 goto out;
1676 }
1677 err = allegro_mcu_push_buffer_reference(channel);
1678 if (err)
1679 goto out;
1680
1681 out:
1682 channel->error = err;
1683 complete(&channel->completion);
1684
1685
1686 return 0;
1687 }
1688
1689 static int
1690 allegro_handle_destroy_channel(struct allegro_dev *dev,
1691 struct mcu_msg_destroy_channel_response *msg)
1692 {
1693 struct allegro_channel *channel;
1694
1695 channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
1696 if (IS_ERR(channel)) {
1697 v4l2_err(&dev->v4l2_dev,
1698 "received %s for unknown channel %d\n",
1699 msg_type_name(msg->header.type),
1700 msg->channel_id);
1701 return -EINVAL;
1702 }
1703
1704 v4l2_dbg(2, debug, &dev->v4l2_dev,
1705 "user %d: vcu destroyed channel %d\n",
1706 channel->user_id, channel->mcu_channel_id);
1707 complete(&channel->completion);
1708
1709 return 0;
1710 }
1711
1712 static int
1713 allegro_handle_encode_frame(struct allegro_dev *dev,
1714 struct mcu_msg_encode_frame_response *msg)
1715 {
1716 struct allegro_channel *channel;
1717
1718 channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
1719 if (IS_ERR(channel)) {
1720 v4l2_err(&dev->v4l2_dev,
1721 "received %s for unknown channel %d\n",
1722 msg_type_name(msg->header.type),
1723 msg->channel_id);
1724 return -EINVAL;
1725 }
1726
1727 allegro_channel_finish_frame(channel, msg);
1728
1729 return 0;
1730 }
1731
1732 static int allegro_receive_message(struct allegro_dev *dev)
1733 {
1734 union mcu_msg_response *msg;
1735 ssize_t size;
1736 int err = 0;
1737
1738 msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1739 if (!msg)
1740 return -ENOMEM;
1741
1742 size = allegro_mbox_read(dev, &dev->mbox_status, msg, sizeof(*msg));
1743 if (size < sizeof(msg->header)) {
1744 v4l2_err(&dev->v4l2_dev,
1745 "invalid mbox message (%zd): must be at least %zu\n",
1746 size, sizeof(msg->header));
1747 err = -EINVAL;
1748 goto out;
1749 }
1750
1751 switch (msg->header.type) {
1752 case MCU_MSG_TYPE_INIT:
1753 err = allegro_handle_init(dev, &msg->init);
1754 break;
1755 case MCU_MSG_TYPE_CREATE_CHANNEL:
1756 err = allegro_handle_create_channel(dev, &msg->create_channel);
1757 break;
1758 case MCU_MSG_TYPE_DESTROY_CHANNEL:
1759 err = allegro_handle_destroy_channel(dev,
1760 &msg->destroy_channel);
1761 break;
1762 case MCU_MSG_TYPE_ENCODE_FRAME:
1763 err = allegro_handle_encode_frame(dev, &msg->encode_frame);
1764 break;
1765 default:
1766 v4l2_warn(&dev->v4l2_dev,
1767 "%s: unknown message %s\n",
1768 __func__, msg_type_name(msg->header.type));
1769 err = -EINVAL;
1770 break;
1771 }
1772
1773 out:
1774 kfree(msg);
1775
1776 return err;
1777 }
1778
1779 static irqreturn_t allegro_hardirq(int irq, void *data)
1780 {
1781 struct allegro_dev *dev = data;
1782 unsigned int status;
1783
1784 regmap_read(dev->regmap, AL5_ITC_CPU_IRQ_STA, &status);
1785 if (!(status & AL5_ITC_CPU_IRQ_STA_TRIGGERED))
1786 return IRQ_NONE;
1787
1788 regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_CLR, status);
1789
1790 return IRQ_WAKE_THREAD;
1791 }
1792
1793 static irqreturn_t allegro_irq_thread(int irq, void *data)
1794 {
1795 struct allegro_dev *dev = data;
1796
1797 allegro_receive_message(dev);
1798
1799 return IRQ_HANDLED;
1800 }
1801
1802 static void allegro_copy_firmware(struct allegro_dev *dev,
1803 const u8 * const buf, size_t size)
1804 {
1805 int err = 0;
1806
1807 v4l2_dbg(1, debug, &dev->v4l2_dev,
1808 "copy mcu firmware (%zu B) to SRAM\n", size);
1809 err = regmap_bulk_write(dev->sram, 0x0, buf, size / 4);
1810 if (err)
1811 v4l2_err(&dev->v4l2_dev,
1812 "failed to copy firmware: %d\n", err);
1813 }
1814
1815 static void allegro_copy_fw_codec(struct allegro_dev *dev,
1816 const u8 * const buf, size_t size)
1817 {
1818 int err;
1819 dma_addr_t icache_offset, dcache_offset;
1820
1821
1822
1823
1824
1825
1826
1827 err = allegro_alloc_buffer(dev, &dev->firmware, size);
1828 if (err) {
1829 v4l2_err(&dev->v4l2_dev,
1830 "failed to allocate %zu bytes for firmware\n", size);
1831 return;
1832 }
1833
1834 v4l2_dbg(1, debug, &dev->v4l2_dev,
1835 "copy codec firmware (%zd B) to phys %pad\n",
1836 size, &dev->firmware.paddr);
1837 memcpy(dev->firmware.vaddr, buf, size);
1838
1839 regmap_write(dev->regmap, AXI_ADDR_OFFSET_IP,
1840 upper_32_bits(dev->firmware.paddr));
1841
1842 icache_offset = dev->firmware.paddr - MCU_CACHE_OFFSET;
1843 v4l2_dbg(2, debug, &dev->v4l2_dev,
1844 "icache_offset: msb = 0x%x, lsb = 0x%x\n",
1845 upper_32_bits(icache_offset), lower_32_bits(icache_offset));
1846 regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_MSB,
1847 upper_32_bits(icache_offset));
1848 regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_LSB,
1849 lower_32_bits(icache_offset));
1850
1851 dcache_offset =
1852 (dev->firmware.paddr & 0xffffffff00000000ULL) - MCU_CACHE_OFFSET;
1853 v4l2_dbg(2, debug, &dev->v4l2_dev,
1854 "dcache_offset: msb = 0x%x, lsb = 0x%x\n",
1855 upper_32_bits(dcache_offset), lower_32_bits(dcache_offset));
1856 regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_MSB,
1857 upper_32_bits(dcache_offset));
1858 regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_LSB,
1859 lower_32_bits(dcache_offset));
1860 }
1861
1862 static void allegro_free_fw_codec(struct allegro_dev *dev)
1863 {
1864 allegro_free_buffer(dev, &dev->firmware);
1865 }
1866
1867
1868
1869
1870
1871 static int allegro_mcu_enable_interrupts(struct allegro_dev *dev)
1872 {
1873 return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, BIT(0));
1874 }
1875
1876 static int allegro_mcu_disable_interrupts(struct allegro_dev *dev)
1877 {
1878 return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, 0);
1879 }
1880
1881 static int allegro_mcu_wait_for_sleep(struct allegro_dev *dev)
1882 {
1883 unsigned long timeout;
1884 unsigned int status;
1885
1886 timeout = jiffies + msecs_to_jiffies(100);
1887 while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
1888 status != AL5_MCU_STA_SLEEP) {
1889 if (time_after(jiffies, timeout))
1890 return -ETIMEDOUT;
1891 cpu_relax();
1892 }
1893
1894 return 0;
1895 }
1896
1897 static int allegro_mcu_start(struct allegro_dev *dev)
1898 {
1899 unsigned long timeout;
1900 unsigned int status;
1901 int err;
1902
1903 err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, BIT(0));
1904 if (err)
1905 return err;
1906
1907 timeout = jiffies + msecs_to_jiffies(100);
1908 while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
1909 status == AL5_MCU_STA_SLEEP) {
1910 if (time_after(jiffies, timeout))
1911 return -ETIMEDOUT;
1912 cpu_relax();
1913 }
1914
1915 err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
1916 if (err)
1917 return err;
1918
1919 return 0;
1920 }
1921
1922 static int allegro_mcu_reset(struct allegro_dev *dev)
1923 {
1924 int err;
1925
1926 err = regmap_write(dev->regmap,
1927 AL5_MCU_RESET_MODE, AL5_MCU_RESET_MODE_SLEEP);
1928 if (err < 0)
1929 return err;
1930
1931 err = regmap_write(dev->regmap, AL5_MCU_RESET, AL5_MCU_RESET_SOFT);
1932 if (err < 0)
1933 return err;
1934
1935 return allegro_mcu_wait_for_sleep(dev);
1936 }
1937
1938 static void allegro_destroy_channel(struct allegro_channel *channel)
1939 {
1940 struct allegro_dev *dev = channel->dev;
1941 unsigned long timeout;
1942
1943 if (channel_exists(channel)) {
1944 reinit_completion(&channel->completion);
1945 allegro_mcu_send_destroy_channel(dev, channel);
1946 timeout = wait_for_completion_timeout(&channel->completion,
1947 msecs_to_jiffies(5000));
1948 if (timeout == 0)
1949 v4l2_warn(&dev->v4l2_dev,
1950 "channel %d: timeout while destroying\n",
1951 channel->mcu_channel_id);
1952
1953 channel->mcu_channel_id = -1;
1954 }
1955
1956 destroy_intermediate_buffers(channel);
1957 destroy_reference_buffers(channel);
1958
1959 v4l2_ctrl_grab(channel->mpeg_video_h264_profile, false);
1960 v4l2_ctrl_grab(channel->mpeg_video_h264_level, false);
1961 v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, false);
1962 v4l2_ctrl_grab(channel->mpeg_video_bitrate, false);
1963 v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, false);
1964 v4l2_ctrl_grab(channel->mpeg_video_cpb_size, false);
1965 v4l2_ctrl_grab(channel->mpeg_video_gop_size, false);
1966
1967 if (channel->user_id != -1) {
1968 clear_bit(channel->user_id, &dev->channel_user_ids);
1969 channel->user_id = -1;
1970 }
1971 }
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983 static int allegro_create_channel(struct allegro_channel *channel)
1984 {
1985 struct allegro_dev *dev = channel->dev;
1986 unsigned long timeout;
1987 enum v4l2_mpeg_video_h264_level min_level;
1988
1989 if (channel_exists(channel)) {
1990 v4l2_warn(&dev->v4l2_dev,
1991 "channel already exists\n");
1992 return 0;
1993 }
1994
1995 channel->user_id = allegro_next_user_id(dev);
1996 if (channel->user_id < 0) {
1997 v4l2_err(&dev->v4l2_dev,
1998 "no free channels available\n");
1999 return -EBUSY;
2000 }
2001 set_bit(channel->user_id, &dev->channel_user_ids);
2002
2003 v4l2_dbg(1, debug, &dev->v4l2_dev,
2004 "user %d: creating channel (%4.4s, %dx%d@%d)\n",
2005 channel->user_id,
2006 (char *)&channel->codec, channel->width, channel->height, 25);
2007
2008 min_level = select_minimum_h264_level(channel->width, channel->height);
2009 if (channel->level < min_level) {
2010 v4l2_warn(&dev->v4l2_dev,
2011 "user %d: selected Level %s too low: increasing to Level %s\n",
2012 channel->user_id,
2013 v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[channel->level],
2014 v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[min_level]);
2015 channel->level = min_level;
2016 }
2017
2018 v4l2_ctrl_grab(channel->mpeg_video_h264_profile, true);
2019 v4l2_ctrl_grab(channel->mpeg_video_h264_level, true);
2020 v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, true);
2021 v4l2_ctrl_grab(channel->mpeg_video_bitrate, true);
2022 v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, true);
2023 v4l2_ctrl_grab(channel->mpeg_video_cpb_size, true);
2024 v4l2_ctrl_grab(channel->mpeg_video_gop_size, true);
2025
2026 reinit_completion(&channel->completion);
2027 allegro_mcu_send_create_channel(dev, channel);
2028 timeout = wait_for_completion_timeout(&channel->completion,
2029 msecs_to_jiffies(5000));
2030 if (timeout == 0)
2031 channel->error = -ETIMEDOUT;
2032 if (channel->error)
2033 goto err;
2034
2035 v4l2_dbg(1, debug, &dev->v4l2_dev,
2036 "channel %d: accepting buffers\n",
2037 channel->mcu_channel_id);
2038
2039 return 0;
2040
2041 err:
2042 allegro_destroy_channel(channel);
2043
2044 return channel->error;
2045 }
2046
2047 static void allegro_set_default_params(struct allegro_channel *channel)
2048 {
2049 channel->width = ALLEGRO_WIDTH_DEFAULT;
2050 channel->height = ALLEGRO_HEIGHT_DEFAULT;
2051 channel->stride = round_up(channel->width, 32);
2052
2053 channel->colorspace = V4L2_COLORSPACE_REC709;
2054 channel->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2055 channel->quantization = V4L2_QUANTIZATION_DEFAULT;
2056 channel->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2057
2058 channel->pixelformat = V4L2_PIX_FMT_NV12;
2059 channel->sizeimage_raw = channel->stride * channel->height * 3 / 2;
2060
2061 channel->codec = V4L2_PIX_FMT_H264;
2062 channel->profile = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
2063 channel->level =
2064 select_minimum_h264_level(channel->width, channel->height);
2065 channel->sizeimage_encoded =
2066 estimate_stream_size(channel->width, channel->height);
2067
2068 channel->bitrate_mode = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR;
2069 channel->bitrate = maximum_bitrate(channel->level);
2070 channel->bitrate_peak = maximum_bitrate(channel->level);
2071 channel->cpb_size = maximum_cpb_size(channel->level);
2072 channel->gop_size = ALLEGRO_GOP_SIZE_DEFAULT;
2073 }
2074
2075 static int allegro_queue_setup(struct vb2_queue *vq,
2076 unsigned int *nbuffers, unsigned int *nplanes,
2077 unsigned int sizes[],
2078 struct device *alloc_devs[])
2079 {
2080 struct allegro_channel *channel = vb2_get_drv_priv(vq);
2081 struct allegro_dev *dev = channel->dev;
2082
2083 v4l2_dbg(2, debug, &dev->v4l2_dev,
2084 "%s: queue setup[%s]: nplanes = %d\n",
2085 V4L2_TYPE_IS_OUTPUT(vq->type) ? "output" : "capture",
2086 *nplanes == 0 ? "REQBUFS" : "CREATE_BUFS", *nplanes);
2087
2088 if (*nplanes != 0) {
2089 if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
2090 if (sizes[0] < channel->sizeimage_raw)
2091 return -EINVAL;
2092 } else {
2093 if (sizes[0] < channel->sizeimage_encoded)
2094 return -EINVAL;
2095 }
2096 } else {
2097 *nplanes = 1;
2098 if (V4L2_TYPE_IS_OUTPUT(vq->type))
2099 sizes[0] = channel->sizeimage_raw;
2100 else
2101 sizes[0] = channel->sizeimage_encoded;
2102 }
2103
2104 return 0;
2105 }
2106
2107 static int allegro_buf_prepare(struct vb2_buffer *vb)
2108 {
2109 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2110 struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2111 struct allegro_dev *dev = channel->dev;
2112
2113 if (allegro_get_state(channel) == ALLEGRO_STATE_DRAIN &&
2114 V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type))
2115 return -EBUSY;
2116
2117 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
2118 if (vbuf->field == V4L2_FIELD_ANY)
2119 vbuf->field = V4L2_FIELD_NONE;
2120 if (vbuf->field != V4L2_FIELD_NONE) {
2121 v4l2_err(&dev->v4l2_dev,
2122 "channel %d: unsupported field\n",
2123 channel->mcu_channel_id);
2124 return -EINVAL;
2125 }
2126 }
2127
2128 return 0;
2129 }
2130
2131 static void allegro_buf_queue(struct vb2_buffer *vb)
2132 {
2133 struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2134 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2135
2136 if (allegro_get_state(channel) == ALLEGRO_STATE_WAIT_FOR_BUFFER &&
2137 vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2138 allegro_channel_buf_done(channel, vbuf, VB2_BUF_STATE_DONE);
2139 return;
2140 }
2141
2142 v4l2_m2m_buf_queue(channel->fh.m2m_ctx, vbuf);
2143 }
2144
2145 static int allegro_start_streaming(struct vb2_queue *q, unsigned int count)
2146 {
2147 struct allegro_channel *channel = vb2_get_drv_priv(q);
2148 struct allegro_dev *dev = channel->dev;
2149
2150 v4l2_dbg(2, debug, &dev->v4l2_dev,
2151 "%s: start streaming\n",
2152 V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2153
2154 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2155 channel->osequence = 0;
2156 allegro_set_state(channel, ALLEGRO_STATE_ENCODING);
2157 } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2158 channel->csequence = 0;
2159 }
2160
2161 return 0;
2162 }
2163
2164 static void allegro_stop_streaming(struct vb2_queue *q)
2165 {
2166 struct allegro_channel *channel = vb2_get_drv_priv(q);
2167 struct allegro_dev *dev = channel->dev;
2168 struct vb2_v4l2_buffer *buffer;
2169
2170 v4l2_dbg(2, debug, &dev->v4l2_dev,
2171 "%s: stop streaming\n",
2172 V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2173
2174 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2175 allegro_set_state(channel, ALLEGRO_STATE_STOPPED);
2176 while ((buffer = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx)))
2177 v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2178 } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2179 allegro_destroy_channel(channel);
2180 while ((buffer = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx)))
2181 v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2182 }
2183 }
2184
2185 static const struct vb2_ops allegro_queue_ops = {
2186 .queue_setup = allegro_queue_setup,
2187 .buf_prepare = allegro_buf_prepare,
2188 .buf_queue = allegro_buf_queue,
2189 .start_streaming = allegro_start_streaming,
2190 .stop_streaming = allegro_stop_streaming,
2191 .wait_prepare = vb2_ops_wait_prepare,
2192 .wait_finish = vb2_ops_wait_finish,
2193 };
2194
2195 static int allegro_queue_init(void *priv,
2196 struct vb2_queue *src_vq,
2197 struct vb2_queue *dst_vq)
2198 {
2199 int err;
2200 struct allegro_channel *channel = priv;
2201
2202 src_vq->dev = &channel->dev->plat_dev->dev;
2203 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2204 src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2205 src_vq->mem_ops = &vb2_dma_contig_memops;
2206 src_vq->drv_priv = channel;
2207 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2208 src_vq->ops = &allegro_queue_ops;
2209 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2210 src_vq->lock = &channel->dev->lock;
2211 err = vb2_queue_init(src_vq);
2212 if (err)
2213 return err;
2214
2215 dst_vq->dev = &channel->dev->plat_dev->dev;
2216 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2217 dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2218 dst_vq->mem_ops = &vb2_dma_contig_memops;
2219 dst_vq->drv_priv = channel;
2220 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2221 dst_vq->ops = &allegro_queue_ops;
2222 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2223 dst_vq->lock = &channel->dev->lock;
2224 err = vb2_queue_init(dst_vq);
2225 if (err)
2226 return err;
2227
2228 return 0;
2229 }
2230
2231 static int allegro_s_ctrl(struct v4l2_ctrl *ctrl)
2232 {
2233 struct allegro_channel *channel = container_of(ctrl->handler,
2234 struct allegro_channel,
2235 ctrl_handler);
2236 struct allegro_dev *dev = channel->dev;
2237
2238 v4l2_dbg(1, debug, &dev->v4l2_dev,
2239 "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val);
2240
2241 switch (ctrl->id) {
2242 case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
2243 channel->level = ctrl->val;
2244 break;
2245 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2246 channel->bitrate_mode = ctrl->val;
2247 break;
2248 case V4L2_CID_MPEG_VIDEO_BITRATE:
2249 channel->bitrate = ctrl->val;
2250 break;
2251 case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK:
2252 channel->bitrate_peak = ctrl->val;
2253 break;
2254 case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE:
2255 channel->cpb_size = ctrl->val;
2256 break;
2257 case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
2258 channel->gop_size = ctrl->val;
2259 break;
2260 }
2261
2262 return 0;
2263 }
2264
2265 static const struct v4l2_ctrl_ops allegro_ctrl_ops = {
2266 .s_ctrl = allegro_s_ctrl,
2267 };
2268
2269 static int allegro_open(struct file *file)
2270 {
2271 struct video_device *vdev = video_devdata(file);
2272 struct allegro_dev *dev = video_get_drvdata(vdev);
2273 struct allegro_channel *channel = NULL;
2274 struct v4l2_ctrl_handler *handler;
2275 u64 mask;
2276
2277 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2278 if (!channel)
2279 return -ENOMEM;
2280
2281 v4l2_fh_init(&channel->fh, vdev);
2282 file->private_data = &channel->fh;
2283 v4l2_fh_add(&channel->fh);
2284
2285 init_completion(&channel->completion);
2286
2287 channel->dev = dev;
2288
2289 allegro_set_default_params(channel);
2290
2291 handler = &channel->ctrl_handler;
2292 v4l2_ctrl_handler_init(handler, 0);
2293 channel->mpeg_video_h264_profile = v4l2_ctrl_new_std_menu(handler,
2294 &allegro_ctrl_ops,
2295 V4L2_CID_MPEG_VIDEO_H264_PROFILE,
2296 V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0,
2297 V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE);
2298 mask = 1 << V4L2_MPEG_VIDEO_H264_LEVEL_1B;
2299 channel->mpeg_video_h264_level = v4l2_ctrl_new_std_menu(handler,
2300 &allegro_ctrl_ops,
2301 V4L2_CID_MPEG_VIDEO_H264_LEVEL,
2302 V4L2_MPEG_VIDEO_H264_LEVEL_5_1, mask,
2303 V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
2304 channel->mpeg_video_bitrate_mode = v4l2_ctrl_new_std_menu(handler,
2305 &allegro_ctrl_ops,
2306 V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
2307 V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,
2308 channel->bitrate_mode);
2309 channel->mpeg_video_bitrate = v4l2_ctrl_new_std(handler,
2310 &allegro_ctrl_ops,
2311 V4L2_CID_MPEG_VIDEO_BITRATE,
2312 0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2313 1, channel->bitrate);
2314 channel->mpeg_video_bitrate_peak = v4l2_ctrl_new_std(handler,
2315 &allegro_ctrl_ops,
2316 V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
2317 0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2318 1, channel->bitrate_peak);
2319 channel->mpeg_video_cpb_size = v4l2_ctrl_new_std(handler,
2320 &allegro_ctrl_ops,
2321 V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
2322 0, maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2323 1, channel->cpb_size);
2324 channel->mpeg_video_gop_size = v4l2_ctrl_new_std(handler,
2325 &allegro_ctrl_ops,
2326 V4L2_CID_MPEG_VIDEO_GOP_SIZE,
2327 0, ALLEGRO_GOP_SIZE_MAX,
2328 1, channel->gop_size);
2329 v4l2_ctrl_new_std(handler,
2330 &allegro_ctrl_ops,
2331 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
2332 1, 32,
2333 1, 1);
2334 channel->fh.ctrl_handler = handler;
2335
2336 channel->mcu_channel_id = -1;
2337 channel->user_id = -1;
2338
2339 INIT_LIST_HEAD(&channel->buffers_reference);
2340 INIT_LIST_HEAD(&channel->buffers_intermediate);
2341
2342 list_add(&channel->list, &dev->channels);
2343
2344 channel->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, channel,
2345 allegro_queue_init);
2346
2347 return 0;
2348 }
2349
2350 static int allegro_release(struct file *file)
2351 {
2352 struct allegro_channel *channel = fh_to_channel(file->private_data);
2353
2354 v4l2_m2m_ctx_release(channel->fh.m2m_ctx);
2355
2356 list_del(&channel->list);
2357
2358 v4l2_ctrl_handler_free(&channel->ctrl_handler);
2359
2360 v4l2_fh_del(&channel->fh);
2361 v4l2_fh_exit(&channel->fh);
2362
2363 kfree(channel);
2364
2365 return 0;
2366 }
2367
2368 static int allegro_querycap(struct file *file, void *fh,
2369 struct v4l2_capability *cap)
2370 {
2371 struct video_device *vdev = video_devdata(file);
2372 struct allegro_dev *dev = video_get_drvdata(vdev);
2373
2374 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
2375 strscpy(cap->card, "Allegro DVT Video Encoder", sizeof(cap->card));
2376 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
2377 dev_name(&dev->plat_dev->dev));
2378
2379 return 0;
2380 }
2381
2382 static int allegro_enum_fmt_vid(struct file *file, void *fh,
2383 struct v4l2_fmtdesc *f)
2384 {
2385 if (f->index)
2386 return -EINVAL;
2387 switch (f->type) {
2388 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
2389 f->pixelformat = V4L2_PIX_FMT_NV12;
2390 break;
2391 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
2392 f->pixelformat = V4L2_PIX_FMT_H264;
2393 break;
2394 default:
2395 return -EINVAL;
2396 }
2397 return 0;
2398 }
2399
2400 static int allegro_g_fmt_vid_cap(struct file *file, void *fh,
2401 struct v4l2_format *f)
2402 {
2403 struct allegro_channel *channel = fh_to_channel(fh);
2404
2405 f->fmt.pix.field = V4L2_FIELD_NONE;
2406 f->fmt.pix.width = channel->width;
2407 f->fmt.pix.height = channel->height;
2408
2409 f->fmt.pix.colorspace = channel->colorspace;
2410 f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
2411 f->fmt.pix.quantization = channel->quantization;
2412 f->fmt.pix.xfer_func = channel->xfer_func;
2413
2414 f->fmt.pix.pixelformat = channel->codec;
2415 f->fmt.pix.bytesperline = 0;
2416 f->fmt.pix.sizeimage = channel->sizeimage_encoded;
2417
2418 return 0;
2419 }
2420
2421 static int allegro_try_fmt_vid_cap(struct file *file, void *fh,
2422 struct v4l2_format *f)
2423 {
2424 f->fmt.pix.field = V4L2_FIELD_NONE;
2425
2426 f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
2427 ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
2428 f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
2429 ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
2430
2431 f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
2432 f->fmt.pix.bytesperline = 0;
2433 f->fmt.pix.sizeimage =
2434 estimate_stream_size(f->fmt.pix.width, f->fmt.pix.height);
2435
2436 return 0;
2437 }
2438
2439 static int allegro_g_fmt_vid_out(struct file *file, void *fh,
2440 struct v4l2_format *f)
2441 {
2442 struct allegro_channel *channel = fh_to_channel(fh);
2443
2444 f->fmt.pix.field = V4L2_FIELD_NONE;
2445
2446 f->fmt.pix.width = channel->width;
2447 f->fmt.pix.height = channel->height;
2448
2449 f->fmt.pix.colorspace = channel->colorspace;
2450 f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
2451 f->fmt.pix.quantization = channel->quantization;
2452 f->fmt.pix.xfer_func = channel->xfer_func;
2453
2454 f->fmt.pix.pixelformat = channel->pixelformat;
2455 f->fmt.pix.bytesperline = channel->stride;
2456 f->fmt.pix.sizeimage = channel->sizeimage_raw;
2457
2458 return 0;
2459 }
2460
2461 static int allegro_try_fmt_vid_out(struct file *file, void *fh,
2462 struct v4l2_format *f)
2463 {
2464 f->fmt.pix.field = V4L2_FIELD_NONE;
2465
2466
2467
2468
2469
2470
2471
2472
2473 f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
2474 ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
2475 f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
2476 ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
2477
2478 f->fmt.pix.pixelformat = V4L2_PIX_FMT_NV12;
2479 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 32);
2480 f->fmt.pix.sizeimage =
2481 f->fmt.pix.bytesperline * f->fmt.pix.height * 3 / 2;
2482
2483 return 0;
2484 }
2485
2486 static int allegro_s_fmt_vid_out(struct file *file, void *fh,
2487 struct v4l2_format *f)
2488 {
2489 struct allegro_channel *channel = fh_to_channel(fh);
2490 int err;
2491
2492 err = allegro_try_fmt_vid_out(file, fh, f);
2493 if (err)
2494 return err;
2495
2496 channel->width = f->fmt.pix.width;
2497 channel->height = f->fmt.pix.height;
2498 channel->stride = f->fmt.pix.bytesperline;
2499 channel->sizeimage_raw = f->fmt.pix.sizeimage;
2500
2501 channel->colorspace = f->fmt.pix.colorspace;
2502 channel->ycbcr_enc = f->fmt.pix.ycbcr_enc;
2503 channel->quantization = f->fmt.pix.quantization;
2504 channel->xfer_func = f->fmt.pix.xfer_func;
2505
2506 channel->level =
2507 select_minimum_h264_level(channel->width, channel->height);
2508 channel->sizeimage_encoded =
2509 estimate_stream_size(channel->width, channel->height);
2510
2511 return 0;
2512 }
2513
2514 static int allegro_channel_cmd_stop(struct allegro_channel *channel)
2515 {
2516 struct allegro_dev *dev = channel->dev;
2517 struct vb2_v4l2_buffer *dst_buf;
2518
2519 switch (allegro_get_state(channel)) {
2520 case ALLEGRO_STATE_DRAIN:
2521 case ALLEGRO_STATE_WAIT_FOR_BUFFER:
2522 return -EBUSY;
2523 case ALLEGRO_STATE_ENCODING:
2524 allegro_set_state(channel, ALLEGRO_STATE_DRAIN);
2525 break;
2526 default:
2527 return 0;
2528 }
2529
2530
2531 if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) != 0) {
2532 v4l2_dbg(1, debug, &dev->v4l2_dev,
2533 "channel %d: CMD_STOP: continue encoding src buffers\n",
2534 channel->mcu_channel_id);
2535 return 0;
2536 }
2537
2538
2539 dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
2540 if (dst_buf) {
2541 v4l2_dbg(1, debug, &dev->v4l2_dev,
2542 "channel %d: CMD_STOP: signaling EOS\n",
2543 channel->mcu_channel_id);
2544 allegro_channel_buf_done(channel, dst_buf, VB2_BUF_STATE_DONE);
2545 return 0;
2546 }
2547
2548
2549
2550
2551
2552 v4l2_dbg(1, debug, &dev->v4l2_dev,
2553 "channel %d: CMD_STOP: wait for CAPTURE buffer to signal EOS\n",
2554 channel->mcu_channel_id);
2555 allegro_set_state(channel, ALLEGRO_STATE_WAIT_FOR_BUFFER);
2556
2557 return 0;
2558 }
2559
2560 static int allegro_channel_cmd_start(struct allegro_channel *channel)
2561 {
2562 switch (allegro_get_state(channel)) {
2563 case ALLEGRO_STATE_DRAIN:
2564 case ALLEGRO_STATE_WAIT_FOR_BUFFER:
2565 return -EBUSY;
2566 case ALLEGRO_STATE_STOPPED:
2567 allegro_set_state(channel, ALLEGRO_STATE_ENCODING);
2568 break;
2569 default:
2570 return 0;
2571 }
2572
2573 return 0;
2574 }
2575
2576 static int allegro_encoder_cmd(struct file *file, void *fh,
2577 struct v4l2_encoder_cmd *cmd)
2578 {
2579 struct allegro_channel *channel = fh_to_channel(fh);
2580 int err;
2581
2582 err = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
2583 if (err)
2584 return err;
2585
2586 switch (cmd->cmd) {
2587 case V4L2_ENC_CMD_STOP:
2588 err = allegro_channel_cmd_stop(channel);
2589 break;
2590 case V4L2_ENC_CMD_START:
2591 err = allegro_channel_cmd_start(channel);
2592 break;
2593 default:
2594 err = -EINVAL;
2595 break;
2596 }
2597
2598 return err;
2599 }
2600
2601 static int allegro_enum_framesizes(struct file *file, void *fh,
2602 struct v4l2_frmsizeenum *fsize)
2603 {
2604 switch (fsize->pixel_format) {
2605 case V4L2_PIX_FMT_H264:
2606 case V4L2_PIX_FMT_NV12:
2607 break;
2608 default:
2609 return -EINVAL;
2610 }
2611
2612 if (fsize->index)
2613 return -EINVAL;
2614
2615 fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
2616 fsize->stepwise.min_width = ALLEGRO_WIDTH_MIN;
2617 fsize->stepwise.max_width = ALLEGRO_WIDTH_MAX;
2618 fsize->stepwise.step_width = 1;
2619 fsize->stepwise.min_height = ALLEGRO_HEIGHT_MIN;
2620 fsize->stepwise.max_height = ALLEGRO_HEIGHT_MAX;
2621 fsize->stepwise.step_height = 1;
2622
2623 return 0;
2624 }
2625
2626 static int allegro_ioctl_streamon(struct file *file, void *priv,
2627 enum v4l2_buf_type type)
2628 {
2629 struct v4l2_fh *fh = file->private_data;
2630 struct allegro_channel *channel = fh_to_channel(fh);
2631 int err;
2632
2633 if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2634 err = allegro_create_channel(channel);
2635 if (err)
2636 return err;
2637 }
2638
2639 return v4l2_m2m_streamon(file, fh->m2m_ctx, type);
2640 }
2641
2642 static int allegro_subscribe_event(struct v4l2_fh *fh,
2643 const struct v4l2_event_subscription *sub)
2644 {
2645 switch (sub->type) {
2646 case V4L2_EVENT_EOS:
2647 return v4l2_event_subscribe(fh, sub, 0, NULL);
2648 default:
2649 return v4l2_ctrl_subscribe_event(fh, sub);
2650 }
2651 }
2652
2653 static const struct v4l2_ioctl_ops allegro_ioctl_ops = {
2654 .vidioc_querycap = allegro_querycap,
2655 .vidioc_enum_fmt_vid_cap = allegro_enum_fmt_vid,
2656 .vidioc_enum_fmt_vid_out = allegro_enum_fmt_vid,
2657 .vidioc_g_fmt_vid_cap = allegro_g_fmt_vid_cap,
2658 .vidioc_try_fmt_vid_cap = allegro_try_fmt_vid_cap,
2659 .vidioc_s_fmt_vid_cap = allegro_try_fmt_vid_cap,
2660 .vidioc_g_fmt_vid_out = allegro_g_fmt_vid_out,
2661 .vidioc_try_fmt_vid_out = allegro_try_fmt_vid_out,
2662 .vidioc_s_fmt_vid_out = allegro_s_fmt_vid_out,
2663
2664 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
2665 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
2666
2667 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
2668 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
2669 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
2670 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
2671 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
2672
2673 .vidioc_streamon = allegro_ioctl_streamon,
2674 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
2675
2676 .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
2677 .vidioc_encoder_cmd = allegro_encoder_cmd,
2678 .vidioc_enum_framesizes = allegro_enum_framesizes,
2679
2680 .vidioc_subscribe_event = allegro_subscribe_event,
2681 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2682 };
2683
2684 static const struct v4l2_file_operations allegro_fops = {
2685 .owner = THIS_MODULE,
2686 .open = allegro_open,
2687 .release = allegro_release,
2688 .poll = v4l2_m2m_fop_poll,
2689 .unlocked_ioctl = video_ioctl2,
2690 .mmap = v4l2_m2m_fop_mmap,
2691 };
2692
2693 static int allegro_register_device(struct allegro_dev *dev)
2694 {
2695 struct video_device *video_dev = &dev->video_dev;
2696
2697 strscpy(video_dev->name, "allegro", sizeof(video_dev->name));
2698 video_dev->fops = &allegro_fops;
2699 video_dev->ioctl_ops = &allegro_ioctl_ops;
2700 video_dev->release = video_device_release_empty;
2701 video_dev->lock = &dev->lock;
2702 video_dev->v4l2_dev = &dev->v4l2_dev;
2703 video_dev->vfl_dir = VFL_DIR_M2M;
2704 video_dev->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
2705 video_set_drvdata(video_dev, dev);
2706
2707 return video_register_device(video_dev, VFL_TYPE_GRABBER, 0);
2708 }
2709
2710 static void allegro_device_run(void *priv)
2711 {
2712 struct allegro_channel *channel = priv;
2713 struct allegro_dev *dev = channel->dev;
2714 struct vb2_v4l2_buffer *src_buf;
2715 struct vb2_v4l2_buffer *dst_buf;
2716 dma_addr_t src_y;
2717 dma_addr_t src_uv;
2718 dma_addr_t dst_addr;
2719 unsigned long dst_size;
2720
2721 dst_buf = v4l2_m2m_next_dst_buf(channel->fh.m2m_ctx);
2722 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
2723 dst_size = vb2_plane_size(&dst_buf->vb2_buf, 0);
2724 allegro_mcu_send_put_stream_buffer(dev, channel, dst_addr, dst_size);
2725
2726 src_buf = v4l2_m2m_next_src_buf(channel->fh.m2m_ctx);
2727 src_buf->sequence = channel->osequence++;
2728
2729 src_y = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
2730 src_uv = src_y + (channel->stride * channel->height);
2731 allegro_mcu_send_encode_frame(dev, channel, src_y, src_uv);
2732 }
2733
2734 static const struct v4l2_m2m_ops allegro_m2m_ops = {
2735 .device_run = allegro_device_run,
2736 };
2737
2738 static int allegro_mcu_hw_init(struct allegro_dev *dev,
2739 const struct fw_info *info)
2740 {
2741 int err;
2742
2743 allegro_mbox_init(dev, &dev->mbox_command,
2744 info->mailbox_cmd, info->mailbox_size);
2745 allegro_mbox_init(dev, &dev->mbox_status,
2746 info->mailbox_status, info->mailbox_size);
2747
2748 allegro_mcu_enable_interrupts(dev);
2749
2750
2751 allegro_mcu_start(dev);
2752 err = allegro_mcu_wait_for_init_timeout(dev, 5000);
2753 if (err < 0) {
2754 v4l2_err(&dev->v4l2_dev,
2755 "mcu did not send INIT after reset\n");
2756 err = -EIO;
2757 goto err_disable_interrupts;
2758 }
2759
2760 err = allegro_alloc_buffer(dev, &dev->suballocator,
2761 info->suballocator_size);
2762 if (err) {
2763 v4l2_err(&dev->v4l2_dev,
2764 "failed to allocate %zu bytes for suballocator\n",
2765 info->suballocator_size);
2766 goto err_reset_mcu;
2767 }
2768
2769 allegro_mcu_send_init(dev, dev->suballocator.paddr,
2770 dev->suballocator.size);
2771 err = allegro_mcu_wait_for_init_timeout(dev, 5000);
2772 if (err < 0) {
2773 v4l2_err(&dev->v4l2_dev,
2774 "mcu failed to configure sub-allocator\n");
2775 err = -EIO;
2776 goto err_free_suballocator;
2777 }
2778
2779 return 0;
2780
2781 err_free_suballocator:
2782 allegro_free_buffer(dev, &dev->suballocator);
2783 err_reset_mcu:
2784 allegro_mcu_reset(dev);
2785 err_disable_interrupts:
2786 allegro_mcu_disable_interrupts(dev);
2787
2788 return err;
2789 }
2790
2791 static int allegro_mcu_hw_deinit(struct allegro_dev *dev)
2792 {
2793 int err;
2794
2795 err = allegro_mcu_reset(dev);
2796 if (err)
2797 v4l2_warn(&dev->v4l2_dev,
2798 "mcu failed to enter sleep state\n");
2799
2800 err = allegro_mcu_disable_interrupts(dev);
2801 if (err)
2802 v4l2_warn(&dev->v4l2_dev,
2803 "failed to disable interrupts\n");
2804
2805 allegro_free_buffer(dev, &dev->suballocator);
2806
2807 return 0;
2808 }
2809
2810 static void allegro_fw_callback(const struct firmware *fw, void *context)
2811 {
2812 struct allegro_dev *dev = context;
2813 const char *fw_codec_name = "al5e.fw";
2814 const struct firmware *fw_codec;
2815 int err;
2816 const struct fw_info *info;
2817
2818 if (!fw)
2819 return;
2820
2821 v4l2_dbg(1, debug, &dev->v4l2_dev,
2822 "requesting codec firmware '%s'\n", fw_codec_name);
2823 err = request_firmware(&fw_codec, fw_codec_name, &dev->plat_dev->dev);
2824 if (err)
2825 goto err_release_firmware;
2826
2827 info = allegro_get_firmware_info(dev, fw, fw_codec);
2828 if (!info) {
2829 v4l2_err(&dev->v4l2_dev, "firmware is not supported\n");
2830 goto err_release_firmware_codec;
2831 }
2832
2833 v4l2_info(&dev->v4l2_dev,
2834 "using mcu firmware version '%s'\n", info->version);
2835
2836
2837 err = allegro_mcu_reset(dev);
2838 if (err) {
2839 v4l2_err(&dev->v4l2_dev, "failed to reset mcu\n");
2840 goto err_release_firmware_codec;
2841 }
2842
2843 allegro_copy_firmware(dev, fw->data, fw->size);
2844 allegro_copy_fw_codec(dev, fw_codec->data, fw_codec->size);
2845
2846 err = allegro_mcu_hw_init(dev, info);
2847 if (err) {
2848 v4l2_err(&dev->v4l2_dev, "failed to initialize mcu\n");
2849 goto err_free_fw_codec;
2850 }
2851
2852 dev->m2m_dev = v4l2_m2m_init(&allegro_m2m_ops);
2853 if (IS_ERR(dev->m2m_dev)) {
2854 v4l2_err(&dev->v4l2_dev, "failed to init mem2mem device\n");
2855 goto err_mcu_hw_deinit;
2856 }
2857
2858 err = allegro_register_device(dev);
2859 if (err) {
2860 v4l2_err(&dev->v4l2_dev, "failed to register video device\n");
2861 goto err_m2m_release;
2862 }
2863
2864 v4l2_dbg(1, debug, &dev->v4l2_dev,
2865 "allegro codec registered as /dev/video%d\n",
2866 dev->video_dev.num);
2867
2868 release_firmware(fw_codec);
2869 release_firmware(fw);
2870
2871 return;
2872
2873 err_m2m_release:
2874 v4l2_m2m_release(dev->m2m_dev);
2875 dev->m2m_dev = NULL;
2876 err_mcu_hw_deinit:
2877 allegro_mcu_hw_deinit(dev);
2878 err_free_fw_codec:
2879 allegro_free_fw_codec(dev);
2880 err_release_firmware_codec:
2881 release_firmware(fw_codec);
2882 err_release_firmware:
2883 release_firmware(fw);
2884 }
2885
2886 static int allegro_firmware_request_nowait(struct allegro_dev *dev)
2887 {
2888 const char *fw = "al5e_b.fw";
2889
2890 v4l2_dbg(1, debug, &dev->v4l2_dev,
2891 "requesting firmware '%s'\n", fw);
2892 return request_firmware_nowait(THIS_MODULE, true, fw,
2893 &dev->plat_dev->dev, GFP_KERNEL, dev,
2894 allegro_fw_callback);
2895 }
2896
2897 static int allegro_probe(struct platform_device *pdev)
2898 {
2899 struct allegro_dev *dev;
2900 struct resource *res, *sram_res;
2901 int ret;
2902 int irq;
2903 void __iomem *regs, *sram_regs;
2904
2905 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2906 if (!dev)
2907 return -ENOMEM;
2908 dev->plat_dev = pdev;
2909 init_completion(&dev->init_complete);
2910 INIT_LIST_HEAD(&dev->channels);
2911
2912 mutex_init(&dev->lock);
2913
2914 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
2915 if (!res) {
2916 dev_err(&pdev->dev,
2917 "regs resource missing from device tree\n");
2918 return -EINVAL;
2919 }
2920 regs = devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res));
2921 if (IS_ERR(regs)) {
2922 dev_err(&pdev->dev, "failed to map registers\n");
2923 return PTR_ERR(regs);
2924 }
2925 dev->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
2926 &allegro_regmap_config);
2927 if (IS_ERR(dev->regmap)) {
2928 dev_err(&pdev->dev, "failed to init regmap\n");
2929 return PTR_ERR(dev->regmap);
2930 }
2931
2932 sram_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
2933 if (!sram_res) {
2934 dev_err(&pdev->dev,
2935 "sram resource missing from device tree\n");
2936 return -EINVAL;
2937 }
2938 sram_regs = devm_ioremap_nocache(&pdev->dev,
2939 sram_res->start,
2940 resource_size(sram_res));
2941 if (IS_ERR(sram_regs)) {
2942 dev_err(&pdev->dev, "failed to map sram\n");
2943 return PTR_ERR(sram_regs);
2944 }
2945 dev->sram = devm_regmap_init_mmio(&pdev->dev, sram_regs,
2946 &allegro_sram_config);
2947 if (IS_ERR(dev->sram)) {
2948 dev_err(&pdev->dev, "failed to init sram\n");
2949 return PTR_ERR(dev->sram);
2950 }
2951
2952 irq = platform_get_irq(pdev, 0);
2953 if (irq < 0)
2954 return irq;
2955 ret = devm_request_threaded_irq(&pdev->dev, irq,
2956 allegro_hardirq,
2957 allegro_irq_thread,
2958 IRQF_SHARED, dev_name(&pdev->dev), dev);
2959 if (ret < 0) {
2960 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2961 return ret;
2962 }
2963
2964 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2965 if (ret)
2966 return ret;
2967
2968 platform_set_drvdata(pdev, dev);
2969
2970 ret = allegro_firmware_request_nowait(dev);
2971 if (ret < 0) {
2972 v4l2_err(&dev->v4l2_dev,
2973 "failed to request firmware: %d\n", ret);
2974 return ret;
2975 }
2976
2977 return 0;
2978 }
2979
2980 static int allegro_remove(struct platform_device *pdev)
2981 {
2982 struct allegro_dev *dev = platform_get_drvdata(pdev);
2983
2984 video_unregister_device(&dev->video_dev);
2985 if (dev->m2m_dev)
2986 v4l2_m2m_release(dev->m2m_dev);
2987 allegro_mcu_hw_deinit(dev);
2988 allegro_free_fw_codec(dev);
2989
2990 v4l2_device_unregister(&dev->v4l2_dev);
2991
2992 return 0;
2993 }
2994
2995 static const struct of_device_id allegro_dt_ids[] = {
2996 { .compatible = "allegro,al5e-1.1" },
2997 { }
2998 };
2999
3000 MODULE_DEVICE_TABLE(of, allegro_dt_ids);
3001
3002 static struct platform_driver allegro_driver = {
3003 .probe = allegro_probe,
3004 .remove = allegro_remove,
3005 .driver = {
3006 .name = "allegro",
3007 .of_match_table = of_match_ptr(allegro_dt_ids),
3008 },
3009 };
3010
3011 module_platform_driver(allegro_driver);
3012
3013 MODULE_LICENSE("GPL");
3014 MODULE_AUTHOR("Michael Tretter <kernel@pengutronix.de>");
3015 MODULE_DESCRIPTION("Allegro DVT encoder driver");