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8 #ifndef _RT3883_REGS_H_
9 #define _RT3883_REGS_H_
10
11 #include <linux/bitops.h>
12
13 #define RT3883_SDRAM_BASE 0x00000000
14 #define RT3883_SYSC_BASE 0x10000000
15 #define RT3883_TIMER_BASE 0x10000100
16 #define RT3883_INTC_BASE 0x10000200
17 #define RT3883_MEMC_BASE 0x10000300
18 #define RT3883_UART0_BASE 0x10000500
19 #define RT3883_PIO_BASE 0x10000600
20 #define RT3883_FSCC_BASE 0x10000700
21 #define RT3883_NANDC_BASE 0x10000810
22 #define RT3883_I2C_BASE 0x10000900
23 #define RT3883_I2S_BASE 0x10000a00
24 #define RT3883_SPI_BASE 0x10000b00
25 #define RT3883_UART1_BASE 0x10000c00
26 #define RT3883_PCM_BASE 0x10002000
27 #define RT3883_GDMA_BASE 0x10002800
28 #define RT3883_CODEC1_BASE 0x10003000
29 #define RT3883_CODEC2_BASE 0x10003800
30 #define RT3883_FE_BASE 0x10100000
31 #define RT3883_ROM_BASE 0x10118000
32 #define RT3883_USBDEV_BASE 0x10112000
33 #define RT3883_PCI_BASE 0x10140000
34 #define RT3883_WLAN_BASE 0x10180000
35 #define RT3883_USBHOST_BASE 0x101c0000
36 #define RT3883_BOOT_BASE 0x1c000000
37 #define RT3883_SRAM_BASE 0x1e000000
38 #define RT3883_PCIMEM_BASE 0x20000000
39
40 #define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
41 #define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
42
43 #define RT3883_SYSC_SIZE 0x100
44 #define RT3883_TIMER_SIZE 0x100
45 #define RT3883_INTC_SIZE 0x100
46 #define RT3883_MEMC_SIZE 0x100
47 #define RT3883_UART0_SIZE 0x100
48 #define RT3883_UART1_SIZE 0x100
49 #define RT3883_PIO_SIZE 0x100
50 #define RT3883_FSCC_SIZE 0x100
51 #define RT3883_NANDC_SIZE 0x0f0
52 #define RT3883_I2C_SIZE 0x100
53 #define RT3883_I2S_SIZE 0x100
54 #define RT3883_SPI_SIZE 0x100
55 #define RT3883_PCM_SIZE 0x800
56 #define RT3883_GDMA_SIZE 0x800
57 #define RT3883_CODEC1_SIZE 0x800
58 #define RT3883_CODEC2_SIZE 0x800
59 #define RT3883_FE_SIZE 0x10000
60 #define RT3883_ROM_SIZE 0x4000
61 #define RT3883_USBDEV_SIZE 0x4000
62 #define RT3883_PCI_SIZE 0x40000
63 #define RT3883_WLAN_SIZE 0x40000
64 #define RT3883_USBHOST_SIZE 0x40000
65 #define RT3883_BOOT_SIZE (32 * 1024 * 1024)
66 #define RT3883_SRAM_SIZE (32 * 1024 * 1024)
67
68
69 #define RT3883_SYSC_REG_CHIPID0_3 0x00
70 #define RT3883_SYSC_REG_CHIPID4_7 0x04
71 #define RT3883_SYSC_REG_REVID 0x0c
72 #define RT3883_SYSC_REG_SYSCFG0 0x10
73 #define RT3883_SYSC_REG_SYSCFG1 0x14
74 #define RT3883_SYSC_REG_CLKCFG0 0x2c
75 #define RT3883_SYSC_REG_CLKCFG1 0x30
76 #define RT3883_SYSC_REG_RSTCTRL 0x34
77 #define RT3883_SYSC_REG_RSTSTAT 0x38
78 #define RT3883_SYSC_REG_USB_PS 0x5c
79 #define RT3883_SYSC_REG_GPIO_MODE 0x60
80 #define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
81 #define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
82 #define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
83 #define RT3883_SYSC_REG_PMU 0x88
84 #define RT3883_SYSC_REG_PMU1 0x8c
85
86 #define RT3883_CHIP_NAME0 0x38335452
87 #define RT3883_CHIP_NAME1 0x20203338
88
89 #define RT3883_REVID_VER_ID_MASK 0x0f
90 #define RT3883_REVID_VER_ID_SHIFT 8
91 #define RT3883_REVID_ECO_ID_MASK 0x0f
92
93 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
94 #define RT3883_SYSCFG0_CPUCLK_SHIFT 8
95 #define RT3883_SYSCFG0_CPUCLK_MASK 0x3
96 #define RT3883_SYSCFG0_CPUCLK_250 0x0
97 #define RT3883_SYSCFG0_CPUCLK_384 0x1
98 #define RT3883_SYSCFG0_CPUCLK_480 0x2
99 #define RT3883_SYSCFG0_CPUCLK_500 0x3
100
101 #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
102 #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
103 #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
104 #define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
105 #define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
106
107 #define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
108 #define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
109 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
110 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
111
112 #define RT3883_GPIO_MODE_UART0_SHIFT 2
113 #define RT3883_GPIO_MODE_UART0_MASK 0x7
114 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
115 #define RT3883_GPIO_MODE_UARTF 0x0
116 #define RT3883_GPIO_MODE_PCM_UARTF 0x1
117 #define RT3883_GPIO_MODE_PCM_I2S 0x2
118 #define RT3883_GPIO_MODE_I2S_UARTF 0x3
119 #define RT3883_GPIO_MODE_PCM_GPIO 0x4
120 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
121 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
122 #define RT3883_GPIO_MODE_GPIO 0x7
123
124 #define RT3883_GPIO_MODE_I2C 0
125 #define RT3883_GPIO_MODE_SPI 1
126 #define RT3883_GPIO_MODE_UART1 5
127 #define RT3883_GPIO_MODE_JTAG 6
128 #define RT3883_GPIO_MODE_MDIO 7
129 #define RT3883_GPIO_MODE_GE1 9
130 #define RT3883_GPIO_MODE_GE2 10
131
132 #define RT3883_GPIO_MODE_PCI_SHIFT 11
133 #define RT3883_GPIO_MODE_PCI_MASK 0x7
134 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
135 #define RT3883_GPIO_MODE_LNA_A_SHIFT 16
136 #define RT3883_GPIO_MODE_LNA_A_MASK 0x3
137 #define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
138 #define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
139 #define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
140 #define RT3883_GPIO_MODE_LNA_G_SHIFT 18
141 #define RT3883_GPIO_MODE_LNA_G_MASK 0x3
142 #define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
143 #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
144 #define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
145
146 #define RT3883_GPIO_I2C_SD 1
147 #define RT3883_GPIO_I2C_SCLK 2
148 #define RT3883_GPIO_SPI_CS0 3
149 #define RT3883_GPIO_SPI_CLK 4
150 #define RT3883_GPIO_SPI_MOSI 5
151 #define RT3883_GPIO_SPI_MISO 6
152 #define RT3883_GPIO_7 7
153 #define RT3883_GPIO_10 10
154 #define RT3883_GPIO_11 11
155 #define RT3883_GPIO_14 14
156 #define RT3883_GPIO_UART1_TXD 15
157 #define RT3883_GPIO_UART1_RXD 16
158 #define RT3883_GPIO_JTAG_TDO 17
159 #define RT3883_GPIO_JTAG_TDI 18
160 #define RT3883_GPIO_JTAG_TMS 19
161 #define RT3883_GPIO_JTAG_TCLK 20
162 #define RT3883_GPIO_JTAG_TRST_N 21
163 #define RT3883_GPIO_MDIO_MDC 22
164 #define RT3883_GPIO_MDIO_MDIO 23
165 #define RT3883_GPIO_LNA_PE_A0 32
166 #define RT3883_GPIO_LNA_PE_A1 33
167 #define RT3883_GPIO_LNA_PE_A2 34
168 #define RT3883_GPIO_LNA_PE_G0 35
169 #define RT3883_GPIO_LNA_PE_G1 36
170 #define RT3883_GPIO_LNA_PE_G2 37
171 #define RT3883_GPIO_PCI_AD0 40
172 #define RT3883_GPIO_PCI_AD31 71
173 #define RT3883_GPIO_GE2_TXD0 72
174 #define RT3883_GPIO_GE2_TXD1 73
175 #define RT3883_GPIO_GE2_TXD2 74
176 #define RT3883_GPIO_GE2_TXD3 75
177 #define RT3883_GPIO_GE2_TXEN 76
178 #define RT3883_GPIO_GE2_TXCLK 77
179 #define RT3883_GPIO_GE2_RXD0 78
180 #define RT3883_GPIO_GE2_RXD1 79
181 #define RT3883_GPIO_GE2_RXD2 80
182 #define RT3883_GPIO_GE2_RXD3 81
183 #define RT3883_GPIO_GE2_RXDV 82
184 #define RT3883_GPIO_GE2_RXCLK 83
185 #define RT3883_GPIO_GE1_TXD0 84
186 #define RT3883_GPIO_GE1_TXD1 85
187 #define RT3883_GPIO_GE1_TXD2 86
188 #define RT3883_GPIO_GE1_TXD3 87
189 #define RT3883_GPIO_GE1_TXEN 88
190 #define RT3883_GPIO_GE1_TXCLK 89
191 #define RT3883_GPIO_GE1_RXD0 90
192 #define RT3883_GPIO_GE1_RXD1 91
193 #define RT3883_GPIO_GE1_RXD2 92
194 #define RT3883_GPIO_GE1_RXD3 93
195 #define RT3883_GPIO_GE1_RXDV 94
196 #define RT3883_GPIO_GE1_RXCLK 95
197
198 #define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
199 #define RT3883_RSTCTRL_FLASH BIT(26)
200 #define RT3883_RSTCTRL_UDEV BIT(25)
201 #define RT3883_RSTCTRL_PCI BIT(24)
202 #define RT3883_RSTCTRL_PCIE BIT(23)
203 #define RT3883_RSTCTRL_UHST BIT(22)
204 #define RT3883_RSTCTRL_FE BIT(21)
205 #define RT3883_RSTCTRL_WLAN BIT(20)
206 #define RT3883_RSTCTRL_UART1 BIT(29)
207 #define RT3883_RSTCTRL_SPI BIT(18)
208 #define RT3883_RSTCTRL_I2S BIT(17)
209 #define RT3883_RSTCTRL_I2C BIT(16)
210 #define RT3883_RSTCTRL_NAND BIT(15)
211 #define RT3883_RSTCTRL_DMA BIT(14)
212 #define RT3883_RSTCTRL_PIO BIT(13)
213 #define RT3883_RSTCTRL_UART BIT(12)
214 #define RT3883_RSTCTRL_PCM BIT(11)
215 #define RT3883_RSTCTRL_MC BIT(10)
216 #define RT3883_RSTCTRL_INTC BIT(9)
217 #define RT3883_RSTCTRL_TIMER BIT(8)
218 #define RT3883_RSTCTRL_SYS BIT(0)
219
220 #define RT3883_INTC_INT_SYSCTL BIT(0)
221 #define RT3883_INTC_INT_TIMER0 BIT(1)
222 #define RT3883_INTC_INT_TIMER1 BIT(2)
223 #define RT3883_INTC_INT_IA BIT(3)
224 #define RT3883_INTC_INT_PCM BIT(4)
225 #define RT3883_INTC_INT_UART0 BIT(5)
226 #define RT3883_INTC_INT_PIO BIT(6)
227 #define RT3883_INTC_INT_DMA BIT(7)
228 #define RT3883_INTC_INT_NAND BIT(8)
229 #define RT3883_INTC_INT_PERFC BIT(9)
230 #define RT3883_INTC_INT_I2S BIT(10)
231 #define RT3883_INTC_INT_UART1 BIT(12)
232 #define RT3883_INTC_INT_UHST BIT(18)
233 #define RT3883_INTC_INT_UDEV BIT(19)
234
235
236 #define RT3883_FSCC_REG_FLASH_CFG0 0x00
237 #define RT3883_FSCC_REG_FLASH_CFG1 0x04
238 #define RT3883_FSCC_REG_CODEC_CFG0 0x40
239 #define RT3883_FSCC_REG_CODEC_CFG1 0x44
240
241 #define RT3883_FLASH_CFG_WIDTH_SHIFT 26
242 #define RT3883_FLASH_CFG_WIDTH_MASK 0x3
243 #define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
244 #define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
245 #define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
246
247 #define RT3883_SDRAM_BASE 0x00000000
248 #define RT3883_MEM_SIZE_MIN 2
249 #define RT3883_MEM_SIZE_MAX 256
250
251 #endif