root/drivers/staging/fbtft/fb_upd161704.c

DEFINITIONS

1. init_display
2. set_addr_win
3. set_var

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * FB driver for the uPD161704 LCD Controller
   4  *
   5  * Copyright (C) 2014 Seong-Woo Kim
   6  *
   7  * Based on fb_ili9325.c by Noralf Tronnes
   8  * Based on ili9325.c by Jeroen Domburg
   9  * Init code from UTFT library by Henning Karlsen
  10  */
  11 
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/delay.h>
  17 
  18 #include "fbtft.h"
  19 
  20 #define DRVNAME         "fb_upd161704"
  21 #define WIDTH           240
  22 #define HEIGHT          320
  23 #define BPP             16
  24 
  25 static int init_display(struct fbtft_par *par)
  26 {
  27         par->fbtftops.reset(par);
  28 
  29         if (par->gpio.cs)
  30                 gpiod_set_value(par->gpio.cs, 0);  /* Activate chip */
  31 
  32         /* Initialization sequence from Lib_UTFT */
  33 
  34         /* register reset */
  35         write_reg(par, 0x0003, 0x0001); /* Soft reset */
  36 
  37         /* oscillator start */
  38         write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */
  39         udelay(100);
  40 
  41         /* y-setting */
  42         write_reg(par, 0x0024, 0x007B); /* amplitude setting */
  43         udelay(10);
  44         write_reg(par, 0x0025, 0x003B); /* amplitude setting */
  45         write_reg(par, 0x0026, 0x0034); /* amplitude setting */
  46         udelay(10);
  47         write_reg(par, 0x0027, 0x0004); /* amplitude setting */
  48         write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */
  49         udelay(10);
  50         write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */
  51         write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */
  52         udelay(10);
  53         write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */
  54         write_reg(par, 0x0063, 0x0022); /* adjustment V34 positive polarity */
  55         udelay(10);
  56         write_reg(par, 0x0064, 0x0027); /* adjustment V31 negative polarity */
  57         udelay(10);
  58         write_reg(par, 0x0065, 0x0014); /* adjustment V61 negative polarity */
  59         udelay(10);
  60         write_reg(par, 0x0066, 0x0010); /* adjustment V61 negative polarity */
  61 
  62         /* Basical clock for 1 line (BASECOUNT[7:0]) number specified */
  63         write_reg(par, 0x002E, 0x002D);
  64 
  65         /* Power supply setting */
  66         write_reg(par, 0x0019, 0x0000); /* DC/DC output setting */
  67         udelay(200);
  68         write_reg(par, 0x001A, 0x1000); /* DC/DC frequency setting */
  69         write_reg(par, 0x001B, 0x0023); /* DC/DC rising setting */
  70         write_reg(par, 0x001C, 0x0C01); /* Regulator voltage setting */
  71         write_reg(par, 0x001D, 0x0000); /* Regulator current setting */
  72         write_reg(par, 0x001E, 0x0009); /* VCOM output setting */
  73         write_reg(par, 0x001F, 0x0035); /* VCOM amplitude setting */
  74         write_reg(par, 0x0020, 0x0015); /* VCOMM cencter setting */
  75         write_reg(par, 0x0018, 0x1E7B); /* DC/DC operation setting */
  76 
  77         /* windows setting */
  78         write_reg(par, 0x0008, 0x0000); /* Minimum X address */
  79         write_reg(par, 0x0009, 0x00EF); /* Maximum X address */
  80         write_reg(par, 0x000a, 0x0000); /* Minimum Y address */
  81         write_reg(par, 0x000b, 0x013F); /* Maximum Y address */
  82 
  83         /* LCD display area setting */
  84         write_reg(par, 0x0029, 0x0000); /* [LCDSIZE]  X MIN. size set */
  85         write_reg(par, 0x002A, 0x0000); /* [LCDSIZE]  Y MIN. size set */
  86         write_reg(par, 0x002B, 0x00EF); /* [LCDSIZE]  X MAX. size set */
  87         write_reg(par, 0x002C, 0x013F); /* [LCDSIZE]  Y MAX. size set */
  88 
  89         /* Gate scan setting */
  90         write_reg(par, 0x0032, 0x0002);
  91 
  92         /* n line inversion line number */
  93         write_reg(par, 0x0033, 0x0000);
  94 
  95         /* Line inversion/frame inversion/interlace setting */
  96         write_reg(par, 0x0037, 0x0000);
  97 
  98         /* Gate scan operation setting register */
  99         write_reg(par, 0x003B, 0x0001);
 100 
 101         /* Color mode */
 102         /*GS = 0: 260-k color (64 gray scale), GS = 1: 8 color (2 gray scale) */
 103         write_reg(par, 0x0004, 0x0000);
 104 
 105         /* RAM control register */
 106         write_reg(par, 0x0005, 0x0000); /*Window access 00:Normal, 10:Window */
 107 
 108         /* Display setting register 2 */
 109         write_reg(par, 0x0001, 0x0000);
 110 
 111         /* display setting */
 112         write_reg(par, 0x0000, 0x0000); /* display on */
 113 
 114         return 0;
 115 }
 116 
 117 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
 118 {
 119         switch (par->info->var.rotate) {
 120         /* R20h = Horizontal GRAM Start Address */
 121         /* R21h = Vertical GRAM Start Address */
 122         case 0:
 123                 write_reg(par, 0x0006, xs);
 124                 write_reg(par, 0x0007, ys);
 125                 break;
 126         case 180:
 127                 write_reg(par, 0x0006, WIDTH - 1 - xs);
 128                 write_reg(par, 0x0007, HEIGHT - 1 - ys);
 129                 break;
 130         case 270:
 131                 write_reg(par, 0x0006, WIDTH - 1 - ys);
 132                 write_reg(par, 0x0007, xs);
 133                 break;
 134         case 90:
 135                 write_reg(par, 0x0006, ys);
 136                 write_reg(par, 0x0007, HEIGHT - 1 - xs);
 137                 break;
 138         }
 139 
 140         write_reg(par, 0x0e); /* Write Data to GRAM */
 141 }
 142 
 143 static int set_var(struct fbtft_par *par)
 144 {
 145         switch (par->info->var.rotate) {
 146         /* AM: GRAM update direction */
 147         case 0:
 148                 write_reg(par, 0x01, 0x0000);
 149                 write_reg(par, 0x05, 0x0000);
 150                 break;
 151         case 180:
 152                 write_reg(par, 0x01, 0x00C0);
 153                 write_reg(par, 0x05, 0x0000);
 154                 break;
 155         case 270:
 156                 write_reg(par, 0x01, 0x0080);
 157                 write_reg(par, 0x05, 0x0001);
 158                 break;
 159         case 90:
 160                 write_reg(par, 0x01, 0x0040);
 161                 write_reg(par, 0x05, 0x0001);
 162                 break;
 163         }
 164 
 165         return 0;
 166 }
 167 
 168 static struct fbtft_display display = {
 169         .regwidth = 16,
 170         .width = WIDTH,
 171         .height = HEIGHT,
 172         .fbtftops = {
 173                 .init_display = init_display,
 174                 .set_addr_win = set_addr_win,
 175                 .set_var = set_var,
 176         },
 177 };
 178 
 179 FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display);
 180 
 181 MODULE_ALIAS("spi:" DRVNAME);
 182 MODULE_ALIAS("platform:" DRVNAME);
 183 MODULE_ALIAS("spi:upd161704");
 184 MODULE_ALIAS("platform:upd161704");
 185 
 186 MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller");
 187 MODULE_AUTHOR("Seong-Woo Kim");
 188 MODULE_LICENSE("GPL");