root/drivers/staging/fbtft/fb_bd663474.c

DEFINITIONS

1. init_display
2. set_addr_win
3. set_var

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * FB driver for the uPD161704 LCD Controller
   4  *
   5  * Copyright (C) 2014 Seong-Woo Kim
   6  *
   7  * Based on fb_ili9325.c by Noralf Tronnes
   8  * Based on ili9325.c by Jeroen Domburg
   9  * Init code from UTFT library by Henning Karlsen
  10  */
  11 
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/delay.h>
  17 
  18 #include "fbtft.h"
  19 
  20 #define DRVNAME         "fb_bd663474"
  21 #define WIDTH           240
  22 #define HEIGHT          320
  23 #define BPP             16
  24 
  25 static int init_display(struct fbtft_par *par)
  26 {
  27         if (par->gpio.cs)
  28                 gpiod_set_value(par->gpio.cs, 0);  /* Activate chip */
  29 
  30         par->fbtftops.reset(par);
  31 
  32         /* Initialization sequence from Lib_UTFT */
  33 
  34         /* oscillator start */
  35         write_reg(par, 0x000, 0x0001);  /*oscillator 0: stop, 1: operation */
  36         mdelay(10);
  37 
  38         /* Power settings */
  39         write_reg(par, 0x100, 0x0000); /* power supply setup */
  40         write_reg(par, 0x101, 0x0000);
  41         write_reg(par, 0x102, 0x3110);
  42         write_reg(par, 0x103, 0xe200);
  43         write_reg(par, 0x110, 0x009d);
  44         write_reg(par, 0x111, 0x0022);
  45         write_reg(par, 0x100, 0x0120);
  46         mdelay(20);
  47 
  48         write_reg(par, 0x100, 0x3120);
  49         mdelay(80);
  50         /* Display control */
  51         write_reg(par, 0x001, 0x0100);
  52         write_reg(par, 0x002, 0x0000);
  53         write_reg(par, 0x003, 0x1230);
  54         write_reg(par, 0x006, 0x0000);
  55         write_reg(par, 0x007, 0x0101);
  56         write_reg(par, 0x008, 0x0808);
  57         write_reg(par, 0x009, 0x0000);
  58         write_reg(par, 0x00b, 0x0000);
  59         write_reg(par, 0x00c, 0x0000);
  60         write_reg(par, 0x00d, 0x0018);
  61         /* LTPS control settings */
  62         write_reg(par, 0x012, 0x0000);
  63         write_reg(par, 0x013, 0x0000);
  64         write_reg(par, 0x018, 0x0000);
  65         write_reg(par, 0x019, 0x0000);
  66 
  67         write_reg(par, 0x203, 0x0000);
  68         write_reg(par, 0x204, 0x0000);
  69 
  70         write_reg(par, 0x210, 0x0000);
  71         write_reg(par, 0x211, 0x00ef);
  72         write_reg(par, 0x212, 0x0000);
  73         write_reg(par, 0x213, 0x013f);
  74         write_reg(par, 0x214, 0x0000);
  75         write_reg(par, 0x215, 0x0000);
  76         write_reg(par, 0x216, 0x0000);
  77         write_reg(par, 0x217, 0x0000);
  78 
  79         /* Gray scale settings */
  80         write_reg(par, 0x300, 0x5343);
  81         write_reg(par, 0x301, 0x1021);
  82         write_reg(par, 0x302, 0x0003);
  83         write_reg(par, 0x303, 0x0011);
  84         write_reg(par, 0x304, 0x050a);
  85         write_reg(par, 0x305, 0x4342);
  86         write_reg(par, 0x306, 0x1100);
  87         write_reg(par, 0x307, 0x0003);
  88         write_reg(par, 0x308, 0x1201);
  89         write_reg(par, 0x309, 0x050a);
  90 
  91         /* RAM access settings */
  92         write_reg(par, 0x400, 0x4027);
  93         write_reg(par, 0x401, 0x0000);
  94         write_reg(par, 0x402, 0x0000);  /* First screen drive position (1) */
  95         write_reg(par, 0x403, 0x013f);  /* First screen drive position (2) */
  96         write_reg(par, 0x404, 0x0000);
  97 
  98         write_reg(par, 0x200, 0x0000);
  99         write_reg(par, 0x201, 0x0000);
 100         write_reg(par, 0x100, 0x7120);
 101         write_reg(par, 0x007, 0x0103);
 102         mdelay(10);
 103         write_reg(par, 0x007, 0x0113);
 104 
 105         return 0;
 106 }
 107 
 108 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
 109 {
 110         switch (par->info->var.rotate) {
 111         /* R200h = Horizontal GRAM Start Address */
 112         /* R201h = Vertical GRAM Start Address */
 113         case 0:
 114                 write_reg(par, 0x0200, xs);
 115                 write_reg(par, 0x0201, ys);
 116                 break;
 117         case 180:
 118                 write_reg(par, 0x0200, WIDTH - 1 - xs);
 119                 write_reg(par, 0x0201, HEIGHT - 1 - ys);
 120                 break;
 121         case 270:
 122                 write_reg(par, 0x0200, WIDTH - 1 - ys);
 123                 write_reg(par, 0x0201, xs);
 124                 break;
 125         case 90:
 126                 write_reg(par, 0x0200, ys);
 127                 write_reg(par, 0x0201, HEIGHT - 1 - xs);
 128                 break;
 129         }
 130         write_reg(par, 0x202); /* Write Data to GRAM */
 131 }
 132 
 133 static int set_var(struct fbtft_par *par)
 134 {
 135         switch (par->info->var.rotate) {
 136         /* AM: GRAM update direction */
 137         case 0:
 138                 write_reg(par, 0x003, 0x1230);
 139                 break;
 140         case 180:
 141                 write_reg(par, 0x003, 0x1200);
 142                 break;
 143         case 270:
 144                 write_reg(par, 0x003, 0x1228);
 145                 break;
 146         case 90:
 147                 write_reg(par, 0x003, 0x1218);
 148                 break;
 149         }
 150 
 151         return 0;
 152 }
 153 
 154 static struct fbtft_display display = {
 155         .regwidth = 16,
 156         .width = WIDTH,
 157         .height = HEIGHT,
 158         .bpp = BPP,
 159         .fbtftops = {
 160                 .init_display = init_display,
 161                 .set_addr_win = set_addr_win,
 162                 .set_var = set_var,
 163         },
 164 };
 165 
 166 FBTFT_REGISTER_DRIVER(DRVNAME, "hitachi,bd663474", &display);
 167 
 168 MODULE_ALIAS("spi:" DRVNAME);
 169 MODULE_ALIAS("platform:" DRVNAME);
 170 MODULE_ALIAS("spi:bd663474");
 171 MODULE_ALIAS("platform:bd663474");
 172 
 173 MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller");
 174 MODULE_AUTHOR("Seong-Woo Kim");
 175 MODULE_LICENSE("GPL");