root/drivers/staging/vt6656/mac.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * File: mac.h
   7  *
   8  * Purpose: MAC routines
   9  *
  10  * Author: Tevin Chen
  11  *
  12  * Date: May 21, 1996
  13  *
  14  * Revision History:
  15  *      07-01-2003 Bryan YC Fan:  Re-write codes to support VT3253 spec.
  16  *      08-25-2003 Kyle Hsu:      Porting MAC functions from sim53.
  17  *      09-03-2003 Bryan YC Fan:  Add MACvDisableProtectMD & MACvEnableProtectMD
  18  */
  19 
  20 #ifndef __MAC_H__
  21 #define __MAC_H__
  22 
  23 #include "device.h"
  24 
  25 #define REV_ID_VT3253_A0        0x00
  26 #define REV_ID_VT3253_A1        0x01
  27 #define REV_ID_VT3253_B0        0x08
  28 #define REV_ID_VT3253_B1        0x09
  29 
  30 /* Registers in the MAC */
  31 #define MAC_REG_BISTCMD         0x04
  32 #define MAC_REG_BISTSR0         0x05
  33 #define MAC_REG_BISTSR1         0x06
  34 #define MAC_REG_BISTSR2         0x07
  35 #define MAC_REG_I2MCSR          0x08
  36 #define MAC_REG_I2MTGID         0x09
  37 #define MAC_REG_I2MTGAD         0x0a
  38 #define MAC_REG_I2MCFG          0x0b
  39 #define MAC_REG_I2MDIPT         0x0c
  40 #define MAC_REG_I2MDOPT         0x0e
  41 #define MAC_REG_USBSUS          0x0f
  42 
  43 #define MAC_REG_LOCALID         0x14
  44 #define MAC_REG_TESTCFG         0x15
  45 #define MAC_REG_JUMPER0         0x16
  46 #define MAC_REG_JUMPER1         0x17
  47 #define MAC_REG_TMCTL           0x18
  48 #define MAC_REG_TMDATA0         0x1c
  49 #define MAC_REG_TMDATA1         0x1d
  50 #define MAC_REG_TMDATA2         0x1e
  51 #define MAC_REG_TMDATA3         0x1f
  52 
  53 /* MAC Parameter related */
  54 #define MAC_REG_LRT             0x20
  55 #define MAC_REG_SRT             0x21
  56 #define MAC_REG_SIFS            0x22
  57 #define MAC_REG_DIFS            0x23
  58 #define MAC_REG_EIFS            0x24
  59 #define MAC_REG_SLOT            0x25
  60 #define MAC_REG_BI              0x26
  61 #define MAC_REG_CWMAXMIN0       0x28
  62 #define MAC_REG_LINKOFFTOTM     0x2a
  63 #define MAC_REG_SWTMOT          0x2b
  64 #define MAC_REG_RTSOKCNT        0x2c
  65 #define MAC_REG_RTSFAILCNT      0x2d
  66 #define MAC_REG_ACKFAILCNT      0x2e
  67 #define MAC_REG_FCSERRCNT       0x2f
  68 
  69 /* TSF Related */
  70 #define MAC_REG_TSFCNTR         0x30
  71 #define MAC_REG_NEXTTBTT        0x38
  72 #define MAC_REG_TSFOFST         0x40
  73 #define MAC_REG_TFTCTL          0x48
  74 
  75 /* WMAC Control/Status Related */
  76 #define MAC_REG_ENCFG0          0x4c
  77 #define MAC_REG_ENCFG1          0x4d
  78 #define MAC_REG_ENCFG2          0x4e
  79 
  80 #define MAC_REG_CFG             0x50
  81 #define MAC_REG_TEST            0x52
  82 #define MAC_REG_HOSTCR          0x54
  83 #define MAC_REG_MACCR           0x55
  84 #define MAC_REG_RCR             0x56
  85 #define MAC_REG_TCR             0x57
  86 #define MAC_REG_IMR             0x58
  87 #define MAC_REG_ISR             0x5c
  88 #define MAC_REG_ISR1            0x5d
  89 
  90 /* Power Saving Related */
  91 #define MAC_REG_PSCFG           0x60
  92 #define MAC_REG_PSCTL           0x61
  93 #define MAC_REG_PSPWRSIG        0x62
  94 #define MAC_REG_BBCR13          0x63
  95 #define MAC_REG_AIDATIM         0x64
  96 #define MAC_REG_PWBT            0x66
  97 #define MAC_REG_WAKEOKTMR       0x68
  98 #define MAC_REG_CALTMR          0x69
  99 #define MAC_REG_SYNSPACCNT      0x6a
 100 #define MAC_REG_WAKSYNOPT       0x6b
 101 
 102 /* Baseband/IF Control Group */
 103 #define MAC_REG_BBREGCTL        0x6c
 104 #define MAC_REG_CHANNEL         0x6d
 105 #define MAC_REG_BBREGADR        0x6e
 106 #define MAC_REG_BBREGDATA       0x6f
 107 #define MAC_REG_IFREGCTL        0x70
 108 #define MAC_REG_IFDATA          0x71
 109 #define MAC_REG_ITRTMSET        0x74
 110 #define MAC_REG_PAPEDELAY       0x77
 111 #define MAC_REG_SOFTPWRCTL      0x78
 112 #define MAC_REG_SOFTPWRCTL2     0x79
 113 #define MAC_REG_GPIOCTL0        0x7a
 114 #define MAC_REG_GPIOCTL1        0x7b
 115 
 116 /* MiscFF PIO related */
 117 #define MAC_REG_MISCFFNDEX      0xbc
 118 #define MAC_REG_MISCFFCTL       0xbe
 119 #define MAC_REG_MISCFFDATA      0xc0
 120 
 121 /* MAC Configuration Group */
 122 #define MAC_REG_PAR0            0xc4
 123 #define MAC_REG_PAR4            0xc8
 124 #define MAC_REG_BSSID0          0xcc
 125 #define MAC_REG_BSSID4          0xd0
 126 #define MAC_REG_MAR0            0xd4
 127 #define MAC_REG_MAR4            0xd8
 128 
 129 /* MAC RSPPKT INFO Group */
 130 #define MAC_REG_RSPINF_B_1      0xdC
 131 #define MAC_REG_RSPINF_B_2      0xe0
 132 #define MAC_REG_RSPINF_B_5      0xe4
 133 #define MAC_REG_RSPINF_B_11     0xe8
 134 #define MAC_REG_RSPINF_A_6      0xec
 135 #define MAC_REG_RSPINF_A_9      0xee
 136 #define MAC_REG_RSPINF_A_12     0xf0
 137 #define MAC_REG_RSPINF_A_18     0xf2
 138 #define MAC_REG_RSPINF_A_24     0xf4
 139 #define MAC_REG_RSPINF_A_36     0xf6
 140 #define MAC_REG_RSPINF_A_48     0xf8
 141 #define MAC_REG_RSPINF_A_54     0xfa
 142 #define MAC_REG_RSPINF_A_72     0xfc
 143 
 144 /* Bits in the I2MCFG EEPROM register */
 145 #define I2MCFG_BOUNDCTL         0x80
 146 #define I2MCFG_WAITCTL          0x20
 147 #define I2MCFG_SCLOECTL         0x10
 148 #define I2MCFG_WBUSYCTL         0x08
 149 #define I2MCFG_NORETRY          0x04
 150 #define I2MCFG_I2MLDSEQ         0x02
 151 #define I2MCFG_I2CMFAST         0x01
 152 
 153 /* Bits in the I2MCSR EEPROM register */
 154 #define I2MCSR_EEMW             0x80
 155 #define I2MCSR_EEMR             0x40
 156 #define I2MCSR_AUTOLD           0x08
 157 #define I2MCSR_NACK             0x02
 158 #define I2MCSR_DONE             0x01
 159 
 160 /* Bits in the TMCTL register */
 161 #define TMCTL_TSUSP             0x04
 162 #define TMCTL_TMD               0x02
 163 #define TMCTL_TE                0x01
 164 
 165 /* Bits in the TFTCTL register */
 166 #define TFTCTL_HWUTSF           0x80
 167 #define TFTCTL_TBTTSYNC         0x40
 168 #define TFTCTL_HWUTSFEN         0x20
 169 #define TFTCTL_TSFCNTRRD        0x10
 170 #define TFTCTL_TBTTSYNCEN       0x08
 171 #define TFTCTL_TSFSYNCEN        0x04
 172 #define TFTCTL_TSFCNTRST        0x02
 173 #define TFTCTL_TSFCNTREN        0x01
 174 
 175 /* Bits in the EnhanceCFG_0 register */
 176 #define EnCFG_BBType_a          0x00
 177 #define EnCFG_BBType_b          0x01
 178 #define EnCFG_BBType_g          0x02
 179 #define EnCFG_BBType_MASK       0x03
 180 #define EnCFG_ProtectMd         0x20
 181 
 182 /* Bits in the EnhanceCFG_1 register */
 183 #define EnCFG_BcnSusInd         0x01
 184 #define EnCFG_BcnSusClr         0x02
 185 
 186 /* Bits in the EnhanceCFG_2 register */
 187 #define EnCFG_NXTBTTCFPSTR      0x01
 188 #define EnCFG_BarkerPream       0x02
 189 #define EnCFG_PktBurstMode      0x04
 190 
 191 /* Bits in the CFG register */
 192 #define CFG_TKIPOPT             0x80
 193 #define CFG_RXDMAOPT            0x40
 194 #define CFG_TMOT_SW             0x20
 195 #define CFG_TMOT_HWLONG         0x10
 196 #define CFG_TMOT_HW             0x00
 197 #define CFG_CFPENDOPT           0x08
 198 #define CFG_BCNSUSEN            0x04
 199 #define CFG_NOTXTIMEOUT         0x02
 200 #define CFG_NOBUFOPT            0x01
 201 
 202 /* Bits in the TEST register */
 203 #define TEST_LBEXT              0x80
 204 #define TEST_LBINT              0x40
 205 #define TEST_LBNONE             0x00
 206 #define TEST_SOFTINT            0x20
 207 #define TEST_CONTTX             0x10
 208 #define TEST_TXPE               0x08
 209 #define TEST_NAVDIS             0x04
 210 #define TEST_NOCTS              0x02
 211 #define TEST_NOACK              0x01
 212 
 213 /* Bits in the HOSTCR register */
 214 #define HOSTCR_TXONST           0x80
 215 #define HOSTCR_RXONST           0x40
 216 #define HOSTCR_ADHOC            0x20
 217 #define HOSTCR_AP               0x10
 218 #define HOSTCR_TXON             0x08
 219 #define HOSTCR_RXON             0x04
 220 #define HOSTCR_MACEN            0x02
 221 #define HOSTCR_SOFTRST          0x01
 222 
 223 /* Bits in the MACCR register */
 224 #define MACCR_SYNCFLUSHOK       0x04
 225 #define MACCR_SYNCFLUSH         0x02
 226 #define MACCR_CLRNAV            0x01
 227 
 228 /* Bits in the RCR register */
 229 #define RCR_SSID                0x80
 230 #define RCR_RXALLTYPE           0x40
 231 #define RCR_UNICAST             0x20
 232 #define RCR_BROADCAST           0x10
 233 #define RCR_MULTICAST           0x08
 234 #define RCR_WPAERR              0x04
 235 #define RCR_ERRCRC              0x02
 236 #define RCR_BSSID               0x01
 237 
 238 /* Bits in the TCR register */
 239 #define TCR_SYNCDCFOPT          0x02
 240 #define TCR_AUTOBCNTX           0x01
 241 
 242 /* ISR1 */
 243 #define ISR_GPIO3               0x40
 244 #define ISR_RXNOBUF             0x08
 245 #define ISR_MIBNEARFULL         0x04
 246 #define ISR_SOFTINT             0x02
 247 #define ISR_FETALERR            0x01
 248 
 249 #define LEDSTS_STS              0x06
 250 #define LEDSTS_TMLEN            0x78
 251 #define LEDSTS_OFF              0x00
 252 #define LEDSTS_ON               0x02
 253 #define LEDSTS_SLOW             0x04
 254 #define LEDSTS_INTER            0x06
 255 
 256 /* ISR0 */
 257 #define ISR_WATCHDOG            0x80
 258 #define ISR_SOFTTIMER           0x40
 259 #define ISR_GPIO0               0x20
 260 #define ISR_TBTT                0x10
 261 #define ISR_RXDMA0              0x08
 262 #define ISR_BNTX                0x04
 263 #define ISR_ACTX                0x01
 264 
 265 /* Bits in the PSCFG register */
 266 #define PSCFG_PHILIPMD          0x40
 267 #define PSCFG_WAKECALEN         0x20
 268 #define PSCFG_WAKETMREN         0x10
 269 #define PSCFG_BBPSPROG          0x08
 270 #define PSCFG_WAKESYN           0x04
 271 #define PSCFG_SLEEPSYN          0x02
 272 #define PSCFG_AUTOSLEEP         0x01
 273 
 274 /* Bits in the PSCTL register */
 275 #define PSCTL_WAKEDONE          0x20
 276 #define PSCTL_PS                0x10
 277 #define PSCTL_GO2DOZE           0x08
 278 #define PSCTL_LNBCN             0x04
 279 #define PSCTL_ALBCN             0x02
 280 #define PSCTL_PSEN              0x01
 281 
 282 /* Bits in the PSPWSIG register */
 283 #define PSSIG_WPE3              0x80
 284 #define PSSIG_WPE2              0x40
 285 #define PSSIG_WPE1              0x20
 286 #define PSSIG_WRADIOPE          0x10
 287 #define PSSIG_SPE3              0x08
 288 #define PSSIG_SPE2              0x04
 289 #define PSSIG_SPE1              0x02
 290 #define PSSIG_SRADIOPE          0x01
 291 
 292 /* Bits in the BBREGCTL register */
 293 #define BBREGCTL_DONE           0x04
 294 #define BBREGCTL_REGR           0x02
 295 #define BBREGCTL_REGW           0x01
 296 
 297 /* Bits in the IFREGCTL register */
 298 #define IFREGCTL_DONE           0x04
 299 #define IFREGCTL_IFRF           0x02
 300 #define IFREGCTL_REGW           0x01
 301 
 302 /* Bits in the SOFTPWRCTL register */
 303 #define SOFTPWRCTL_RFLEOPT      0x08
 304 #define SOFTPWRCTL_TXPEINV      0x02
 305 #define SOFTPWRCTL_SWPECTI      0x01
 306 #define SOFTPWRCTL_SWPAPE       0x20
 307 #define SOFTPWRCTL_SWCALEN      0x10
 308 #define SOFTPWRCTL_SWRADIO_PE   0x08
 309 #define SOFTPWRCTL_SWPE2        0x04
 310 #define SOFTPWRCTL_SWPE1        0x02
 311 #define SOFTPWRCTL_SWPE3        0x01
 312 
 313 /* Bits in the GPIOCTL1 register */
 314 #define GPIO3_MD                0x20
 315 #define GPIO3_DATA              0x40
 316 #define GPIO3_INTMD             0x80
 317 
 318 /* Bits in the MISCFFCTL register */
 319 #define MISCFFCTL_WRITE         0x0001
 320 
 321 /* Loopback mode */
 322 #define MAC_LB_EXT              0x02
 323 #define MAC_LB_INTERNAL         0x01
 324 #define MAC_LB_NONE             0x00
 325 
 326 /* Ethernet address filter type */
 327 #define PKT_TYPE_NONE           0x00 /* turn off receiver */
 328 #define PKT_TYPE_ALL_MULTICAST  0x80
 329 #define PKT_TYPE_PROMISCUOUS    0x40
 330 #define PKT_TYPE_DIRECTED       0x20 /* obselete */
 331 #define PKT_TYPE_BROADCAST      0x10
 332 #define PKT_TYPE_MULTICAST      0x08
 333 #define PKT_TYPE_ERROR_WPA      0x04
 334 #define PKT_TYPE_ERROR_CRC      0x02
 335 #define PKT_TYPE_BSSID          0x01
 336 
 337 #define Default_BI              0x200
 338 
 339 /* MiscFIFO Offset */
 340 #define MISCFIFO_KEYETRY0       32
 341 #define MISCFIFO_KEYENTRYSIZE   22
 342 
 343 #define MAC_REVISION_A0         0x00
 344 #define MAC_REVISION_A1         0x01
 345 
 346 struct vnt_mac_set_key {
 347         union {
 348                 struct {
 349                         u8 addr[ETH_ALEN];
 350                         __le16 key_ctl;
 351                 } write __packed;
 352                 u32 swap[2];
 353         } u;
 354         u8 key[WLAN_KEY_LEN_CCMP];
 355 } __packed;
 356 
 357 void vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter);
 358 void vnt_mac_shutdown(struct vnt_private *priv);
 359 void vnt_mac_set_bb_type(struct vnt_private *priv, u8 type);
 360 void vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx);
 361 void vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx,
 362                           u32 key_idx, u8 *addr, u8 *key);
 363 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
 364 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
 365 void vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);
 366 void vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr);
 367 void vnt_mac_enable_protect_mode(struct vnt_private *priv);
 368 void vnt_mac_disable_protect_mode(struct vnt_private *priv);
 369 void vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv);
 370 void vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv);
 371 void vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval);
 372 int vnt_mac_set_led(struct vnt_private *privpriv, u8 state, u8 led);
 373 
 374 #endif /* __MAC_H__ */