This source file includes following definitions.
- xgene_gpio_set_bit
- xgene_gpio_sb_irq_set_type
- xgene_gpio_sb_to_irq
- xgene_gpio_sb_domain_activate
- xgene_gpio_sb_domain_deactivate
- xgene_gpio_sb_domain_translate
- xgene_gpio_sb_domain_alloc
- xgene_gpio_sb_probe
- xgene_gpio_sb_remove
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11 #include <linux/module.h>
12 #include <linux/io.h>
13 #include <linux/platform_device.h>
14 #include <linux/of_gpio.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/acpi.h>
17
18 #include "gpiolib.h"
19 #include "gpiolib-acpi.h"
20
21
22 #define XGENE_NIRQ_PROPERTY "apm,nr-irqs"
23 #define XGENE_NGPIO_PROPERTY "apm,nr-gpios"
24 #define XGENE_IRQ_START_PROPERTY "apm,irq-start"
25
26 #define XGENE_DFLT_MAX_NGPIO 22
27 #define XGENE_DFLT_MAX_NIRQ 6
28 #define XGENE_DFLT_IRQ_START_PIN 8
29 #define GPIO_MASK(x) (1U << ((x) % 32))
30
31 #define MPA_GPIO_INT_LVL 0x0290
32 #define MPA_GPIO_OE_ADDR 0x029c
33 #define MPA_GPIO_OUT_ADDR 0x02a0
34 #define MPA_GPIO_IN_ADDR 0x02a4
35 #define MPA_GPIO_SEL_LO 0x0294
36
37 #define GPIO_INT_LEVEL_H 0x000001
38 #define GPIO_INT_LEVEL_L 0x000000
39
40
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46
47
48
49 struct xgene_gpio_sb {
50 struct gpio_chip gc;
51 void __iomem *regs;
52 struct irq_domain *irq_domain;
53 u16 irq_start;
54 u16 nirq;
55 u16 parent_irq_base;
56 };
57
58 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
59 #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
60
61 static void xgene_gpio_set_bit(struct gpio_chip *gc,
62 void __iomem *reg, u32 gpio, int val)
63 {
64 u32 data;
65
66 data = gc->read_reg(reg);
67 if (val)
68 data |= GPIO_MASK(gpio);
69 else
70 data &= ~GPIO_MASK(gpio);
71 gc->write_reg(reg, data);
72 }
73
74 static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
75 {
76 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
77 int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
78 int lvl_type = GPIO_INT_LEVEL_H;
79
80 switch (type & IRQ_TYPE_SENSE_MASK) {
81 case IRQ_TYPE_EDGE_RISING:
82 case IRQ_TYPE_LEVEL_HIGH:
83 lvl_type = GPIO_INT_LEVEL_H;
84 break;
85 case IRQ_TYPE_EDGE_FALLING:
86 case IRQ_TYPE_LEVEL_LOW:
87 lvl_type = GPIO_INT_LEVEL_L;
88 break;
89 default:
90 break;
91 }
92
93 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
94 gpio * 2, 1);
95 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
96 d->hwirq, lvl_type);
97
98
99 if (type & IRQ_TYPE_EDGE_BOTH)
100 return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
101 else
102 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
103 }
104
105 static struct irq_chip xgene_gpio_sb_irq_chip = {
106 .name = "sbgpio",
107 .irq_eoi = irq_chip_eoi_parent,
108 .irq_mask = irq_chip_mask_parent,
109 .irq_unmask = irq_chip_unmask_parent,
110 .irq_set_type = xgene_gpio_sb_irq_set_type,
111 };
112
113 static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
114 {
115 struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
116 struct irq_fwspec fwspec;
117
118 if ((gpio < priv->irq_start) ||
119 (gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
120 return -ENXIO;
121
122 fwspec.fwnode = gc->parent->fwnode;
123 fwspec.param_count = 2;
124 fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
125 fwspec.param[1] = IRQ_TYPE_NONE;
126 return irq_create_fwspec_mapping(&fwspec);
127 }
128
129 static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
130 struct irq_data *irq_data,
131 bool reserve)
132 {
133 struct xgene_gpio_sb *priv = d->host_data;
134 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
135 int ret;
136
137 ret = gpiochip_lock_as_irq(&priv->gc, gpio);
138 if (ret) {
139 dev_err(priv->gc.parent,
140 "Unable to configure XGene GPIO standby pin %d as IRQ\n",
141 gpio);
142 return ret;
143 }
144
145 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
146 gpio * 2, 1);
147 return 0;
148 }
149
150 static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
151 struct irq_data *irq_data)
152 {
153 struct xgene_gpio_sb *priv = d->host_data;
154 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
155
156 gpiochip_unlock_as_irq(&priv->gc, gpio);
157 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
158 gpio * 2, 0);
159 }
160
161 static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
162 struct irq_fwspec *fwspec,
163 unsigned long *hwirq,
164 unsigned int *type)
165 {
166 struct xgene_gpio_sb *priv = d->host_data;
167
168 if ((fwspec->param_count != 2) ||
169 (fwspec->param[0] >= priv->nirq))
170 return -EINVAL;
171 *hwirq = fwspec->param[0];
172 *type = fwspec->param[1];
173 return 0;
174 }
175
176 static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
177 unsigned int virq,
178 unsigned int nr_irqs, void *data)
179 {
180 struct irq_fwspec *fwspec = data;
181 struct irq_fwspec parent_fwspec;
182 struct xgene_gpio_sb *priv = domain->host_data;
183 irq_hw_number_t hwirq;
184 unsigned int i;
185
186 hwirq = fwspec->param[0];
187 for (i = 0; i < nr_irqs; i++)
188 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
189 &xgene_gpio_sb_irq_chip, priv);
190
191 parent_fwspec.fwnode = domain->parent->fwnode;
192 if (is_of_node(parent_fwspec.fwnode)) {
193 parent_fwspec.param_count = 3;
194 parent_fwspec.param[0] = 0;
195
196 parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
197 parent_fwspec.param[2] = fwspec->param[1];
198 } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
199 parent_fwspec.param_count = 2;
200 parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
201 parent_fwspec.param[1] = fwspec->param[1];
202 } else
203 return -EINVAL;
204
205 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
206 &parent_fwspec);
207 }
208
209 static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
210 .translate = xgene_gpio_sb_domain_translate,
211 .alloc = xgene_gpio_sb_domain_alloc,
212 .free = irq_domain_free_irqs_common,
213 .activate = xgene_gpio_sb_domain_activate,
214 .deactivate = xgene_gpio_sb_domain_deactivate,
215 };
216
217 static int xgene_gpio_sb_probe(struct platform_device *pdev)
218 {
219 struct xgene_gpio_sb *priv;
220 int ret;
221 void __iomem *regs;
222 struct irq_domain *parent_domain = NULL;
223 u32 val32;
224
225 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
226 if (!priv)
227 return -ENOMEM;
228
229 regs = devm_platform_ioremap_resource(pdev, 0);
230 if (IS_ERR(regs))
231 return PTR_ERR(regs);
232
233 priv->regs = regs;
234
235 ret = platform_get_irq(pdev, 0);
236 if (ret > 0) {
237 priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
238 parent_domain = irq_get_irq_data(ret)->domain;
239 }
240 if (!parent_domain) {
241 dev_err(&pdev->dev, "unable to obtain parent domain\n");
242 return -ENODEV;
243 }
244
245 ret = bgpio_init(&priv->gc, &pdev->dev, 4,
246 regs + MPA_GPIO_IN_ADDR,
247 regs + MPA_GPIO_OUT_ADDR, NULL,
248 regs + MPA_GPIO_OE_ADDR, NULL, 0);
249 if (ret)
250 return ret;
251
252 priv->gc.to_irq = xgene_gpio_sb_to_irq;
253
254
255 priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
256 if (!device_property_read_u32(&pdev->dev,
257 XGENE_IRQ_START_PROPERTY, &val32))
258 priv->irq_start = val32;
259
260
261 priv->nirq = XGENE_DFLT_MAX_NIRQ;
262 if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
263 priv->nirq = val32;
264
265
266 priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
267 if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
268 priv->gc.ngpio = val32;
269
270 dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
271 priv->gc.ngpio, priv->nirq, priv->irq_start);
272
273 platform_set_drvdata(pdev, priv);
274
275 priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
276 0, priv->nirq, pdev->dev.fwnode,
277 &xgene_gpio_sb_domain_ops, priv);
278 if (!priv->irq_domain)
279 return -ENODEV;
280
281 priv->gc.irq.domain = priv->irq_domain;
282
283 ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
284 if (ret) {
285 dev_err(&pdev->dev,
286 "failed to register X-Gene GPIO Standby driver\n");
287 irq_domain_remove(priv->irq_domain);
288 return ret;
289 }
290
291 dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
292
293 if (priv->nirq > 0) {
294
295 acpi_gpiochip_request_interrupts(&priv->gc);
296 }
297
298 return ret;
299 }
300
301 static int xgene_gpio_sb_remove(struct platform_device *pdev)
302 {
303 struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
304
305 if (priv->nirq > 0) {
306 acpi_gpiochip_free_interrupts(&priv->gc);
307 }
308
309 irq_domain_remove(priv->irq_domain);
310
311 return 0;
312 }
313
314 static const struct of_device_id xgene_gpio_sb_of_match[] = {
315 {.compatible = "apm,xgene-gpio-sb", },
316 {},
317 };
318 MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
319
320 #ifdef CONFIG_ACPI
321 static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
322 {"APMC0D15", 0},
323 {},
324 };
325 MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
326 #endif
327
328 static struct platform_driver xgene_gpio_sb_driver = {
329 .driver = {
330 .name = "xgene-gpio-sb",
331 .of_match_table = xgene_gpio_sb_of_match,
332 .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
333 },
334 .probe = xgene_gpio_sb_probe,
335 .remove = xgene_gpio_sb_remove,
336 };
337 module_platform_driver(xgene_gpio_sb_driver);
338
339 MODULE_AUTHOR("AppliedMicro");
340 MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
341 MODULE_LICENSE("GPL");