root/drivers/gpio/gpio-grgpio.c

DEFINITIONS

1. grgpio_set_imask
2. grgpio_to_irq
3. grgpio_irq_set_type
4. grgpio_irq_mask
5. grgpio_irq_unmask
6. grgpio_irq_handler
7. grgpio_irq_map
8. grgpio_irq_unmap
9. grgpio_probe
10. grgpio_remove

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
   4  *
   5  * 2013 (c) Aeroflex Gaisler AB
   6  *
   7  * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
   8  * IP core library.
   9  *
  10  * Full documentation of the GRGPIO core can be found here:
  11  * http://www.gaisler.com/products/grlib/grip.pdf
  12  *
  13  * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
  14  * information on open firmware properties.
  15  *
  16  * Contributors: Andreas Larsson <andreas@gaisler.com>
  17  */
  18 
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/gpio/driver.h>
  27 #include <linux/slab.h>
  28 #include <linux/err.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/irqdomain.h>
  32 #include <linux/bitops.h>
  33 
  34 #define GRGPIO_MAX_NGPIO 32
  35 
  36 #define GRGPIO_DATA             0x00
  37 #define GRGPIO_OUTPUT           0x04
  38 #define GRGPIO_DIR              0x08
  39 #define GRGPIO_IMASK            0x0c
  40 #define GRGPIO_IPOL             0x10
  41 #define GRGPIO_IEDGE            0x14
  42 #define GRGPIO_BYPASS           0x18
  43 #define GRGPIO_IMAP_BASE        0x20
  44 
  45 /* Structure for an irq of the core - called an underlying irq */
  46 struct grgpio_uirq {
  47         u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
  48         u8 uirq; /* Underlying irq of the gpio driver */
  49 };
  50 
  51 /*
  52  * Structure for an irq of a gpio line handed out by this driver. The index is
  53  * used to map to the corresponding underlying irq.
  54  */
  55 struct grgpio_lirq {
  56         s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
  57         u8 irq; /* irq for the gpio line */
  58 };
  59 
  60 struct grgpio_priv {
  61         struct gpio_chip gc;
  62         void __iomem *regs;
  63         struct device *dev;
  64 
  65         u32 imask; /* irq mask shadow register */
  66 
  67         /*
  68          * The grgpio core can have multiple "underlying" irqs. The gpio lines
  69          * can be mapped to any one or none of these underlying irqs
  70          * independently of each other. This driver sets up an irq domain and
  71          * hands out separate irqs to each gpio line
  72          */
  73         struct irq_domain *domain;
  74 
  75         /*
  76          * This array contains information on each underlying irq, each
  77          * irq of the grgpio core itself.
  78          */
  79         struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
  80 
  81         /*
  82          * This array contains information for each gpio line on the irqs
  83          * obtains from this driver. An index value of -1 for a certain gpio
  84          * line indicates that the line has no irq. Otherwise the index connects
  85          * the irq to the underlying irq by pointing into the uirqs array.
  86          */
  87         struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
  88 };
  89 
  90 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
  91                              int val)
  92 {
  93         struct gpio_chip *gc = &priv->gc;
  94 
  95         if (val)
  96                 priv->imask |= BIT(offset);
  97         else
  98                 priv->imask &= ~BIT(offset);
  99         gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
 100 }
 101 
 102 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
 103 {
 104         struct grgpio_priv *priv = gpiochip_get_data(gc);
 105 
 106         if (offset >= gc->ngpio)
 107                 return -ENXIO;
 108 
 109         if (priv->lirqs[offset].index < 0)
 110                 return -ENXIO;
 111 
 112         return irq_create_mapping(priv->domain, offset);
 113 }
 114 
 115 /* -------------------- IRQ chip functions -------------------- */
 116 
 117 static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
 118 {
 119         struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
 120         unsigned long flags;
 121         u32 mask = BIT(d->hwirq);
 122         u32 ipol;
 123         u32 iedge;
 124         u32 pol;
 125         u32 edge;
 126 
 127         switch (type) {
 128         case IRQ_TYPE_LEVEL_LOW:
 129                 pol = 0;
 130                 edge = 0;
 131                 break;
 132         case IRQ_TYPE_LEVEL_HIGH:
 133                 pol = mask;
 134                 edge = 0;
 135                 break;
 136         case IRQ_TYPE_EDGE_FALLING:
 137                 pol = 0;
 138                 edge = mask;
 139                 break;
 140         case IRQ_TYPE_EDGE_RISING:
 141                 pol = mask;
 142                 edge = mask;
 143                 break;
 144         default:
 145                 return -EINVAL;
 146         }
 147 
 148         spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
 149 
 150         ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
 151         iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
 152 
 153         priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
 154         priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
 155 
 156         spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 157 
 158         return 0;
 159 }
 160 
 161 static void grgpio_irq_mask(struct irq_data *d)
 162 {
 163         struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
 164         int offset = d->hwirq;
 165         unsigned long flags;
 166 
 167         spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
 168 
 169         grgpio_set_imask(priv, offset, 0);
 170 
 171         spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 172 }
 173 
 174 static void grgpio_irq_unmask(struct irq_data *d)
 175 {
 176         struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
 177         int offset = d->hwirq;
 178         unsigned long flags;
 179 
 180         spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
 181 
 182         grgpio_set_imask(priv, offset, 1);
 183 
 184         spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 185 }
 186 
 187 static struct irq_chip grgpio_irq_chip = {
 188         .name                   = "grgpio",
 189         .irq_mask               = grgpio_irq_mask,
 190         .irq_unmask             = grgpio_irq_unmask,
 191         .irq_set_type           = grgpio_irq_set_type,
 192 };
 193 
 194 static irqreturn_t grgpio_irq_handler(int irq, void *dev)
 195 {
 196         struct grgpio_priv *priv = dev;
 197         int ngpio = priv->gc.ngpio;
 198         unsigned long flags;
 199         int i;
 200         int match = 0;
 201 
 202         spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
 203 
 204         /*
 205          * For each gpio line, call its interrupt handler if it its underlying
 206          * irq matches the current irq that is handled.
 207          */
 208         for (i = 0; i < ngpio; i++) {
 209                 struct grgpio_lirq *lirq = &priv->lirqs[i];
 210 
 211                 if (priv->imask & BIT(i) && lirq->index >= 0 &&
 212                     priv->uirqs[lirq->index].uirq == irq) {
 213                         generic_handle_irq(lirq->irq);
 214                         match = 1;
 215                 }
 216         }
 217 
 218         spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 219 
 220         if (!match)
 221                 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
 222 
 223         return IRQ_HANDLED;
 224 }
 225 
 226 /*
 227  * This function will be called as a consequence of the call to
 228  * irq_create_mapping in grgpio_to_irq
 229  */
 230 static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
 231                           irq_hw_number_t hwirq)
 232 {
 233         struct grgpio_priv *priv = d->host_data;
 234         struct grgpio_lirq *lirq;
 235         struct grgpio_uirq *uirq;
 236         unsigned long flags;
 237         int offset = hwirq;
 238         int ret = 0;
 239 
 240         if (!priv)
 241                 return -EINVAL;
 242 
 243         lirq = &priv->lirqs[offset];
 244         if (lirq->index < 0)
 245                 return -EINVAL;
 246 
 247         dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
 248                 irq, offset);
 249 
 250         spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
 251 
 252         /* Request underlying irq if not already requested */
 253         lirq->irq = irq;
 254         uirq = &priv->uirqs[lirq->index];
 255         if (uirq->refcnt == 0) {
 256                 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 257                 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
 258                                   dev_name(priv->dev), priv);
 259                 if (ret) {
 260                         dev_err(priv->dev,
 261                                 "Could not request underlying irq %d\n",
 262                                 uirq->uirq);
 263                         return ret;
 264                 }
 265                 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
 266         }
 267         uirq->refcnt++;
 268 
 269         spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 270 
 271         /* Setup irq  */
 272         irq_set_chip_data(irq, priv);
 273         irq_set_chip_and_handler(irq, &grgpio_irq_chip,
 274                                  handle_simple_irq);
 275         irq_set_noprobe(irq);
 276 
 277         return ret;
 278 }
 279 
 280 static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
 281 {
 282         struct grgpio_priv *priv = d->host_data;
 283         int index;
 284         struct grgpio_lirq *lirq;
 285         struct grgpio_uirq *uirq;
 286         unsigned long flags;
 287         int ngpio = priv->gc.ngpio;
 288         int i;
 289 
 290         irq_set_chip_and_handler(irq, NULL, NULL);
 291         irq_set_chip_data(irq, NULL);
 292 
 293         spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
 294 
 295         /* Free underlying irq if last user unmapped */
 296         index = -1;
 297         for (i = 0; i < ngpio; i++) {
 298                 lirq = &priv->lirqs[i];
 299                 if (lirq->irq == irq) {
 300                         grgpio_set_imask(priv, i, 0);
 301                         lirq->irq = 0;
 302                         index = lirq->index;
 303                         break;
 304                 }
 305         }
 306         WARN_ON(index < 0);
 307 
 308         if (index >= 0) {
 309                 uirq = &priv->uirqs[lirq->index];
 310                 uirq->refcnt--;
 311                 if (uirq->refcnt == 0) {
 312                         spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 313                         free_irq(uirq->uirq, priv);
 314                         return;
 315                 }
 316         }
 317 
 318         spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 319 }
 320 
 321 static const struct irq_domain_ops grgpio_irq_domain_ops = {
 322         .map    = grgpio_irq_map,
 323         .unmap  = grgpio_irq_unmap,
 324 };
 325 
 326 /* ------------------------------------------------------------ */
 327 
 328 static int grgpio_probe(struct platform_device *ofdev)
 329 {
 330         struct device_node *np = ofdev->dev.of_node;
 331         void  __iomem *regs;
 332         struct gpio_chip *gc;
 333         struct grgpio_priv *priv;
 334         int err;
 335         u32 prop;
 336         s32 *irqmap;
 337         int size;
 338         int i;
 339 
 340         priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
 341         if (!priv)
 342                 return -ENOMEM;
 343 
 344         regs = devm_platform_ioremap_resource(ofdev, 0);
 345         if (IS_ERR(regs))
 346                 return PTR_ERR(regs);
 347 
 348         gc = &priv->gc;
 349         err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
 350                          regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
 351                          BGPIOF_BIG_ENDIAN_BYTE_ORDER);
 352         if (err) {
 353                 dev_err(&ofdev->dev, "bgpio_init() failed\n");
 354                 return err;
 355         }
 356 
 357         priv->regs = regs;
 358         priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
 359         priv->dev = &ofdev->dev;
 360 
 361         gc->of_node = np;
 362         gc->owner = THIS_MODULE;
 363         gc->to_irq = grgpio_to_irq;
 364         gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
 365         gc->base = -1;
 366 
 367         err = of_property_read_u32(np, "nbits", &prop);
 368         if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
 369                 gc->ngpio = GRGPIO_MAX_NGPIO;
 370                 dev_dbg(&ofdev->dev,
 371                         "No or invalid nbits property: assume %d\n", gc->ngpio);
 372         } else {
 373                 gc->ngpio = prop;
 374         }
 375 
 376         /*
 377          * The irqmap contains the index values indicating which underlying irq,
 378          * if anyone, is connected to that line
 379          */
 380         irqmap = (s32 *)of_get_property(np, "irqmap", &size);
 381         if (irqmap) {
 382                 if (size < gc->ngpio) {
 383                         dev_err(&ofdev->dev,
 384                                 "irqmap shorter than ngpio (%d < %d)\n",
 385                                 size, gc->ngpio);
 386                         return -EINVAL;
 387                 }
 388 
 389                 priv->domain = irq_domain_add_linear(np, gc->ngpio,
 390                                                      &grgpio_irq_domain_ops,
 391                                                      priv);
 392                 if (!priv->domain) {
 393                         dev_err(&ofdev->dev, "Could not add irq domain\n");
 394                         return -EINVAL;
 395                 }
 396 
 397                 for (i = 0; i < gc->ngpio; i++) {
 398                         struct grgpio_lirq *lirq;
 399                         int ret;
 400 
 401                         lirq = &priv->lirqs[i];
 402                         lirq->index = irqmap[i];
 403 
 404                         if (lirq->index < 0)
 405                                 continue;
 406 
 407                         ret = platform_get_irq(ofdev, lirq->index);
 408                         if (ret <= 0) {
 409                                 /*
 410                                  * Continue without irq functionality for that
 411                                  * gpio line
 412                                  */
 413                                 continue;
 414                         }
 415                         priv->uirqs[lirq->index].uirq = ret;
 416                 }
 417         }
 418 
 419         platform_set_drvdata(ofdev, priv);
 420 
 421         err = gpiochip_add_data(gc, priv);
 422         if (err) {
 423                 dev_err(&ofdev->dev, "Could not add gpiochip\n");
 424                 if (priv->domain)
 425                         irq_domain_remove(priv->domain);
 426                 return err;
 427         }
 428 
 429         dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
 430                  priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
 431 
 432         return 0;
 433 }
 434 
 435 static int grgpio_remove(struct platform_device *ofdev)
 436 {
 437         struct grgpio_priv *priv = platform_get_drvdata(ofdev);
 438         unsigned long flags;
 439         int i;
 440         int ret = 0;
 441 
 442         spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
 443 
 444         if (priv->domain) {
 445                 for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
 446                         if (priv->uirqs[i].refcnt != 0) {
 447                                 ret = -EBUSY;
 448                                 goto out;
 449                         }
 450                 }
 451         }
 452 
 453         gpiochip_remove(&priv->gc);
 454 
 455         if (priv->domain)
 456                 irq_domain_remove(priv->domain);
 457 
 458 out:
 459         spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
 460 
 461         return ret;
 462 }
 463 
 464 static const struct of_device_id grgpio_match[] = {
 465         {.name = "GAISLER_GPIO"},
 466         {.name = "01_01a"},
 467         {},
 468 };
 469 
 470 MODULE_DEVICE_TABLE(of, grgpio_match);
 471 
 472 static struct platform_driver grgpio_driver = {
 473         .driver = {
 474                 .name = "grgpio",
 475                 .of_match_table = grgpio_match,
 476         },
 477         .probe = grgpio_probe,
 478         .remove = grgpio_remove,
 479 };
 480 module_platform_driver(grgpio_driver);
 481 
 482 MODULE_AUTHOR("Aeroflex Gaisler AB.");
 483 MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
 484 MODULE_LICENSE("GPL");