drivers/platform/x86/intel_scu

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This source file includes following definitions.
ipc_command
ipc_data_writel
ipc_read_status
ipc_data_readb
ipc_data_readl
busy_loop
ipc_wait_for_interrupt
intel_scu_ipc_check_status
pwr_reg_rdwr
intel_scu_ipc_ioread8
intel_scu_ipc_ioread16
intel_scu_ipc_ioread32
intel_scu_ipc_iowrite8
intel_scu_ipc_iowrite16
intel_scu_ipc_iowrite32
intel_scu_ipc_readv
intel_scu_ipc_writev
intel_scu_ipc_update_register
intel_scu_ipc_simple_command
intel_scu_ipc_command
intel_scu_ipc_raw_command
intel_scu_ipc_i2c_cntrl
ioc
ipc_probe
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Intel SCU IPC mechanism
   4  *
   5  * (C) Copyright 2008-2010,2015 Intel Corporation
   6  * Author: Sreedhara DS (sreedhara.ds@intel.com)
   7  *
   8  * SCU running in ARC processor communicates with other entity running in IA
   9  * core through IPC mechanism which in turn messaging between IA core ad SCU.
  10  * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
  11  * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
  12  * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
  13  * along with other APIs.
  14  */
  15 
  16 #include <linux/delay.h>
  17 #include <linux/device.h>
  18 #include <linux/errno.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/pm.h>
  23 #include <linux/sfi.h>
  24 
  25 #include <asm/intel-mid.h>
  26 #include <asm/intel_scu_ipc.h>
  27 
  28 /* IPC defines the following message types */
  29 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
  30 #define IPCMSG_BATTERY        0xEF /* Coulomb Counter Accumulator */
  31 #define IPCMSG_FW_UPDATE      0xFE /* Firmware update */
  32 #define IPCMSG_PCNTRL         0xFF /* Power controller unit read/write */
  33 #define IPCMSG_FW_REVISION    0xF4 /* Get firmware revision */
  34 
  35 /* Command id associated with message IPCMSG_PCNTRL */
  36 #define IPC_CMD_PCNTRL_W      0 /* Register write */
  37 #define IPC_CMD_PCNTRL_R      1 /* Register read */
  38 #define IPC_CMD_PCNTRL_M      2 /* Register read-modify-write */
  39 
  40 /*
  41  * IPC register summary
  42  *
  43  * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
  44  * To read or write information to the SCU, driver writes to IPC-1 memory
  45  * mapped registers. The following is the IPC mechanism
  46  *
  47  * 1. IA core cDMI interface claims this transaction and converts it to a
  48  *    Transaction Layer Packet (TLP) message which is sent across the cDMI.
  49  *
  50  * 2. South Complex cDMI block receives this message and writes it to
  51  *    the IPC-1 register block, causing an interrupt to the SCU
  52  *
  53  * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
  54  *    message handler is called within firmware.
  55  */
  56 
  57 #define IPC_WWBUF_SIZE    20            /* IPC Write buffer Size */
  58 #define IPC_RWBUF_SIZE    20            /* IPC Read buffer Size */
  59 #define IPC_IOC           0x100         /* IPC command register IOC bit */
  60 
  61 #define PCI_DEVICE_ID_LINCROFT          0x082a
  62 #define PCI_DEVICE_ID_PENWELL           0x080e
  63 #define PCI_DEVICE_ID_CLOVERVIEW        0x08ea
  64 #define PCI_DEVICE_ID_TANGIER           0x11a0
  65 
  66 /* intel scu ipc driver data */
  67 struct intel_scu_ipc_pdata_t {
  68         u32 i2c_base;
  69         u32 i2c_len;
  70 };
  71 
  72 static const struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
  73         .i2c_base = 0xff12b000,
  74         .i2c_len = 0x10,
  75 };
  76 
  77 /* Penwell and Cloverview */
  78 static const struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
  79         .i2c_base = 0xff12b000,
  80         .i2c_len = 0x10,
  81 };
  82 
  83 static const struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
  84         .i2c_base  = 0xff00d000,
  85         .i2c_len = 0x10,
  86 };
  87 
  88 struct intel_scu_ipc_dev {
  89         struct device *dev;
  90         void __iomem *ipc_base;
  91         void __iomem *i2c_base;
  92         struct completion cmd_complete;
  93         u8 irq_mode;
  94 };
  95 
  96 static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */
  97 
  98 #define IPC_STATUS              0x04
  99 #define IPC_STATUS_IRQ          BIT(2)
 100 
 101 /*
 102  * IPC Read Buffer (Read Only):
 103  * 16 byte buffer for receiving data from SCU, if IPC command
 104  * processing results in response data
 105  */
 106 #define IPC_READ_BUFFER         0x90
 107 
 108 #define IPC_I2C_CNTRL_ADDR      0
 109 #define I2C_DATA_ADDR           0x04
 110 
 111 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
 112 
 113 /*
 114  * Send ipc command
 115  * Command Register (Write Only):
 116  * A write to this register results in an interrupt to the SCU core processor
 117  * Format:
 118  * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
 119  */
 120 static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
 121 {
 122         reinit_completion(&scu->cmd_complete);
 123         writel(cmd | IPC_IOC, scu->ipc_base);
 124 }
 125 
 126 /*
 127  * Write ipc data
 128  * IPC Write Buffer (Write Only):
 129  * 16-byte buffer for sending data associated with IPC command to
 130  * SCU. Size of the data is specified in the IPC_COMMAND_REG register
 131  */
 132 static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
 133 {
 134         writel(data, scu->ipc_base + 0x80 + offset);
 135 }
 136 
 137 /*
 138  * Status Register (Read Only):
 139  * Driver will read this register to get the ready/busy status of the IPC
 140  * block and error status of the IPC command that was just processed by SCU
 141  * Format:
 142  * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
 143  */
 144 static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
 145 {
 146         return __raw_readl(scu->ipc_base + 0x04);
 147 }
 148 
 149 /* Read ipc byte data */
 150 static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
 151 {
 152         return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
 153 }
 154 
 155 /* Read ipc u32 data */
 156 static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
 157 {
 158         return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
 159 }
 160 
 161 /* Wait till scu status is busy */
 162 static inline int busy_loop(struct intel_scu_ipc_dev *scu)
 163 {
 164         u32 status = ipc_read_status(scu);
 165         u32 loop_count = 100000;
 166 
 167         /* break if scu doesn't reset busy bit after huge retry */
 168         while ((status & BIT(0)) && --loop_count) {
 169                 udelay(1); /* scu processing time is in few u secods */
 170                 status = ipc_read_status(scu);
 171         }
 172 
 173         if (status & BIT(0)) {
 174                 dev_err(scu->dev, "IPC timed out");
 175                 return -ETIMEDOUT;
 176         }
 177 
 178         if (status & BIT(1))
 179                 return -EIO;
 180 
 181         return 0;
 182 }
 183 
 184 /* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
 185 static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
 186 {
 187         int status;
 188 
 189         if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
 190                 dev_err(scu->dev, "IPC timed out\n");
 191                 return -ETIMEDOUT;
 192         }
 193 
 194         status = ipc_read_status(scu);
 195         if (status & BIT(1))
 196                 return -EIO;
 197 
 198         return 0;
 199 }
 200 
 201 static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
 202 {
 203         return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
 204 }
 205 
 206 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
 207 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
 208 {
 209         struct intel_scu_ipc_dev *scu = &ipcdev;
 210         int nc;
 211         u32 offset = 0;
 212         int err;
 213         u8 cbuf[IPC_WWBUF_SIZE];
 214         u32 *wbuf = (u32 *)&cbuf;
 215 
 216         memset(cbuf, 0, sizeof(cbuf));
 217 
 218         mutex_lock(&ipclock);
 219 
 220         if (scu->dev == NULL) {
 221                 mutex_unlock(&ipclock);
 222                 return -ENODEV;
 223         }
 224 
 225         for (nc = 0; nc < count; nc++, offset += 2) {
 226                 cbuf[offset] = addr[nc];
 227                 cbuf[offset + 1] = addr[nc] >> 8;
 228         }
 229 
 230         if (id == IPC_CMD_PCNTRL_R) {
 231                 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
 232                         ipc_data_writel(scu, wbuf[nc], offset);
 233                 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
 234         } else if (id == IPC_CMD_PCNTRL_W) {
 235                 for (nc = 0; nc < count; nc++, offset += 1)
 236                         cbuf[offset] = data[nc];
 237                 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
 238                         ipc_data_writel(scu, wbuf[nc], offset);
 239                 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
 240         } else if (id == IPC_CMD_PCNTRL_M) {
 241                 cbuf[offset] = data[0];
 242                 cbuf[offset + 1] = data[1];
 243                 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
 244                 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
 245         }
 246 
 247         err = intel_scu_ipc_check_status(scu);
 248         if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
 249                 /* Workaround: values are read as 0 without memcpy_fromio */
 250                 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
 251                 for (nc = 0; nc < count; nc++)
 252                         data[nc] = ipc_data_readb(scu, nc);
 253         }
 254         mutex_unlock(&ipclock);
 255         return err;
 256 }
 257 
 258 /**
 259  *      intel_scu_ipc_ioread8           -       read a word via the SCU
 260  *      @addr: register on SCU
 261  *      @data: return pointer for read byte
 262  *
 263  *      Read a single register. Returns 0 on success or an error code. All
 264  *      locking between SCU accesses is handled for the caller.
 265  *
 266  *      This function may sleep.
 267  */
 268 int intel_scu_ipc_ioread8(u16 addr, u8 *data)
 269 {
 270         return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
 271 }
 272 EXPORT_SYMBOL(intel_scu_ipc_ioread8);
 273 
 274 /**
 275  *      intel_scu_ipc_ioread16          -       read a word via the SCU
 276  *      @addr: register on SCU
 277  *      @data: return pointer for read word
 278  *
 279  *      Read a register pair. Returns 0 on success or an error code. All
 280  *      locking between SCU accesses is handled for the caller.
 281  *
 282  *      This function may sleep.
 283  */
 284 int intel_scu_ipc_ioread16(u16 addr, u16 *data)
 285 {
 286         u16 x[2] = {addr, addr + 1};
 287         return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
 288 }
 289 EXPORT_SYMBOL(intel_scu_ipc_ioread16);
 290 
 291 /**
 292  *      intel_scu_ipc_ioread32          -       read a dword via the SCU
 293  *      @addr: register on SCU
 294  *      @data: return pointer for read dword
 295  *
 296  *      Read four registers. Returns 0 on success or an error code. All
 297  *      locking between SCU accesses is handled for the caller.
 298  *
 299  *      This function may sleep.
 300  */
 301 int intel_scu_ipc_ioread32(u16 addr, u32 *data)
 302 {
 303         u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
 304         return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
 305 }
 306 EXPORT_SYMBOL(intel_scu_ipc_ioread32);
 307 
 308 /**
 309  *      intel_scu_ipc_iowrite8          -       write a byte via the SCU
 310  *      @addr: register on SCU
 311  *      @data: byte to write
 312  *
 313  *      Write a single register. Returns 0 on success or an error code. All
 314  *      locking between SCU accesses is handled for the caller.
 315  *
 316  *      This function may sleep.
 317  */
 318 int intel_scu_ipc_iowrite8(u16 addr, u8 data)
 319 {
 320         return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
 321 }
 322 EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
 323 
 324 /**
 325  *      intel_scu_ipc_iowrite16         -       write a word via the SCU
 326  *      @addr: register on SCU
 327  *      @data: word to write
 328  *
 329  *      Write two registers. Returns 0 on success or an error code. All
 330  *      locking between SCU accesses is handled for the caller.
 331  *
 332  *      This function may sleep.
 333  */
 334 int intel_scu_ipc_iowrite16(u16 addr, u16 data)
 335 {
 336         u16 x[2] = {addr, addr + 1};
 337         return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
 338 }
 339 EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
 340 
 341 /**
 342  *      intel_scu_ipc_iowrite32         -       write a dword via the SCU
 343  *      @addr: register on SCU
 344  *      @data: dword to write
 345  *
 346  *      Write four registers. Returns 0 on success or an error code. All
 347  *      locking between SCU accesses is handled for the caller.
 348  *
 349  *      This function may sleep.
 350  */
 351 int intel_scu_ipc_iowrite32(u16 addr, u32 data)
 352 {
 353         u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
 354         return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
 355 }
 356 EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
 357 
 358 /**
 359  *      intel_scu_ipc_readvv            -       read a set of registers
 360  *      @addr: register list
 361  *      @data: bytes to return
 362  *      @len: length of array
 363  *
 364  *      Read registers. Returns 0 on success or an error code. All
 365  *      locking between SCU accesses is handled for the caller.
 366  *
 367  *      The largest array length permitted by the hardware is 5 items.
 368  *
 369  *      This function may sleep.
 370  */
 371 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
 372 {
 373         return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
 374 }
 375 EXPORT_SYMBOL(intel_scu_ipc_readv);
 376 
 377 /**
 378  *      intel_scu_ipc_writev            -       write a set of registers
 379  *      @addr: register list
 380  *      @data: bytes to write
 381  *      @len: length of array
 382  *
 383  *      Write registers. Returns 0 on success or an error code. All
 384  *      locking between SCU accesses is handled for the caller.
 385  *
 386  *      The largest array length permitted by the hardware is 5 items.
 387  *
 388  *      This function may sleep.
 389  *
 390  */
 391 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
 392 {
 393         return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
 394 }
 395 EXPORT_SYMBOL(intel_scu_ipc_writev);
 396 
 397 /**
 398  *      intel_scu_ipc_update_register   -       r/m/w a register
 399  *      @addr: register address
 400  *      @bits: bits to update
 401  *      @mask: mask of bits to update
 402  *
 403  *      Read-modify-write power control unit register. The first data argument
 404  *      must be register value and second is mask value
 405  *      mask is a bitmap that indicates which bits to update.
 406  *      0 = masked. Don't modify this bit, 1 = modify this bit.
 407  *      returns 0 on success or an error code.
 408  *
 409  *      This function may sleep. Locking between SCU accesses is handled
 410  *      for the caller.
 411  */
 412 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
 413 {
 414         u8 data[2] = { bits, mask };
 415         return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
 416 }
 417 EXPORT_SYMBOL(intel_scu_ipc_update_register);
 418 
 419 /**
 420  *      intel_scu_ipc_simple_command    -       send a simple command
 421  *      @cmd: command
 422  *      @sub: sub type
 423  *
 424  *      Issue a simple command to the SCU. Do not use this interface if
 425  *      you must then access data as any data values may be overwritten
 426  *      by another SCU access by the time this function returns.
 427  *
 428  *      This function may sleep. Locking for SCU accesses is handled for
 429  *      the caller.
 430  */
 431 int intel_scu_ipc_simple_command(int cmd, int sub)
 432 {
 433         struct intel_scu_ipc_dev *scu = &ipcdev;
 434         int err;
 435 
 436         mutex_lock(&ipclock);
 437         if (scu->dev == NULL) {
 438                 mutex_unlock(&ipclock);
 439                 return -ENODEV;
 440         }
 441         ipc_command(scu, sub << 12 | cmd);
 442         err = intel_scu_ipc_check_status(scu);
 443         mutex_unlock(&ipclock);
 444         return err;
 445 }
 446 EXPORT_SYMBOL(intel_scu_ipc_simple_command);
 447 
 448 /**
 449  *      intel_scu_ipc_command   -       command with data
 450  *      @cmd: command
 451  *      @sub: sub type
 452  *      @in: input data
 453  *      @inlen: input length in dwords
 454  *      @out: output data
 455  *      @outlein: output length in dwords
 456  *
 457  *      Issue a command to the SCU which involves data transfers. Do the
 458  *      data copies under the lock but leave it for the caller to interpret
 459  */
 460 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
 461                           u32 *out, int outlen)
 462 {
 463         struct intel_scu_ipc_dev *scu = &ipcdev;
 464         int i, err;
 465 
 466         mutex_lock(&ipclock);
 467         if (scu->dev == NULL) {
 468                 mutex_unlock(&ipclock);
 469                 return -ENODEV;
 470         }
 471 
 472         for (i = 0; i < inlen; i++)
 473                 ipc_data_writel(scu, *in++, 4 * i);
 474 
 475         ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
 476         err = intel_scu_ipc_check_status(scu);
 477 
 478         if (!err) {
 479                 for (i = 0; i < outlen; i++)
 480                         *out++ = ipc_data_readl(scu, 4 * i);
 481         }
 482 
 483         mutex_unlock(&ipclock);
 484         return err;
 485 }
 486 EXPORT_SYMBOL(intel_scu_ipc_command);
 487 
 488 #define IPC_SPTR                0x08
 489 #define IPC_DPTR                0x0C
 490 
 491 /**
 492  * intel_scu_ipc_raw_command() - IPC command with data and pointers
 493  * @cmd:        IPC command code.
 494  * @sub:        IPC command sub type.
 495  * @in:         input data of this IPC command.
 496  * @inlen:      input data length in dwords.
 497  * @out:        output data of this IPC command.
 498  * @outlen:     output data length in dwords.
 499  * @sptr:       data writing to SPTR register.
 500  * @dptr:       data writing to DPTR register.
 501  *
 502  * Send an IPC command to SCU with input/output data and source/dest pointers.
 503  *
 504  * Return:      an IPC error code or 0 on success.
 505  */
 506 int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,
 507                               u32 *out, int outlen, u32 dptr, u32 sptr)
 508 {
 509         struct intel_scu_ipc_dev *scu = &ipcdev;
 510         int inbuflen = DIV_ROUND_UP(inlen, 4);
 511         u32 inbuf[4];
 512         int i, err;
 513 
 514         /* Up to 16 bytes */
 515         if (inbuflen > 4)
 516                 return -EINVAL;
 517 
 518         mutex_lock(&ipclock);
 519         if (scu->dev == NULL) {
 520                 mutex_unlock(&ipclock);
 521                 return -ENODEV;
 522         }
 523 
 524         writel(dptr, scu->ipc_base + IPC_DPTR);
 525         writel(sptr, scu->ipc_base + IPC_SPTR);
 526 
 527         /*
 528          * SRAM controller doesn't support 8-bit writes, it only
 529          * supports 32-bit writes, so we have to copy input data into
 530          * the temporary buffer, and SCU FW will use the inlen to
 531          * determine the actual input data length in the temporary
 532          * buffer.
 533          */
 534         memcpy(inbuf, in, inlen);
 535 
 536         for (i = 0; i < inbuflen; i++)
 537                 ipc_data_writel(scu, inbuf[i], 4 * i);
 538 
 539         ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
 540         err = intel_scu_ipc_check_status(scu);
 541         if (!err) {
 542                 for (i = 0; i < outlen; i++)
 543                         *out++ = ipc_data_readl(scu, 4 * i);
 544         }
 545 
 546         mutex_unlock(&ipclock);
 547         return err;
 548 }
 549 EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);
 550 
 551 /* I2C commands */
 552 #define IPC_I2C_WRITE 1 /* I2C Write command */
 553 #define IPC_I2C_READ  2 /* I2C Read command */
 554 
 555 /**
 556  *      intel_scu_ipc_i2c_cntrl         -       I2C read/write operations
 557  *      @addr: I2C address + command bits
 558  *      @data: data to read/write
 559  *
 560  *      Perform an an I2C read/write operation via the SCU. All locking is
 561  *      handled for the caller. This function may sleep.
 562  *
 563  *      Returns an error code or 0 on success.
 564  *
 565  *      This has to be in the IPC driver for the locking.
 566  */
 567 int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
 568 {
 569         struct intel_scu_ipc_dev *scu = &ipcdev;
 570         u32 cmd = 0;
 571 
 572         mutex_lock(&ipclock);
 573         if (scu->dev == NULL) {
 574                 mutex_unlock(&ipclock);
 575                 return -ENODEV;
 576         }
 577         cmd = (addr >> 24) & 0xFF;
 578         if (cmd == IPC_I2C_READ) {
 579                 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
 580                 /* Write not getting updated without delay */
 581                 usleep_range(1000, 2000);
 582                 *data = readl(scu->i2c_base + I2C_DATA_ADDR);
 583         } else if (cmd == IPC_I2C_WRITE) {
 584                 writel(*data, scu->i2c_base + I2C_DATA_ADDR);
 585                 usleep_range(1000, 2000);
 586                 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
 587         } else {
 588                 dev_err(scu->dev,
 589                         "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
 590 
 591                 mutex_unlock(&ipclock);
 592                 return -EIO;
 593         }
 594         mutex_unlock(&ipclock);
 595         return 0;
 596 }
 597 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
 598 
 599 /*
 600  * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
 601  * When ioc bit is set to 1, caller api must wait for interrupt handler called
 602  * which in turn unlocks the caller api. Currently this is not used
 603  *
 604  * This is edge triggered so we need take no action to clear anything
 605  */
 606 static irqreturn_t ioc(int irq, void *dev_id)
 607 {
 608         struct intel_scu_ipc_dev *scu = dev_id;
 609         int status = ipc_read_status(scu);
 610 
 611         writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
 612         complete(&scu->cmd_complete);
 613 
 614         return IRQ_HANDLED;
 615 }
 616 
 617 /**
 618  *      ipc_probe       -       probe an Intel SCU IPC
 619  *      @pdev: the PCI device matching
 620  *      @id: entry in the match table
 621  *
 622  *      Enable and install an intel SCU IPC. This appears in the PCI space
 623  *      but uses some hard coded addresses as well.
 624  */
 625 static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 626 {
 627         int err;
 628         struct intel_scu_ipc_dev *scu = &ipcdev;
 629         struct intel_scu_ipc_pdata_t *pdata;
 630 
 631         if (scu->dev)           /* We support only one SCU */
 632                 return -EBUSY;
 633 
 634         pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
 635         if (!pdata)
 636                 return -ENODEV;
 637 
 638         err = pcim_enable_device(pdev);
 639         if (err)
 640                 return err;
 641 
 642         err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
 643         if (err)
 644                 return err;
 645 
 646         init_completion(&scu->cmd_complete);
 647 
 648         scu->ipc_base = pcim_iomap_table(pdev)[0];
 649 
 650         scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
 651         if (!scu->i2c_base)
 652                 return -ENOMEM;
 653 
 654         err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
 655                                scu);
 656         if (err)
 657                 return err;
 658 
 659         /* Assign device at last */
 660         scu->dev = &pdev->dev;
 661 
 662         intel_scu_devices_create();
 663 
 664         pci_set_drvdata(pdev, scu);
 665         return 0;
 666 }
 667 
 668 #define SCU_DEVICE(id, pdata)   {PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&pdata}
 669 
 670 static const struct pci_device_id pci_ids[] = {
 671         SCU_DEVICE(PCI_DEVICE_ID_LINCROFT,      intel_scu_ipc_lincroft_pdata),
 672         SCU_DEVICE(PCI_DEVICE_ID_PENWELL,       intel_scu_ipc_penwell_pdata),
 673         SCU_DEVICE(PCI_DEVICE_ID_CLOVERVIEW,    intel_scu_ipc_penwell_pdata),
 674         SCU_DEVICE(PCI_DEVICE_ID_TANGIER,       intel_scu_ipc_tangier_pdata),
 675         {}
 676 };
 677 
 678 static struct pci_driver ipc_driver = {
 679         .driver = {
 680                 .suppress_bind_attrs = true,
 681         },
 682         .name = "intel_scu_ipc",
 683         .id_table = pci_ids,
 684         .probe = ipc_probe,
 685 };
 686 builtin_pci_driver(ipc_driver);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/platform/x86/intel_scu_ipc.c

DEFINITIONS
