root/drivers/platform/mellanox/mlxbf-tmfifo-regs.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2019, Mellanox Technologies. All rights reserved.
   4  */
   5 
   6 #ifndef __MLXBF_TMFIFO_REGS_H__
   7 #define __MLXBF_TMFIFO_REGS_H__
   8 
   9 #include <linux/types.h>
  10 #include <linux/bits.h>
  11 
  12 #define MLXBF_TMFIFO_TX_DATA                            0x00
  13 #define MLXBF_TMFIFO_TX_STS                             0x08
  14 #define MLXBF_TMFIFO_TX_STS__LENGTH                     0x0001
  15 #define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT                0
  16 #define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH                9
  17 #define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL            0
  18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK                GENMASK_ULL(8, 0)
  19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK                 GENMASK_ULL(8, 0)
  20 #define MLXBF_TMFIFO_TX_CTL                             0x10
  21 #define MLXBF_TMFIFO_TX_CTL__LENGTH                     0x0001
  22 #define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT                  0
  23 #define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH                  8
  24 #define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL              128
  25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK                  GENMASK_ULL(7, 0)
  26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK                   GENMASK_ULL(7, 0)
  27 #define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT                  8
  28 #define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH                  8
  29 #define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL              128
  30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK                  GENMASK_ULL(7, 0)
  31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK                   GENMASK_ULL(15, 8)
  32 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT          32
  33 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH          9
  34 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL      256
  35 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK          GENMASK_ULL(8, 0)
  36 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK           GENMASK_ULL(40, 32)
  37 #define MLXBF_TMFIFO_RX_DATA                            0x00
  38 #define MLXBF_TMFIFO_RX_STS                             0x08
  39 #define MLXBF_TMFIFO_RX_STS__LENGTH                     0x0001
  40 #define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT                0
  41 #define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH                9
  42 #define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL            0
  43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK                GENMASK_ULL(8, 0)
  44 #define MLXBF_TMFIFO_RX_STS__COUNT_MASK                 GENMASK_ULL(8, 0)
  45 #define MLXBF_TMFIFO_RX_CTL                             0x10
  46 #define MLXBF_TMFIFO_RX_CTL__LENGTH                     0x0001
  47 #define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT                  0
  48 #define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH                  8
  49 #define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL              128
  50 #define MLXBF_TMFIFO_RX_CTL__LWM_RMASK                  GENMASK_ULL(7, 0)
  51 #define MLXBF_TMFIFO_RX_CTL__LWM_MASK                   GENMASK_ULL(7, 0)
  52 #define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT                  8
  53 #define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH                  8
  54 #define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL              128
  55 #define MLXBF_TMFIFO_RX_CTL__HWM_RMASK                  GENMASK_ULL(7, 0)
  56 #define MLXBF_TMFIFO_RX_CTL__HWM_MASK                   GENMASK_ULL(15, 8)
  57 #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT          32
  58 #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH          9
  59 #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL      256
  60 #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK          GENMASK_ULL(8, 0)
  61 #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK           GENMASK_ULL(40, 32)
  62 
  63 #endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */