1 /*
2 * This file is provided under a GPLv2 license. When using or
3 * redistributing this file, you may do so under that license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
16 * Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, one can be found http://www.gnu.org/licenses/.
20 *
21 * The full GNU General Public License is included in this distribution in
22 * the file called "COPYING".
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * IDT PCIe-switch NTB Linux driver
37 *
38 * Contact Information:
39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
40 */
41
42 #ifndef NTB_HW_IDT_H
43 #define NTB_HW_IDT_H
44
45 #include <linux/types.h>
46 #include <linux/pci.h>
47 #include <linux/pci_ids.h>
48 #include <linux/interrupt.h>
49 #include <linux/spinlock.h>
50 #include <linux/mutex.h>
51 #include <linux/ntb.h>
52
53 /*
54 * Macro is used to create the struct pci_device_id that matches
55 * the supported IDT PCIe-switches
56 * @devname: Capitalized name of the particular device
57 * @data: Variable passed to the driver of the particular device
58 */
59 #define IDT_PCI_DEVICE_IDS(devname, data) \
60 .vendor = PCI_VENDOR_ID_IDT, .device = PCI_DEVICE_ID_IDT_##devname, \
61 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
62 .class = (PCI_CLASS_BRIDGE_OTHER << 8), .class_mask = (0xFFFF00), \
63 .driver_data = (kernel_ulong_t)&data
64
65 /*
66 * IDT PCIe-switches device IDs
67 */
68 #define PCI_DEVICE_ID_IDT_89HPES24NT6AG2 0x8091
69 #define PCI_DEVICE_ID_IDT_89HPES32NT8AG2 0x808F
70 #define PCI_DEVICE_ID_IDT_89HPES32NT8BG2 0x8088
71 #define PCI_DEVICE_ID_IDT_89HPES12NT12G2 0x8092
72 #define PCI_DEVICE_ID_IDT_89HPES16NT16G2 0x8090
73 #define PCI_DEVICE_ID_IDT_89HPES24NT24G2 0x808E
74 #define PCI_DEVICE_ID_IDT_89HPES32NT24AG2 0x808C
75 #define PCI_DEVICE_ID_IDT_89HPES32NT24BG2 0x808A
76
77 /*
78 * NT-function Configuration Space registers
79 * NOTE 1) The IDT PCIe-switch internal data is little-endian
80 * so it must be taken into account in the driver
81 * internals.
82 * 2) Additionally the registers should be accessed either
83 * with byte-enables corresponding to their native size or
84 * the size of one DWORD
85 *
86 * So to simplify the driver code, there is only DWORD-sized read/write
87 * operations utilized.
88 */
89 /* PCI Express Configuration Space */
90 /* PCI Express command/status register (DWORD) */
91 #define IDT_NT_PCICMDSTS 0x00004U
92 /* PCI Express Device Capabilities (DWORD) */
93 #define IDT_NT_PCIEDCAP 0x00044U
94 /* PCI Express Device Control/Status (WORD+WORD) */
95 #define IDT_NT_PCIEDCTLSTS 0x00048U
96 /* PCI Express Link Capabilities (DWORD) */
97 #define IDT_NT_PCIELCAP 0x0004CU
98 /* PCI Express Link Control/Status (WORD+WORD) */
99 #define IDT_NT_PCIELCTLSTS 0x00050U
100 /* PCI Express Device Capabilities 2 (DWORD) */
101 #define IDT_NT_PCIEDCAP2 0x00064U
102 /* PCI Express Device Control 2 (WORD+WORD) */
103 #define IDT_NT_PCIEDCTL2 0x00068U
104 /* PCI Power Management Control and Status (DWORD) */
105 #define IDT_NT_PMCSR 0x000C4U
106 /*==========================================*/
107 /* IDT Proprietary NT-port-specific registers */
108 /* NT-function main control registers */
109 /* NT Endpoint Control (DWORD) */
110 #define IDT_NT_NTCTL 0x00400U
111 /* NT Endpoint Interrupt Status/Mask (DWORD) */
112 #define IDT_NT_NTINTSTS 0x00404U
113 #define IDT_NT_NTINTMSK 0x00408U
114 /* NT Endpoint Signal Data (DWORD) */
115 #define IDT_NT_NTSDATA 0x0040CU
116 /* NT Endpoint Global Signal (DWORD) */
117 #define IDT_NT_NTGSIGNAL 0x00410U
118 /* Internal Error Reporting Mask 0/1 (DWORD) */
119 #define IDT_NT_NTIERRORMSK0 0x00414U
120 #define IDT_NT_NTIERRORMSK1 0x00418U
121 /* Doorbel registers */
122 /* NT Outbound Doorbell Set (DWORD) */
123 #define IDT_NT_OUTDBELLSET 0x00420U
124 /* NT Inbound Doorbell Status/Mask (DWORD) */
125 #define IDT_NT_INDBELLSTS 0x00428U
126 #define IDT_NT_INDBELLMSK 0x0042CU
127 /* Message registers */
128 /* Outbound Message N (DWORD) */
129 #define IDT_NT_OUTMSG0 0x00430U
130 #define IDT_NT_OUTMSG1 0x00434U
131 #define IDT_NT_OUTMSG2 0x00438U
132 #define IDT_NT_OUTMSG3 0x0043CU
133 /* Inbound Message N (DWORD) */
134 #define IDT_NT_INMSG0 0x00440U
135 #define IDT_NT_INMSG1 0x00444U
136 #define IDT_NT_INMSG2 0x00448U
137 #define IDT_NT_INMSG3 0x0044CU
138 /* Inbound Message Source N (DWORD) */
139 #define IDT_NT_INMSGSRC0 0x00450U
140 #define IDT_NT_INMSGSRC1 0x00454U
141 #define IDT_NT_INMSGSRC2 0x00458U
142 #define IDT_NT_INMSGSRC3 0x0045CU
143 /* Message Status (DWORD) */
144 #define IDT_NT_MSGSTS 0x00460U
145 /* Message Status Mask (DWORD) */
146 #define IDT_NT_MSGSTSMSK 0x00464U
147 /* BAR-setup registers */
148 /* BAR N Setup/Limit Address/Lower and Upper Translated Base Address (DWORD) */
149 #define IDT_NT_BARSETUP0 0x00470U
150 #define IDT_NT_BARLIMIT0 0x00474U
151 #define IDT_NT_BARLTBASE0 0x00478U
152 #define IDT_NT_BARUTBASE0 0x0047CU
153 #define IDT_NT_BARSETUP1 0x00480U
154 #define IDT_NT_BARLIMIT1 0x00484U
155 #define IDT_NT_BARLTBASE1 0x00488U
156 #define IDT_NT_BARUTBASE1 0x0048CU
157 #define IDT_NT_BARSETUP2 0x00490U
158 #define IDT_NT_BARLIMIT2 0x00494U
159 #define IDT_NT_BARLTBASE2 0x00498U
160 #define IDT_NT_BARUTBASE2 0x0049CU
161 #define IDT_NT_BARSETUP3 0x004A0U
162 #define IDT_NT_BARLIMIT3 0x004A4U
163 #define IDT_NT_BARLTBASE3 0x004A8U
164 #define IDT_NT_BARUTBASE3 0x004ACU
165 #define IDT_NT_BARSETUP4 0x004B0U
166 #define IDT_NT_BARLIMIT4 0x004B4U
167 #define IDT_NT_BARLTBASE4 0x004B8U
168 #define IDT_NT_BARUTBASE4 0x004BCU
169 #define IDT_NT_BARSETUP5 0x004C0U
170 #define IDT_NT_BARLIMIT5 0x004C4U
171 #define IDT_NT_BARLTBASE5 0x004C8U
172 #define IDT_NT_BARUTBASE5 0x004CCU
173 /* NT mapping table registers */
174 /* NT Mapping Table Address/Status/Data (DWORD) */
175 #define IDT_NT_NTMTBLADDR 0x004D0U
176 #define IDT_NT_NTMTBLSTS 0x004D4U
177 #define IDT_NT_NTMTBLDATA 0x004D8U
178 /* Requester ID (Bus:Device:Function) Capture (DWORD) */
179 #define IDT_NT_REQIDCAP 0x004DCU
180 /* Memory Windows Lookup table registers */
181 /* Lookup Table Offset/Lower, Middle and Upper data (DWORD) */
182 #define IDT_NT_LUTOFFSET 0x004E0U
183 #define IDT_NT_LUTLDATA 0x004E4U
184 #define IDT_NT_LUTMDATA 0x004E8U
185 #define IDT_NT_LUTUDATA 0x004ECU
186 /* NT Endpoint Uncorrectable/Correctable Errors Emulation registers (DWORD) */
187 #define IDT_NT_NTUEEM 0x004F0U
188 #define IDT_NT_NTCEEM 0x004F4U
189 /* Global Address Space Access/Data registers (DWARD) */
190 #define IDT_NT_GASAADDR 0x00FF8U
191 #define IDT_NT_GASADATA 0x00FFCU
192
193 /*
194 * IDT PCIe-switch Global Configuration and Status registers
195 */
196 /* Port N Configuration register in global space */
197 /* PCI Express command/status and link control/status registers (WORD+WORD) */
198 #define IDT_SW_NTP0_PCIECMDSTS 0x01004U
199 #define IDT_SW_NTP0_PCIELCTLSTS 0x01050U
200 /* NT-function control register (DWORD) */
201 #define IDT_SW_NTP0_NTCTL 0x01400U
202 /* BAR setup/limit/base address registers (DWORD) */
203 #define IDT_SW_NTP0_BARSETUP0 0x01470U
204 #define IDT_SW_NTP0_BARLIMIT0 0x01474U
205 #define IDT_SW_NTP0_BARLTBASE0 0x01478U
206 #define IDT_SW_NTP0_BARUTBASE0 0x0147CU
207 #define IDT_SW_NTP0_BARSETUP1 0x01480U
208 #define IDT_SW_NTP0_BARLIMIT1 0x01484U
209 #define IDT_SW_NTP0_BARLTBASE1 0x01488U
210 #define IDT_SW_NTP0_BARUTBASE1 0x0148CU
211 #define IDT_SW_NTP0_BARSETUP2 0x01490U
212 #define IDT_SW_NTP0_BARLIMIT2 0x01494U
213 #define IDT_SW_NTP0_BARLTBASE2 0x01498U
214 #define IDT_SW_NTP0_BARUTBASE2 0x0149CU
215 #define IDT_SW_NTP0_BARSETUP3 0x014A0U
216 #define IDT_SW_NTP0_BARLIMIT3 0x014A4U
217 #define IDT_SW_NTP0_BARLTBASE3 0x014A8U
218 #define IDT_SW_NTP0_BARUTBASE3 0x014ACU
219 #define IDT_SW_NTP0_BARSETUP4 0x014B0U
220 #define IDT_SW_NTP0_BARLIMIT4 0x014B4U
221 #define IDT_SW_NTP0_BARLTBASE4 0x014B8U
222 #define IDT_SW_NTP0_BARUTBASE4 0x014BCU
223 #define IDT_SW_NTP0_BARSETUP5 0x014C0U
224 #define IDT_SW_NTP0_BARLIMIT5 0x014C4U
225 #define IDT_SW_NTP0_BARLTBASE5 0x014C8U
226 #define IDT_SW_NTP0_BARUTBASE5 0x014CCU
227 /* PCI Express command/status and link control/status registers (WORD+WORD) */
228 #define IDT_SW_NTP2_PCIECMDSTS 0x05004U
229 #define IDT_SW_NTP2_PCIELCTLSTS 0x05050U
230 /* NT-function control register (DWORD) */
231 #define IDT_SW_NTP2_NTCTL 0x05400U
232 /* BAR setup/limit/base address registers (DWORD) */
233 #define IDT_SW_NTP2_BARSETUP0 0x05470U
234 #define IDT_SW_NTP2_BARLIMIT0 0x05474U
235 #define IDT_SW_NTP2_BARLTBASE0 0x05478U
236 #define IDT_SW_NTP2_BARUTBASE0 0x0547CU
237 #define IDT_SW_NTP2_BARSETUP1 0x05480U
238 #define IDT_SW_NTP2_BARLIMIT1 0x05484U
239 #define IDT_SW_NTP2_BARLTBASE1 0x05488U
240 #define IDT_SW_NTP2_BARUTBASE1 0x0548CU
241 #define IDT_SW_NTP2_BARSETUP2 0x05490U
242 #define IDT_SW_NTP2_BARLIMIT2 0x05494U
243 #define IDT_SW_NTP2_BARLTBASE2 0x05498U
244 #define IDT_SW_NTP2_BARUTBASE2 0x0549CU
245 #define IDT_SW_NTP2_BARSETUP3 0x054A0U
246 #define IDT_SW_NTP2_BARLIMIT3 0x054A4U
247 #define IDT_SW_NTP2_BARLTBASE3 0x054A8U
248 #define IDT_SW_NTP2_BARUTBASE3 0x054ACU
249 #define IDT_SW_NTP2_BARSETUP4 0x054B0U
250 #define IDT_SW_NTP2_BARLIMIT4 0x054B4U
251 #define IDT_SW_NTP2_BARLTBASE4 0x054B8U
252 #define IDT_SW_NTP2_BARUTBASE4 0x054BCU
253 #define IDT_SW_NTP2_BARSETUP5 0x054C0U
254 #define IDT_SW_NTP2_BARLIMIT5 0x054C4U
255 #define IDT_SW_NTP2_BARLTBASE5 0x054C8U
256 #define IDT_SW_NTP2_BARUTBASE5 0x054CCU
257 /* PCI Express command/status and link control/status registers (WORD+WORD) */
258 #define IDT_SW_NTP4_PCIECMDSTS 0x09004U
259 #define IDT_SW_NTP4_PCIELCTLSTS 0x09050U
260 /* NT-function control register (DWORD) */
261 #define IDT_SW_NTP4_NTCTL 0x09400U
262 /* BAR setup/limit/base address registers (DWORD) */
263 #define IDT_SW_NTP4_BARSETUP0 0x09470U
264 #define IDT_SW_NTP4_BARLIMIT0 0x09474U
265 #define IDT_SW_NTP4_BARLTBASE0 0x09478U
266 #define IDT_SW_NTP4_BARUTBASE0 0x0947CU
267 #define IDT_SW_NTP4_BARSETUP1 0x09480U
268 #define IDT_SW_NTP4_BARLIMIT1 0x09484U
269 #define IDT_SW_NTP4_BARLTBASE1 0x09488U
270 #define IDT_SW_NTP4_BARUTBASE1 0x0948CU
271 #define IDT_SW_NTP4_BARSETUP2 0x09490U
272 #define IDT_SW_NTP4_BARLIMIT2 0x09494U
273 #define IDT_SW_NTP4_BARLTBASE2 0x09498U
274 #define IDT_SW_NTP4_BARUTBASE2 0x0949CU
275 #define IDT_SW_NTP4_BARSETUP3 0x094A0U
276 #define IDT_SW_NTP4_BARLIMIT3 0x094A4U
277 #define IDT_SW_NTP4_BARLTBASE3 0x094A8U
278 #define IDT_SW_NTP4_BARUTBASE3 0x094ACU
279 #define IDT_SW_NTP4_BARSETUP4 0x094B0U
280 #define IDT_SW_NTP4_BARLIMIT4 0x094B4U
281 #define IDT_SW_NTP4_BARLTBASE4 0x094B8U
282 #define IDT_SW_NTP4_BARUTBASE4 0x094BCU
283 #define IDT_SW_NTP4_BARSETUP5 0x094C0U
284 #define IDT_SW_NTP4_BARLIMIT5 0x094C4U
285 #define IDT_SW_NTP4_BARLTBASE5 0x094C8U
286 #define IDT_SW_NTP4_BARUTBASE5 0x094CCU
287 /* PCI Express command/status and link control/status registers (WORD+WORD) */
288 #define IDT_SW_NTP6_PCIECMDSTS 0x0D004U
289 #define IDT_SW_NTP6_PCIELCTLSTS 0x0D050U
290 /* NT-function control register (DWORD) */
291 #define IDT_SW_NTP6_NTCTL 0x0D400U
292 /* BAR setup/limit/base address registers (DWORD) */
293 #define IDT_SW_NTP6_BARSETUP0 0x0D470U
294 #define IDT_SW_NTP6_BARLIMIT0 0x0D474U
295 #define IDT_SW_NTP6_BARLTBASE0 0x0D478U
296 #define IDT_SW_NTP6_BARUTBASE0 0x0D47CU
297 #define IDT_SW_NTP6_BARSETUP1 0x0D480U
298 #define IDT_SW_NTP6_BARLIMIT1 0x0D484U
299 #define IDT_SW_NTP6_BARLTBASE1 0x0D488U
300 #define IDT_SW_NTP6_BARUTBASE1 0x0D48CU
301 #define IDT_SW_NTP6_BARSETUP2 0x0D490U
302 #define IDT_SW_NTP6_BARLIMIT2 0x0D494U
303 #define IDT_SW_NTP6_BARLTBASE2 0x0D498U
304 #define IDT_SW_NTP6_BARUTBASE2 0x0D49CU
305 #define IDT_SW_NTP6_BARSETUP3 0x0D4A0U
306 #define IDT_SW_NTP6_BARLIMIT3 0x0D4A4U
307 #define IDT_SW_NTP6_BARLTBASE3 0x0D4A8U
308 #define IDT_SW_NTP6_BARUTBASE3 0x0D4ACU
309 #define IDT_SW_NTP6_BARSETUP4 0x0D4B0U
310 #define IDT_SW_NTP6_BARLIMIT4 0x0D4B4U
311 #define IDT_SW_NTP6_BARLTBASE4 0x0D4B8U
312 #define IDT_SW_NTP6_BARUTBASE4 0x0D4BCU
313 #define IDT_SW_NTP6_BARSETUP5 0x0D4C0U
314 #define IDT_SW_NTP6_BARLIMIT5 0x0D4C4U
315 #define IDT_SW_NTP6_BARLTBASE5 0x0D4C8U
316 #define IDT_SW_NTP6_BARUTBASE5 0x0D4CCU
317 /* PCI Express command/status and link control/status registers (WORD+WORD) */
318 #define IDT_SW_NTP8_PCIECMDSTS 0x11004U
319 #define IDT_SW_NTP8_PCIELCTLSTS 0x11050U
320 /* NT-function control register (DWORD) */
321 #define IDT_SW_NTP8_NTCTL 0x11400U
322 /* BAR setup/limit/base address registers (DWORD) */
323 #define IDT_SW_NTP8_BARSETUP0 0x11470U
324 #define IDT_SW_NTP8_BARLIMIT0 0x11474U
325 #define IDT_SW_NTP8_BARLTBASE0 0x11478U
326 #define IDT_SW_NTP8_BARUTBASE0 0x1147CU
327 #define IDT_SW_NTP8_BARSETUP1 0x11480U
328 #define IDT_SW_NTP8_BARLIMIT1 0x11484U
329 #define IDT_SW_NTP8_BARLTBASE1 0x11488U
330 #define IDT_SW_NTP8_BARUTBASE1 0x1148CU
331 #define IDT_SW_NTP8_BARSETUP2 0x11490U
332 #define IDT_SW_NTP8_BARLIMIT2 0x11494U
333 #define IDT_SW_NTP8_BARLTBASE2 0x11498U
334 #define IDT_SW_NTP8_BARUTBASE2 0x1149CU
335 #define IDT_SW_NTP8_BARSETUP3 0x114A0U
336 #define IDT_SW_NTP8_BARLIMIT3 0x114A4U
337 #define IDT_SW_NTP8_BARLTBASE3 0x114A8U
338 #define IDT_SW_NTP8_BARUTBASE3 0x114ACU
339 #define IDT_SW_NTP8_BARSETUP4 0x114B0U
340 #define IDT_SW_NTP8_BARLIMIT4 0x114B4U
341 #define IDT_SW_NTP8_BARLTBASE4 0x114B8U
342 #define IDT_SW_NTP8_BARUTBASE4 0x114BCU
343 #define IDT_SW_NTP8_BARSETUP5 0x114C0U
344 #define IDT_SW_NTP8_BARLIMIT5 0x114C4U
345 #define IDT_SW_NTP8_BARLTBASE5 0x114C8U
346 #define IDT_SW_NTP8_BARUTBASE5 0x114CCU
347 /* PCI Express command/status and link control/status registers (WORD+WORD) */
348 #define IDT_SW_NTP12_PCIECMDSTS 0x19004U
349 #define IDT_SW_NTP12_PCIELCTLSTS 0x19050U
350 /* NT-function control register (DWORD) */
351 #define IDT_SW_NTP12_NTCTL 0x19400U
352 /* BAR setup/limit/base address registers (DWORD) */
353 #define IDT_SW_NTP12_BARSETUP0 0x19470U
354 #define IDT_SW_NTP12_BARLIMIT0 0x19474U
355 #define IDT_SW_NTP12_BARLTBASE0 0x19478U
356 #define IDT_SW_NTP12_BARUTBASE0 0x1947CU
357 #define IDT_SW_NTP12_BARSETUP1 0x19480U
358 #define IDT_SW_NTP12_BARLIMIT1 0x19484U
359 #define IDT_SW_NTP12_BARLTBASE1 0x19488U
360 #define IDT_SW_NTP12_BARUTBASE1 0x1948CU
361 #define IDT_SW_NTP12_BARSETUP2 0x19490U
362 #define IDT_SW_NTP12_BARLIMIT2 0x19494U
363 #define IDT_SW_NTP12_BARLTBASE2 0x19498U
364 #define IDT_SW_NTP12_BARUTBASE2 0x1949CU
365 #define IDT_SW_NTP12_BARSETUP3 0x194A0U
366 #define IDT_SW_NTP12_BARLIMIT3 0x194A4U
367 #define IDT_SW_NTP12_BARLTBASE3 0x194A8U
368 #define IDT_SW_NTP12_BARUTBASE3 0x194ACU
369 #define IDT_SW_NTP12_BARSETUP4 0x194B0U
370 #define IDT_SW_NTP12_BARLIMIT4 0x194B4U
371 #define IDT_SW_NTP12_BARLTBASE4 0x194B8U
372 #define IDT_SW_NTP12_BARUTBASE4 0x194BCU
373 #define IDT_SW_NTP12_BARSETUP5 0x194C0U
374 #define IDT_SW_NTP12_BARLIMIT5 0x194C4U
375 #define IDT_SW_NTP12_BARLTBASE5 0x194C8U
376 #define IDT_SW_NTP12_BARUTBASE5 0x194CCU
377 /* PCI Express command/status and link control/status registers (WORD+WORD) */
378 #define IDT_SW_NTP16_PCIECMDSTS 0x21004U
379 #define IDT_SW_NTP16_PCIELCTLSTS 0x21050U
380 /* NT-function control register (DWORD) */
381 #define IDT_SW_NTP16_NTCTL 0x21400U
382 /* BAR setup/limit/base address registers (DWORD) */
383 #define IDT_SW_NTP16_BARSETUP0 0x21470U
384 #define IDT_SW_NTP16_BARLIMIT0 0x21474U
385 #define IDT_SW_NTP16_BARLTBASE0 0x21478U
386 #define IDT_SW_NTP16_BARUTBASE0 0x2147CU
387 #define IDT_SW_NTP16_BARSETUP1 0x21480U
388 #define IDT_SW_NTP16_BARLIMIT1 0x21484U
389 #define IDT_SW_NTP16_BARLTBASE1 0x21488U
390 #define IDT_SW_NTP16_BARUTBASE1 0x2148CU
391 #define IDT_SW_NTP16_BARSETUP2 0x21490U
392 #define IDT_SW_NTP16_BARLIMIT2 0x21494U
393 #define IDT_SW_NTP16_BARLTBASE2 0x21498U
394 #define IDT_SW_NTP16_BARUTBASE2 0x2149CU
395 #define IDT_SW_NTP16_BARSETUP3 0x214A0U
396 #define IDT_SW_NTP16_BARLIMIT3 0x214A4U
397 #define IDT_SW_NTP16_BARLTBASE3 0x214A8U
398 #define IDT_SW_NTP16_BARUTBASE3 0x214ACU
399 #define IDT_SW_NTP16_BARSETUP4 0x214B0U
400 #define IDT_SW_NTP16_BARLIMIT4 0x214B4U
401 #define IDT_SW_NTP16_BARLTBASE4 0x214B8U
402 #define IDT_SW_NTP16_BARUTBASE4 0x214BCU
403 #define IDT_SW_NTP16_BARSETUP5 0x214C0U
404 #define IDT_SW_NTP16_BARLIMIT5 0x214C4U
405 #define IDT_SW_NTP16_BARLTBASE5 0x214C8U
406 #define IDT_SW_NTP16_BARUTBASE5 0x214CCU
407 /* PCI Express command/status and link control/status registers (WORD+WORD) */
408 #define IDT_SW_NTP20_PCIECMDSTS 0x29004U
409 #define IDT_SW_NTP20_PCIELCTLSTS 0x29050U
410 /* NT-function control register (DWORD) */
411 #define IDT_SW_NTP20_NTCTL 0x29400U
412 /* BAR setup/limit/base address registers (DWORD) */
413 #define IDT_SW_NTP20_BARSETUP0 0x29470U
414 #define IDT_SW_NTP20_BARLIMIT0 0x29474U
415 #define IDT_SW_NTP20_BARLTBASE0 0x29478U
416 #define IDT_SW_NTP20_BARUTBASE0 0x2947CU
417 #define IDT_SW_NTP20_BARSETUP1 0x29480U
418 #define IDT_SW_NTP20_BARLIMIT1 0x29484U
419 #define IDT_SW_NTP20_BARLTBASE1 0x29488U
420 #define IDT_SW_NTP20_BARUTBASE1 0x2948CU
421 #define IDT_SW_NTP20_BARSETUP2 0x29490U
422 #define IDT_SW_NTP20_BARLIMIT2 0x29494U
423 #define IDT_SW_NTP20_BARLTBASE2 0x29498U
424 #define IDT_SW_NTP20_BARUTBASE2 0x2949CU
425 #define IDT_SW_NTP20_BARSETUP3 0x294A0U
426 #define IDT_SW_NTP20_BARLIMIT3 0x294A4U
427 #define IDT_SW_NTP20_BARLTBASE3 0x294A8U
428 #define IDT_SW_NTP20_BARUTBASE3 0x294ACU
429 #define IDT_SW_NTP20_BARSETUP4 0x294B0U
430 #define IDT_SW_NTP20_BARLIMIT4 0x294B4U
431 #define IDT_SW_NTP20_BARLTBASE4 0x294B8U
432 #define IDT_SW_NTP20_BARUTBASE4 0x294BCU
433 #define IDT_SW_NTP20_BARSETUP5 0x294C0U
434 #define IDT_SW_NTP20_BARLIMIT5 0x294C4U
435 #define IDT_SW_NTP20_BARLTBASE5 0x294C8U
436 #define IDT_SW_NTP20_BARUTBASE5 0x294CCU
437 /* IDT PCIe-switch control register (DWORD) */
438 #define IDT_SW_CTL 0x3E000U
439 /* Boot Configuration Vector Status (DWORD) */
440 #define IDT_SW_BCVSTS 0x3E004U
441 /* Port Clocking Mode (DWORD) */
442 #define IDT_SW_PCLKMODE 0x3E008U
443 /* Reset Drain Delay (DWORD) */
444 #define IDT_SW_RDRAINDELAY 0x3E080U
445 /* Port Operating Mode Change Drain Delay (DWORD) */
446 #define IDT_SW_POMCDELAY 0x3E084U
447 /* Side Effect Delay (DWORD) */
448 #define IDT_SW_SEDELAY 0x3E088U
449 /* Upstream Secondary Bus Reset Delay (DWORD) */
450 #define IDT_SW_SSBRDELAY 0x3E08CU
451 /* Switch partition N Control/Status/Failover registers */
452 #define IDT_SW_SWPART0CTL 0x3E100U
453 #define IDT_SW_SWPART0STS 0x3E104U
454 #define IDT_SW_SWPART0FCTL 0x3E108U
455 #define IDT_SW_SWPART1CTL 0x3E120U
456 #define IDT_SW_SWPART1STS 0x3E124U
457 #define IDT_SW_SWPART1FCTL 0x3E128U
458 #define IDT_SW_SWPART2CTL 0x3E140U
459 #define IDT_SW_SWPART2STS 0x3E144U
460 #define IDT_SW_SWPART2FCTL 0x3E148U
461 #define IDT_SW_SWPART3CTL 0x3E160U
462 #define IDT_SW_SWPART3STS 0x3E164U
463 #define IDT_SW_SWPART3FCTL 0x3E168U
464 #define IDT_SW_SWPART4CTL 0x3E180U
465 #define IDT_SW_SWPART4STS 0x3E184U
466 #define IDT_SW_SWPART4FCTL 0x3E188U
467 #define IDT_SW_SWPART5CTL 0x3E1A0U
468 #define IDT_SW_SWPART5STS 0x3E1A4U
469 #define IDT_SW_SWPART5FCTL 0x3E1A8U
470 #define IDT_SW_SWPART6CTL 0x3E1C0U
471 #define IDT_SW_SWPART6STS 0x3E1C4U
472 #define IDT_SW_SWPART6FCTL 0x3E1C8U
473 #define IDT_SW_SWPART7CTL 0x3E1E0U
474 #define IDT_SW_SWPART7STS 0x3E1E4U
475 #define IDT_SW_SWPART7FCTL 0x3E1E8U
476 /* Switch port N control and status registers */
477 #define IDT_SW_SWPORT0CTL 0x3E200U
478 #define IDT_SW_SWPORT0STS 0x3E204U
479 #define IDT_SW_SWPORT0FCTL 0x3E208U
480 #define IDT_SW_SWPORT2CTL 0x3E240U
481 #define IDT_SW_SWPORT2STS 0x3E244U
482 #define IDT_SW_SWPORT2FCTL 0x3E248U
483 #define IDT_SW_SWPORT4CTL 0x3E280U
484 #define IDT_SW_SWPORT4STS 0x3E284U
485 #define IDT_SW_SWPORT4FCTL 0x3E288U
486 #define IDT_SW_SWPORT6CTL 0x3E2C0U
487 #define IDT_SW_SWPORT6STS 0x3E2C4U
488 #define IDT_SW_SWPORT6FCTL 0x3E2C8U
489 #define IDT_SW_SWPORT8CTL 0x3E300U
490 #define IDT_SW_SWPORT8STS 0x3E304U
491 #define IDT_SW_SWPORT8FCTL 0x3E308U
492 #define IDT_SW_SWPORT12CTL 0x3E380U
493 #define IDT_SW_SWPORT12STS 0x3E384U
494 #define IDT_SW_SWPORT12FCTL 0x3E388U
495 #define IDT_SW_SWPORT16CTL 0x3E400U
496 #define IDT_SW_SWPORT16STS 0x3E404U
497 #define IDT_SW_SWPORT16FCTL 0x3E408U
498 #define IDT_SW_SWPORT20CTL 0x3E480U
499 #define IDT_SW_SWPORT20STS 0x3E484U
500 #define IDT_SW_SWPORT20FCTL 0x3E488U
501 /* Switch Event registers */
502 /* Switch Event Status/Mask/Partition mask (DWORD) */
503 #define IDT_SW_SESTS 0x3EC00U
504 #define IDT_SW_SEMSK 0x3EC04U
505 #define IDT_SW_SEPMSK 0x3EC08U
506 /* Switch Event Link Up/Down Status/Mask (DWORD) */
507 #define IDT_SW_SELINKUPSTS 0x3EC0CU
508 #define IDT_SW_SELINKUPMSK 0x3EC10U
509 #define IDT_SW_SELINKDNSTS 0x3EC14U
510 #define IDT_SW_SELINKDNMSK 0x3EC18U
511 /* Switch Event Fundamental Reset Status/Mask (DWORD) */
512 #define IDT_SW_SEFRSTSTS 0x3EC1CU
513 #define IDT_SW_SEFRSTMSK 0x3EC20U
514 /* Switch Event Hot Reset Status/Mask (DWORD) */
515 #define IDT_SW_SEHRSTSTS 0x3EC24U
516 #define IDT_SW_SEHRSTMSK 0x3EC28U
517 /* Switch Event Failover Mask (DWORD) */
518 #define IDT_SW_SEFOVRMSK 0x3EC2CU
519 /* Switch Event Global Signal Status/Mask (DWORD) */
520 #define IDT_SW_SEGSIGSTS 0x3EC30U
521 #define IDT_SW_SEGSIGMSK 0x3EC34U
522 /* NT Global Doorbell Status (DWORD) */
523 #define IDT_SW_GDBELLSTS 0x3EC3CU
524 /* Switch partition N message M control (msgs routing table) (DWORD) */
525 #define IDT_SW_SWP0MSGCTL0 0x3EE00U
526 #define IDT_SW_SWP1MSGCTL0 0x3EE04U
527 #define IDT_SW_SWP2MSGCTL0 0x3EE08U
528 #define IDT_SW_SWP3MSGCTL0 0x3EE0CU
529 #define IDT_SW_SWP4MSGCTL0 0x3EE10U
530 #define IDT_SW_SWP5MSGCTL0 0x3EE14U
531 #define IDT_SW_SWP6MSGCTL0 0x3EE18U
532 #define IDT_SW_SWP7MSGCTL0 0x3EE1CU
533 #define IDT_SW_SWP0MSGCTL1 0x3EE20U
534 #define IDT_SW_SWP1MSGCTL1 0x3EE24U
535 #define IDT_SW_SWP2MSGCTL1 0x3EE28U
536 #define IDT_SW_SWP3MSGCTL1 0x3EE2CU
537 #define IDT_SW_SWP4MSGCTL1 0x3EE30U
538 #define IDT_SW_SWP5MSGCTL1 0x3EE34U
539 #define IDT_SW_SWP6MSGCTL1 0x3EE38U
540 #define IDT_SW_SWP7MSGCTL1 0x3EE3CU
541 #define IDT_SW_SWP0MSGCTL2 0x3EE40U
542 #define IDT_SW_SWP1MSGCTL2 0x3EE44U
543 #define IDT_SW_SWP2MSGCTL2 0x3EE48U
544 #define IDT_SW_SWP3MSGCTL2 0x3EE4CU
545 #define IDT_SW_SWP4MSGCTL2 0x3EE50U
546 #define IDT_SW_SWP5MSGCTL2 0x3EE54U
547 #define IDT_SW_SWP6MSGCTL2 0x3EE58U
548 #define IDT_SW_SWP7MSGCTL2 0x3EE5CU
549 #define IDT_SW_SWP0MSGCTL3 0x3EE60U
550 #define IDT_SW_SWP1MSGCTL3 0x3EE64U
551 #define IDT_SW_SWP2MSGCTL3 0x3EE68U
552 #define IDT_SW_SWP3MSGCTL3 0x3EE6CU
553 #define IDT_SW_SWP4MSGCTL3 0x3EE70U
554 #define IDT_SW_SWP5MSGCTL3 0x3EE74U
555 #define IDT_SW_SWP6MSGCTL3 0x3EE78U
556 #define IDT_SW_SWP7MSGCTL3 0x3EE7CU
557 /* SMBus Status and Control registers (DWORD) */
558 #define IDT_SW_SMBUSSTS 0x3F188U
559 #define IDT_SW_SMBUSCTL 0x3F18CU
560 /* Serial EEPROM Interface (DWORD) */
561 #define IDT_SW_EEPROMINTF 0x3F190U
562 /* MBus I/O Expander Address N (DWORD) */
563 #define IDT_SW_IOEXPADDR0 0x3F198U
564 #define IDT_SW_IOEXPADDR1 0x3F19CU
565 #define IDT_SW_IOEXPADDR2 0x3F1A0U
566 #define IDT_SW_IOEXPADDR3 0x3F1A4U
567 #define IDT_SW_IOEXPADDR4 0x3F1A8U
568 #define IDT_SW_IOEXPADDR5 0x3F1ACU
569 /* General Purpose Events Control and Status registers (DWORD) */
570 #define IDT_SW_GPECTL 0x3F1B0U
571 #define IDT_SW_GPESTS 0x3F1B4U
572 /* Temperature sensor Control/Status/Alarm/Adjustment/Slope registers */
573 #define IDT_SW_TMPCTL 0x3F1D4U
574 #define IDT_SW_TMPSTS 0x3F1D8U
575 #define IDT_SW_TMPALARM 0x3F1DCU
576 #define IDT_SW_TMPADJ 0x3F1E0U
577 #define IDT_SW_TSSLOPE 0x3F1E4U
578 /* SMBus Configuration Block header log (DWORD) */
579 #define IDT_SW_SMBUSCBHL 0x3F1E8U
580
581 /*
582 * Common registers related constants
583 * @IDT_REG_ALIGN: Registers alignment used in the driver
584 * @IDT_REG_PCI_MAX: Maximum PCI configuration space register value
585 * @IDT_REG_SW_MAX: Maximum global register value
586 */
587 #define IDT_REG_ALIGN 4
588 #define IDT_REG_PCI_MAX 0x00FFFU
589 #define IDT_REG_SW_MAX 0x3FFFFU
590
591 /*
592 * PCICMDSTS register fields related constants
593 * @IDT_PCICMDSTS_IOAE: I/O access enable
594 * @IDT_PCICMDSTS_MAE: Memory access enable
595 * @IDT_PCICMDSTS_BME: Bus master enable
596 */
597 #define IDT_PCICMDSTS_IOAE 0x00000001U
598 #define IDT_PCICMDSTS_MAE 0x00000002U
599 #define IDT_PCICMDSTS_BME 0x00000004U
600
601 /*
602 * PCIEDCAP register fields related constants
603 * @IDT_PCIEDCAP_MPAYLOAD_MASK: Maximum payload size mask
604 * @IDT_PCIEDCAP_MPAYLOAD_FLD: Maximum payload size field offset
605 * @IDT_PCIEDCAP_MPAYLOAD_S128: Max supported payload size of 128 bytes
606 * @IDT_PCIEDCAP_MPAYLOAD_S256: Max supported payload size of 256 bytes
607 * @IDT_PCIEDCAP_MPAYLOAD_S512: Max supported payload size of 512 bytes
608 * @IDT_PCIEDCAP_MPAYLOAD_S1024: Max supported payload size of 1024 bytes
609 * @IDT_PCIEDCAP_MPAYLOAD_S2048: Max supported payload size of 2048 bytes
610 */
611 #define IDT_PCIEDCAP_MPAYLOAD_MASK 0x00000007U
612 #define IDT_PCIEDCAP_MPAYLOAD_FLD 0
613 #define IDT_PCIEDCAP_MPAYLOAD_S128 0x00000000U
614 #define IDT_PCIEDCAP_MPAYLOAD_S256 0x00000001U
615 #define IDT_PCIEDCAP_MPAYLOAD_S512 0x00000002U
616 #define IDT_PCIEDCAP_MPAYLOAD_S1024 0x00000003U
617 #define IDT_PCIEDCAP_MPAYLOAD_S2048 0x00000004U
618
619 /*
620 * PCIEDCTLSTS registers fields related constants
621 * @IDT_PCIEDCTL_MPS_MASK: Maximum payload size mask
622 * @IDT_PCIEDCTL_MPS_FLD: MPS field offset
623 * @IDT_PCIEDCTL_MPS_S128: Max payload size of 128 bytes
624 * @IDT_PCIEDCTL_MPS_S256: Max payload size of 256 bytes
625 * @IDT_PCIEDCTL_MPS_S512: Max payload size of 512 bytes
626 * @IDT_PCIEDCTL_MPS_S1024: Max payload size of 1024 bytes
627 * @IDT_PCIEDCTL_MPS_S2048: Max payload size of 2048 bytes
628 * @IDT_PCIEDCTL_MPS_S4096: Max payload size of 4096 bytes
629 */
630 #define IDT_PCIEDCTLSTS_MPS_MASK 0x000000E0U
631 #define IDT_PCIEDCTLSTS_MPS_FLD 5
632 #define IDT_PCIEDCTLSTS_MPS_S128 0x00000000U
633 #define IDT_PCIEDCTLSTS_MPS_S256 0x00000020U
634 #define IDT_PCIEDCTLSTS_MPS_S512 0x00000040U
635 #define IDT_PCIEDCTLSTS_MPS_S1024 0x00000060U
636 #define IDT_PCIEDCTLSTS_MPS_S2048 0x00000080U
637 #define IDT_PCIEDCTLSTS_MPS_S4096 0x000000A0U
638
639 /*
640 * PCIELCAP register fields related constants
641 * @IDT_PCIELCAP_PORTNUM_MASK: Port number field mask
642 * @IDT_PCIELCAP_PORTNUM_FLD: Port number field offset
643 */
644 #define IDT_PCIELCAP_PORTNUM_MASK 0xFF000000U
645 #define IDT_PCIELCAP_PORTNUM_FLD 24
646
647 /*
648 * PCIELCTLSTS registers fields related constants
649 * @IDT_PCIELSTS_CLS_MASK: Current link speed mask
650 * @IDT_PCIELSTS_CLS_FLD: Current link speed field offset
651 * @IDT_PCIELSTS_NLW_MASK: Negotiated link width mask
652 * @IDT_PCIELSTS_NLW_FLD: Negotiated link width field offset
653 * @IDT_PCIELSTS_SCLK_COM: Common slot clock configuration
654 */
655 #define IDT_PCIELCTLSTS_CLS_MASK 0x000F0000U
656 #define IDT_PCIELCTLSTS_CLS_FLD 16
657 #define IDT_PCIELCTLSTS_NLW_MASK 0x03F00000U
658 #define IDT_PCIELCTLSTS_NLW_FLD 20
659 #define IDT_PCIELCTLSTS_SCLK_COM 0x10000000U
660
661 /*
662 * NTCTL register fields related constants
663 * @IDT_NTCTL_IDPROTDIS: ID Protection check disable (disable MTBL)
664 * @IDT_NTCTL_CPEN: Completion enable
665 * @IDT_NTCTL_RNS: Request no snoop processing (if MTBL disabled)
666 * @IDT_NTCTL_ATP: Address type processing (if MTBL disabled)
667 */
668 #define IDT_NTCTL_IDPROTDIS 0x00000001U
669 #define IDT_NTCTL_CPEN 0x00000002U
670 #define IDT_NTCTL_RNS 0x00000004U
671 #define IDT_NTCTL_ATP 0x00000008U
672
673 /*
674 * NTINTSTS register fields related constants
675 * @IDT_NTINTSTS_MSG: Message interrupt bit
676 * @IDT_NTINTSTS_DBELL: Doorbell interrupt bit
677 * @IDT_NTINTSTS_SEVENT: Switch Event interrupt bit
678 * @IDT_NTINTSTS_TMPSENSOR: Temperature sensor interrupt bit
679 */
680 #define IDT_NTINTSTS_MSG 0x00000001U
681 #define IDT_NTINTSTS_DBELL 0x00000002U
682 #define IDT_NTINTSTS_SEVENT 0x00000008U
683 #define IDT_NTINTSTS_TMPSENSOR 0x00000080U
684
685 /*
686 * NTINTMSK register fields related constants
687 * @IDT_NTINTMSK_MSG: Message interrupt mask bit
688 * @IDT_NTINTMSK_DBELL: Doorbell interrupt mask bit
689 * @IDT_NTINTMSK_SEVENT: Switch Event interrupt mask bit
690 * @IDT_NTINTMSK_TMPSENSOR: Temperature sensor interrupt mask bit
691 * @IDT_NTINTMSK_ALL: NTB-related interrupts mask
692 */
693 #define IDT_NTINTMSK_MSG 0x00000001U
694 #define IDT_NTINTMSK_DBELL 0x00000002U
695 #define IDT_NTINTMSK_SEVENT 0x00000008U
696 #define IDT_NTINTMSK_TMPSENSOR 0x00000080U
697 #define IDT_NTINTMSK_ALL \
698 (IDT_NTINTMSK_MSG | IDT_NTINTMSK_DBELL | IDT_NTINTMSK_SEVENT)
699
700 /*
701 * NTGSIGNAL register fields related constants
702 * @IDT_NTGSIGNAL_SET: Set global signal of the local partition
703 */
704 #define IDT_NTGSIGNAL_SET 0x00000001U
705
706 /*
707 * BARSETUP register fields related constants
708 * @IDT_BARSETUP_TYPE_MASK: Mask of the TYPE field
709 * @IDT_BARSETUP_TYPE_32: 32-bit addressing BAR
710 * @IDT_BARSETUP_TYPE_64: 64-bit addressing BAR
711 * @IDT_BARSETUP_PREF: Value of the BAR prefetchable field
712 * @IDT_BARSETUP_SIZE_MASK: Mask of the SIZE field
713 * @IDT_BARSETUP_SIZE_FLD: SIZE field offset
714 * @IDT_BARSETUP_SIZE_CFG: SIZE field value in case of config space MODE
715 * @IDT_BARSETUP_MODE_CFG: Configuration space BAR mode
716 * @IDT_BARSETUP_ATRAN_MASK: ATRAN field mask
717 * @IDT_BARSETUP_ATRAN_FLD: ATRAN field offset
718 * @IDT_BARSETUP_ATRAN_DIR: Direct address translation memory window
719 * @IDT_BARSETUP_ATRAN_LUT12: 12-entry lookup table
720 * @IDT_BARSETUP_ATRAN_LUT24: 24-entry lookup table
721 * @IDT_BARSETUP_TPART_MASK: TPART field mask
722 * @IDT_BARSETUP_TPART_FLD: TPART field offset
723 * @IDT_BARSETUP_EN: BAR enable bit
724 */
725 #define IDT_BARSETUP_TYPE_MASK 0x00000006U
726 #define IDT_BARSETUP_TYPE_FLD 0
727 #define IDT_BARSETUP_TYPE_32 0x00000000U
728 #define IDT_BARSETUP_TYPE_64 0x00000004U
729 #define IDT_BARSETUP_PREF 0x00000008U
730 #define IDT_BARSETUP_SIZE_MASK 0x000003F0U
731 #define IDT_BARSETUP_SIZE_FLD 4
732 #define IDT_BARSETUP_SIZE_CFG 0x000000C0U
733 #define IDT_BARSETUP_MODE_CFG 0x00000400U
734 #define IDT_BARSETUP_ATRAN_MASK 0x00001800U
735 #define IDT_BARSETUP_ATRAN_FLD 11
736 #define IDT_BARSETUP_ATRAN_DIR 0x00000000U
737 #define IDT_BARSETUP_ATRAN_LUT12 0x00000800U
738 #define IDT_BARSETUP_ATRAN_LUT24 0x00001000U
739 #define IDT_BARSETUP_TPART_MASK 0x0000E000U
740 #define IDT_BARSETUP_TPART_FLD 13
741 #define IDT_BARSETUP_EN 0x80000000U
742
743 /*
744 * NTMTBLDATA register fields related constants
745 * @IDT_NTMTBLDATA_VALID: Set the MTBL entry being valid
746 * @IDT_NTMTBLDATA_REQID_MASK: Bus:Device:Function field mask
747 * @IDT_NTMTBLDATA_REQID_FLD: Bus:Device:Function field offset
748 * @IDT_NTMTBLDATA_PART_MASK: Partition field mask
749 * @IDT_NTMTBLDATA_PART_FLD: Partition field offset
750 * @IDT_NTMTBLDATA_ATP_TRANS: Enable AT field translation on request TLPs
751 * @IDT_NTMTBLDATA_CNS_INV: Enable No Snoop attribute inversion of
752 * Completion TLPs
753 * @IDT_NTMTBLDATA_RNS_INV: Enable No Snoop attribute inversion of
754 * Request TLPs
755 */
756 #define IDT_NTMTBLDATA_VALID 0x00000001U
757 #define IDT_NTMTBLDATA_REQID_MASK 0x0001FFFEU
758 #define IDT_NTMTBLDATA_REQID_FLD 1
759 #define IDT_NTMTBLDATA_PART_MASK 0x000E0000U
760 #define IDT_NTMTBLDATA_PART_FLD 17
761 #define IDT_NTMTBLDATA_ATP_TRANS 0x20000000U
762 #define IDT_NTMTBLDATA_CNS_INV 0x40000000U
763 #define IDT_NTMTBLDATA_RNS_INV 0x80000000U
764
765 /*
766 * REQIDCAP register fields related constants
767 * @IDT_REQIDCAP_REQID_MASK: Request ID field mask
768 * @IDT_REQIDCAP_REQID_FLD: Request ID field offset
769 */
770 #define IDT_REQIDCAP_REQID_MASK 0x0000FFFFU
771 #define IDT_REQIDCAP_REQID_FLD 0
772
773 /*
774 * LUTOFFSET register fields related constants
775 * @IDT_LUTOFFSET_INDEX_MASK: Lookup table index field mask
776 * @IDT_LUTOFFSET_INDEX_FLD: Lookup table index field offset
777 * @IDT_LUTOFFSET_BAR_MASK: Lookup table BAR select field mask
778 * @IDT_LUTOFFSET_BAR_FLD: Lookup table BAR select field offset
779 */
780 #define IDT_LUTOFFSET_INDEX_MASK 0x0000001FU
781 #define IDT_LUTOFFSET_INDEX_FLD 0
782 #define IDT_LUTOFFSET_BAR_MASK 0x00000700U
783 #define IDT_LUTOFFSET_BAR_FLD 8
784
785 /*
786 * LUTUDATA register fields related constants
787 * @IDT_LUTUDATA_PART_MASK: Partition field mask
788 * @IDT_LUTUDATA_PART_FLD: Partition field offset
789 * @IDT_LUTUDATA_VALID: Lookup table entry valid bit
790 */
791 #define IDT_LUTUDATA_PART_MASK 0x0000000FU
792 #define IDT_LUTUDATA_PART_FLD 0
793 #define IDT_LUTUDATA_VALID 0x80000000U
794
795 /*
796 * SWPARTxSTS register fields related constants
797 * @IDT_SWPARTxSTS_SCI: Switch partition state change initiated
798 * @IDT_SWPARTxSTS_SCC: Switch partition state change completed
799 * @IDT_SWPARTxSTS_STATE_MASK: Switch partition state mask
800 * @IDT_SWPARTxSTS_STATE_FLD: Switch partition state field offset
801 * @IDT_SWPARTxSTS_STATE_DIS: Switch partition disabled
802 * @IDT_SWPARTxSTS_STATE_ACT: Switch partition enabled
803 * @IDT_SWPARTxSTS_STATE_RES: Switch partition in reset
804 * @IDT_SWPARTxSTS_US: Switch partition has upstream port
805 * @IDT_SWPARTxSTS_USID_MASK: Switch partition upstream port ID mask
806 * @IDT_SWPARTxSTS_USID_FLD: Switch partition upstream port ID field offset
807 * @IDT_SWPARTxSTS_NT: Upstream port has NT function
808 * @IDT_SWPARTxSTS_DMA: Upstream port has DMA function
809 */
810 #define IDT_SWPARTxSTS_SCI 0x00000001U
811 #define IDT_SWPARTxSTS_SCC 0x00000002U
812 #define IDT_SWPARTxSTS_STATE_MASK 0x00000060U
813 #define IDT_SWPARTxSTS_STATE_FLD 5
814 #define IDT_SWPARTxSTS_STATE_DIS 0x00000000U
815 #define IDT_SWPARTxSTS_STATE_ACT 0x00000020U
816 #define IDT_SWPARTxSTS_STATE_RES 0x00000060U
817 #define IDT_SWPARTxSTS_US 0x00000100U
818 #define IDT_SWPARTxSTS_USID_MASK 0x00003E00U
819 #define IDT_SWPARTxSTS_USID_FLD 9
820 #define IDT_SWPARTxSTS_NT 0x00004000U
821 #define IDT_SWPARTxSTS_DMA 0x00008000U
822
823 /*
824 * SWPORTxSTS register fields related constants
825 * @IDT_SWPORTxSTS_OMCI: Operation mode change initiated
826 * @IDT_SWPORTxSTS_OMCC: Operation mode change completed
827 * @IDT_SWPORTxSTS_LINKUP: Link up status
828 * @IDT_SWPORTxSTS_DS: Port lanes behave as downstream lanes
829 * @IDT_SWPORTxSTS_MODE_MASK: Port mode field mask
830 * @IDT_SWPORTxSTS_MODE_FLD: Port mode field offset
831 * @IDT_SWPORTxSTS_MODE_DIS: Port mode - disabled
832 * @IDT_SWPORTxSTS_MODE_DS: Port mode - downstream switch port
833 * @IDT_SWPORTxSTS_MODE_US: Port mode - upstream switch port
834 * @IDT_SWPORTxSTS_MODE_NT: Port mode - NT function
835 * @IDT_SWPORTxSTS_MODE_USNT: Port mode - upstream switch port with NTB
836 * @IDT_SWPORTxSTS_MODE_UNAT: Port mode - unattached
837 * @IDT_SWPORTxSTS_MODE_USDMA: Port mode - upstream switch port with DMA
838 * @IDT_SWPORTxSTS_MODE_USNTDMA:Port mode - upstream port with NTB and DMA
839 * @IDT_SWPORTxSTS_MODE_NTDMA: Port mode - NT function with DMA
840 * @IDT_SWPORTxSTS_SWPART_MASK: Port partition field mask
841 * @IDT_SWPORTxSTS_SWPART_FLD: Port partition field offset
842 * @IDT_SWPORTxSTS_DEVNUM_MASK: Port device number field mask
843 * @IDT_SWPORTxSTS_DEVNUM_FLD: Port device number field offset
844 */
845 #define IDT_SWPORTxSTS_OMCI 0x00000001U
846 #define IDT_SWPORTxSTS_OMCC 0x00000002U
847 #define IDT_SWPORTxSTS_LINKUP 0x00000010U
848 #define IDT_SWPORTxSTS_DS 0x00000020U
849 #define IDT_SWPORTxSTS_MODE_MASK 0x000003C0U
850 #define IDT_SWPORTxSTS_MODE_FLD 6
851 #define IDT_SWPORTxSTS_MODE_DIS 0x00000000U
852 #define IDT_SWPORTxSTS_MODE_DS 0x00000040U
853 #define IDT_SWPORTxSTS_MODE_US 0x00000080U
854 #define IDT_SWPORTxSTS_MODE_NT 0x000000C0U
855 #define IDT_SWPORTxSTS_MODE_USNT 0x00000100U
856 #define IDT_SWPORTxSTS_MODE_UNAT 0x00000140U
857 #define IDT_SWPORTxSTS_MODE_USDMA 0x00000180U
858 #define IDT_SWPORTxSTS_MODE_USNTDMA 0x000001C0U
859 #define IDT_SWPORTxSTS_MODE_NTDMA 0x00000200U
860 #define IDT_SWPORTxSTS_SWPART_MASK 0x00001C00U
861 #define IDT_SWPORTxSTS_SWPART_FLD 10
862 #define IDT_SWPORTxSTS_DEVNUM_MASK 0x001F0000U
863 #define IDT_SWPORTxSTS_DEVNUM_FLD 16
864
865 /*
866 * SEMSK register fields related constants
867 * @IDT_SEMSK_LINKUP: Link Up event mask bit
868 * @IDT_SEMSK_LINKDN: Link Down event mask bit
869 * @IDT_SEMSK_GSIGNAL: Global Signal event mask bit
870 */
871 #define IDT_SEMSK_LINKUP 0x00000001U
872 #define IDT_SEMSK_LINKDN 0x00000002U
873 #define IDT_SEMSK_GSIGNAL 0x00000020U
874
875 /*
876 * SWPxMSGCTL register fields related constants
877 * @IDT_SWPxMSGCTL_REG_MASK: Register select field mask
878 * @IDT_SWPxMSGCTL_REG_FLD: Register select field offset
879 * @IDT_SWPxMSGCTL_PART_MASK: Partition select field mask
880 * @IDT_SWPxMSGCTL_PART_FLD: Partition select field offset
881 */
882 #define IDT_SWPxMSGCTL_REG_MASK 0x00000003U
883 #define IDT_SWPxMSGCTL_REG_FLD 0
884 #define IDT_SWPxMSGCTL_PART_MASK 0x00000070U
885 #define IDT_SWPxMSGCTL_PART_FLD 4
886
887 /*
888 * TMPCTL register fields related constants
889 * @IDT_TMPCTL_LTH_MASK: Low temperature threshold field mask
890 * @IDT_TMPCTL_LTH_FLD: Low temperature threshold field offset
891 * @IDT_TMPCTL_MTH_MASK: Middle temperature threshold field mask
892 * @IDT_TMPCTL_MTH_FLD: Middle temperature threshold field offset
893 * @IDT_TMPCTL_HTH_MASK: High temperature threshold field mask
894 * @IDT_TMPCTL_HTH_FLD: High temperature threshold field offset
895 * @IDT_TMPCTL_PDOWN: Temperature sensor power down
896 */
897 #define IDT_TMPCTL_LTH_MASK 0x000000FFU
898 #define IDT_TMPCTL_LTH_FLD 0
899 #define IDT_TMPCTL_MTH_MASK 0x0000FF00U
900 #define IDT_TMPCTL_MTH_FLD 8
901 #define IDT_TMPCTL_HTH_MASK 0x00FF0000U
902 #define IDT_TMPCTL_HTH_FLD 16
903 #define IDT_TMPCTL_PDOWN 0x80000000U
904
905 /*
906 * TMPSTS register fields related constants
907 * @IDT_TMPSTS_TEMP_MASK: Current temperature field mask
908 * @IDT_TMPSTS_TEMP_FLD: Current temperature field offset
909 * @IDT_TMPSTS_LTEMP_MASK: Lowest temperature field mask
910 * @IDT_TMPSTS_LTEMP_FLD: Lowest temperature field offset
911 * @IDT_TMPSTS_HTEMP_MASK: Highest temperature field mask
912 * @IDT_TMPSTS_HTEMP_FLD: Highest temperature field offset
913 */
914 #define IDT_TMPSTS_TEMP_MASK 0x000000FFU
915 #define IDT_TMPSTS_TEMP_FLD 0
916 #define IDT_TMPSTS_LTEMP_MASK 0x0000FF00U
917 #define IDT_TMPSTS_LTEMP_FLD 8
918 #define IDT_TMPSTS_HTEMP_MASK 0x00FF0000U
919 #define IDT_TMPSTS_HTEMP_FLD 16
920
921 /*
922 * TMPALARM register fields related constants
923 * @IDT_TMPALARM_LTEMP_MASK: Lowest temperature field mask
924 * @IDT_TMPALARM_LTEMP_FLD: Lowest temperature field offset
925 * @IDT_TMPALARM_HTEMP_MASK: Highest temperature field mask
926 * @IDT_TMPALARM_HTEMP_FLD: Highest temperature field offset
927 * @IDT_TMPALARM_IRQ_MASK: Alarm IRQ status mask
928 */
929 #define IDT_TMPALARM_LTEMP_MASK 0x0000FF00U
930 #define IDT_TMPALARM_LTEMP_FLD 8
931 #define IDT_TMPALARM_HTEMP_MASK 0x00FF0000U
932 #define IDT_TMPALARM_HTEMP_FLD 16
933 #define IDT_TMPALARM_IRQ_MASK 0x3F000000U
934
935 /*
936 * TMPADJ register fields related constants
937 * @IDT_TMPADJ_OFFSET_MASK: Temperature value offset field mask
938 * @IDT_TMPADJ_OFFSET_FLD: Temperature value offset field offset
939 */
940 #define IDT_TMPADJ_OFFSET_MASK 0x000000FFU
941 #define IDT_TMPADJ_OFFSET_FLD 0
942
943 /*
944 * Helper macro to get/set the corresponding field value
945 * @GET_FIELD: Retrieve the value of the corresponding field
946 * @SET_FIELD: Set the specified field up
947 * @IS_FLD_SET: Check whether a field is set with value
948 */
949 #define GET_FIELD(field, data) \
950 (((u32)(data) & IDT_ ##field## _MASK) >> IDT_ ##field## _FLD)
951 #define SET_FIELD(field, data, value) \
952 (((u32)(data) & ~IDT_ ##field## _MASK) | \
953 ((u32)(value) << IDT_ ##field## _FLD))
954 #define IS_FLD_SET(field, data, value) \
955 (((u32)(data) & IDT_ ##field## _MASK) == IDT_ ##field## _ ##value)
956
957 /*
958 * Useful registers masks:
959 * @IDT_DBELL_MASK: Doorbell bits mask
960 * @IDT_OUTMSG_MASK: Out messages status bits mask
961 * @IDT_INMSG_MASK: In messages status bits mask
962 * @IDT_MSG_MASK: Any message status bits mask
963 */
964 #define IDT_DBELL_MASK ((u32)0xFFFFFFFFU)
965 #define IDT_OUTMSG_MASK ((u32)0x0000000FU)
966 #define IDT_INMSG_MASK ((u32)0x000F0000U)
967 #define IDT_MSG_MASK (IDT_INMSG_MASK | IDT_OUTMSG_MASK)
968
969 /*
970 * Number of IDT NTB resources:
971 * @IDT_MSG_CNT: Number of Message registers
972 * @IDT_BAR_CNT: Number of BARs of each port
973 * @IDT_MTBL_ENTRY_CNT: Number mapping table entries
974 */
975 #define IDT_MSG_CNT 4
976 #define IDT_BAR_CNT 6
977 #define IDT_MTBL_ENTRY_CNT 64
978
979 /*
980 * General IDT PCIe-switch constant
981 * @IDT_MAX_NR_PORTS: Maximum number of ports per IDT PCIe-switch
982 * @IDT_MAX_NR_PARTS: Maximum number of partitions per IDT PCIe-switch
983 * @IDT_MAX_NR_PEERS: Maximum number of NT-peers per IDT PCIe-switch
984 * @IDT_MAX_NR_MWS: Maximum number of Memory Widows
985 * @IDT_PCIE_REGSIZE: Size of the registers in bytes
986 * @IDT_TRANS_ALIGN: Alignment of translated base address
987 * @IDT_DIR_SIZE_ALIGN: Alignment of size setting for direct translated MWs.
988 * Even though the lower 10 bits are reserved, they are
989 * treated by IDT as one's so basically there is no any
990 * alignment of size limit for DIR address translation.
991 */
992 #define IDT_MAX_NR_PORTS 24
993 #define IDT_MAX_NR_PARTS 8
994 #define IDT_MAX_NR_PEERS 8
995 #define IDT_MAX_NR_MWS 29
996 #define IDT_PCIE_REGSIZE 4
997 #define IDT_TRANS_ALIGN 4
998 #define IDT_DIR_SIZE_ALIGN 1
999
1000 /*
1001 * IDT PCIe-switch temperature sensor value limits
1002 * @IDT_TEMP_MIN_MDEG: Minimal integer value of temperature
1003 * @IDT_TEMP_MAX_MDEG: Maximal integer value of temperature
1004 * @IDT_TEMP_MIN_OFFSET:Minimal integer value of temperature offset
1005 * @IDT_TEMP_MAX_OFFSET:Maximal integer value of temperature offset
1006 */
1007 #define IDT_TEMP_MIN_MDEG 0
1008 #define IDT_TEMP_MAX_MDEG 127500
1009 #define IDT_TEMP_MIN_OFFSET -64000
1010 #define IDT_TEMP_MAX_OFFSET 63500
1011
1012 /*
1013 * Temperature sensor values enumeration
1014 * @IDT_TEMP_CUR: Current temperature
1015 * @IDT_TEMP_LOW: Lowest historical temperature
1016 * @IDT_TEMP_HIGH: Highest historical temperature
1017 * @IDT_TEMP_OFFSET: Current temperature offset
1018 */
1019 enum idt_temp_val {
1020 IDT_TEMP_CUR,
1021 IDT_TEMP_LOW,
1022 IDT_TEMP_HIGH,
1023 IDT_TEMP_OFFSET
1024 };
1025
1026 /*
1027 * IDT Memory Windows type. Depending on the device settings, IDT supports
1028 * Direct Address Translation MW registers and Lookup Table registers
1029 * @IDT_MW_DIR: Direct address translation
1030 * @IDT_MW_LUT12: 12-entry lookup table entry
1031 * @IDT_MW_LUT24: 24-entry lookup table entry
1032 *
1033 * NOTE These values are exactly the same as one of the BARSETUP ATRAN field
1034 */
1035 enum idt_mw_type {
1036 IDT_MW_DIR = 0x0,
1037 IDT_MW_LUT12 = 0x1,
1038 IDT_MW_LUT24 = 0x2
1039 };
1040
1041 /*
1042 * IDT PCIe-switch model private data
1043 * @name: Device name
1044 * @port_cnt: Total number of NT endpoint ports
1045 * @ports: Port ids
1046 */
1047 struct idt_89hpes_cfg {
1048 char *name;
1049 unsigned char port_cnt;
1050 unsigned char ports[];
1051 };
1052
1053 /*
1054 * Memory window configuration structure
1055 * @type: Type of the memory window (direct address translation or lookup
1056 * table)
1057 *
1058 * @bar: PCIe BAR the memory window referenced to
1059 * @idx: Index of the memory window within the BAR
1060 *
1061 * @addr_align: Alignment of translated address
1062 * @size_align: Alignment of memory window size
1063 * @size_max: Maximum size of memory window
1064 */
1065 struct idt_mw_cfg {
1066 enum idt_mw_type type;
1067
1068 unsigned char bar;
1069 unsigned char idx;
1070
1071 u64 addr_align;
1072 u64 size_align;
1073 u64 size_max;
1074 };
1075
1076 /*
1077 * Description structure of peer IDT NT-functions:
1078 * @port: NT-function port
1079 * @part: NT-function partition
1080 *
1081 * @mw_cnt: Number of memory windows supported by NT-function
1082 * @mws: Array of memory windows descriptors
1083 */
1084 struct idt_ntb_peer {
1085 unsigned char port;
1086 unsigned char part;
1087
1088 unsigned char mw_cnt;
1089 struct idt_mw_cfg *mws;
1090 };
1091
1092 /*
1093 * Description structure of local IDT NT-function:
1094 * @ntb: Linux NTB-device description structure
1095 * @swcfg: Pointer to the structure of local IDT PCIe-switch
1096 * specific cofnfigurations
1097 *
1098 * @port: Local NT-function port
1099 * @part: Local NT-function partition
1100 *
1101 * @peer_cnt: Number of peers with activated NTB-function
1102 * @peers: Array of peers descripting structures
1103 * @port_idx_map: Map of port number -> peer index
1104 * @part_idx_map: Map of partition number -> peer index
1105 *
1106 * @mtbl_lock: Mapping table access lock
1107 *
1108 * @mw_cnt: Number of memory windows supported by NT-function
1109 * @mws: Array of memory windows descriptors
1110 * @lut_lock: Lookup table access lock
1111 *
1112 * @msg_locks: Message registers mapping table lockers
1113 *
1114 * @cfgspc: Virtual address of the memory mapped configuration
1115 * space of the NT-function
1116 * @db_mask_lock: Doorbell mask register lock
1117 * @msg_mask_lock: Message mask register lock
1118 * @gasa_lock: GASA registers access lock
1119 *
1120 * @hwmon_mtx: Temperature sensor interface update mutex
1121 *
1122 * @dbgfs_info: DebugFS info node
1123 */
1124 struct idt_ntb_dev {
1125 struct ntb_dev ntb;
1126 struct idt_89hpes_cfg *swcfg;
1127
1128 unsigned char port;
1129 unsigned char part;
1130
1131 unsigned char peer_cnt;
1132 struct idt_ntb_peer peers[IDT_MAX_NR_PEERS];
1133 char port_idx_map[IDT_MAX_NR_PORTS];
1134 char part_idx_map[IDT_MAX_NR_PARTS];
1135
1136 spinlock_t mtbl_lock;
1137
1138 unsigned char mw_cnt;
1139 struct idt_mw_cfg *mws;
1140 spinlock_t lut_lock;
1141
1142 spinlock_t msg_locks[IDT_MSG_CNT];
1143
1144 void __iomem *cfgspc;
1145 spinlock_t db_mask_lock;
1146 spinlock_t msg_mask_lock;
1147 spinlock_t gasa_lock;
1148
1149 struct mutex hwmon_mtx;
1150
1151 struct dentry *dbgfs_info;
1152 };
1153 #define to_ndev_ntb(__ntb) container_of(__ntb, struct idt_ntb_dev, ntb)
1154
1155 /*
1156 * Descriptor of the IDT PCIe-switch BAR resources
1157 * @setup: BAR setup register
1158 * @limit: BAR limit register
1159 * @ltbase: Lower translated base address
1160 * @utbase: Upper translated base address
1161 */
1162 struct idt_ntb_bar {
1163 unsigned int setup;
1164 unsigned int limit;
1165 unsigned int ltbase;
1166 unsigned int utbase;
1167 };
1168
1169 /*
1170 * Descriptor of the IDT PCIe-switch message resources
1171 * @in: Inbound message register
1172 * @out: Outbound message register
1173 * @src: Source of inbound message register
1174 */
1175 struct idt_ntb_msg {
1176 unsigned int in;
1177 unsigned int out;
1178 unsigned int src;
1179 };
1180
1181 /*
1182 * Descriptor of the IDT PCIe-switch NT-function specific parameters in the
1183 * PCI Configuration Space
1184 * @bars: BARs related registers
1185 * @msgs: Messaging related registers
1186 */
1187 struct idt_ntb_regs {
1188 struct idt_ntb_bar bars[IDT_BAR_CNT];
1189 struct idt_ntb_msg msgs[IDT_MSG_CNT];
1190 };
1191
1192 /*
1193 * Descriptor of the IDT PCIe-switch port specific parameters in the
1194 * Global Configuration Space
1195 * @pcicmdsts: PCI command/status register
1196 * @pcielctlsts: PCIe link control/status
1197 *
1198 * @ctl: Port control register
1199 * @sts: Port status register
1200 *
1201 * @bars: BARs related registers
1202 */
1203 struct idt_ntb_port {
1204 unsigned int pcicmdsts;
1205 unsigned int pcielctlsts;
1206 unsigned int ntctl;
1207
1208 unsigned int ctl;
1209 unsigned int sts;
1210
1211 struct idt_ntb_bar bars[IDT_BAR_CNT];
1212 };
1213
1214 /*
1215 * Descriptor of the IDT PCIe-switch partition specific parameters.
1216 * @ctl: Partition control register in the Global Address Space
1217 * @sts: Partition status register in the Global Address Space
1218 * @msgctl: Messages control registers
1219 */
1220 struct idt_ntb_part {
1221 unsigned int ctl;
1222 unsigned int sts;
1223 unsigned int msgctl[IDT_MSG_CNT];
1224 };
1225
1226 #endif /* NTB_HW_IDT_H */