drivers/mmc/host/sdhci-s3c.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
to_s3c
sdhci_s3c_get_max_clk
sdhci_s3c_consider_clock
sdhci_s3c_set_clock
sdhci_s3c_get_min_clock
sdhci_cmu_get_max_clock
sdhci_cmu_get_min_clock
sdhci_cmu_set_clock
sdhci_s3c_parse_dt
sdhci_s3c_parse_dt
sdhci_s3c_get_driver_data
sdhci_s3c_probe
sdhci_s3c_remove
sdhci_s3c_suspend
sdhci_s3c_resume
sdhci_s3c_runtime_suspend
sdhci_s3c_runtime_resume
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* linux/drivers/mmc/host/sdhci-s3c.c
   3  *
   4  * Copyright 2008 Openmoko Inc.
   5  * Copyright 2008 Simtec Electronics
   6  *      Ben Dooks <ben@simtec.co.uk>
   7  *      http://armlinux.simtec.co.uk/
   8  *
   9  * SDHCI (HSMMC) support for Samsung SoC
  10  */
  11 
  12 #include <linux/spinlock.h>
  13 #include <linux/delay.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/platform_data/mmc-sdhci-s3c.h>
  17 #include <linux/slab.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20 #include <linux/gpio.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/pm.h>
  25 #include <linux/pm_runtime.h>
  26 
  27 #include <linux/mmc/host.h>
  28 
  29 #include "sdhci.h"
  30 
  31 #define MAX_BUS_CLK     (4)
  32 
  33 #define S3C_SDHCI_CONTROL2                      (0x80)
  34 #define S3C_SDHCI_CONTROL3                      (0x84)
  35 #define S3C64XX_SDHCI_CONTROL4                  (0x8C)
  36 
  37 #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR       BIT(31)
  38 #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK         BIT(30)
  39 #define S3C_SDHCI_CTRL2_CDINVRXD3               BIT(29)
  40 #define S3C_SDHCI_CTRL2_SLCARDOUT               BIT(28)
  41 
  42 #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK          (0xf << 24)
  43 #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT         (24)
  44 #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x)           ((_x) << 24)
  45 
  46 #define S3C_SDHCI_CTRL2_LVLDAT_MASK             (0xff << 16)
  47 #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT            (16)
  48 #define S3C_SDHCI_CTRL2_LVLDAT(_x)              ((_x) << 16)
  49 
  50 #define S3C_SDHCI_CTRL2_ENFBCLKTX               BIT(15)
  51 #define S3C_SDHCI_CTRL2_ENFBCLKRX               BIT(14)
  52 #define S3C_SDHCI_CTRL2_SDCDSEL                 BIT(13)
  53 #define S3C_SDHCI_CTRL2_SDSIGPC                 BIT(12)
  54 #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART        BIT(11)
  55 
  56 #define S3C_SDHCI_CTRL2_DFCNT_MASK              (0x3 << 9)
  57 #define S3C_SDHCI_CTRL2_DFCNT_SHIFT             (9)
  58 #define S3C_SDHCI_CTRL2_DFCNT_NONE              (0x0 << 9)
  59 #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK            (0x1 << 9)
  60 #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK           (0x2 << 9)
  61 #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK           (0x3 << 9)
  62 
  63 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD            BIT(8)
  64 #define S3C_SDHCI_CTRL2_RWAITMODE               BIT(7)
  65 #define S3C_SDHCI_CTRL2_DISBUFRD                BIT(6)
  66 
  67 #define S3C_SDHCI_CTRL2_SELBASECLK_MASK         (0x3 << 4)
  68 #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT        (4)
  69 #define S3C_SDHCI_CTRL2_PWRSYNC                 BIT(3)
  70 #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON          BIT(1)
  71 #define S3C_SDHCI_CTRL2_HWINITFIN               BIT(0)
  72 
  73 #define S3C_SDHCI_CTRL3_FCSEL3                  BIT(31)
  74 #define S3C_SDHCI_CTRL3_FCSEL2                  BIT(23)
  75 #define S3C_SDHCI_CTRL3_FCSEL1                  BIT(15)
  76 #define S3C_SDHCI_CTRL3_FCSEL0                  BIT(7)
  77 
  78 #define S3C_SDHCI_CTRL3_FIA3_MASK               (0x7f << 24)
  79 #define S3C_SDHCI_CTRL3_FIA3_SHIFT              (24)
  80 #define S3C_SDHCI_CTRL3_FIA3(_x)                ((_x) << 24)
  81 
  82 #define S3C_SDHCI_CTRL3_FIA2_MASK               (0x7f << 16)
  83 #define S3C_SDHCI_CTRL3_FIA2_SHIFT              (16)
  84 #define S3C_SDHCI_CTRL3_FIA2(_x)                ((_x) << 16)
  85 
  86 #define S3C_SDHCI_CTRL3_FIA1_MASK               (0x7f << 8)
  87 #define S3C_SDHCI_CTRL3_FIA1_SHIFT              (8)
  88 #define S3C_SDHCI_CTRL3_FIA1(_x)                ((_x) << 8)
  89 
  90 #define S3C_SDHCI_CTRL3_FIA0_MASK               (0x7f << 0)
  91 #define S3C_SDHCI_CTRL3_FIA0_SHIFT              (0)
  92 #define S3C_SDHCI_CTRL3_FIA0(_x)                ((_x) << 0)
  93 
  94 #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK       (0x3 << 16)
  95 #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT      (16)
  96 #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA        (0x0 << 16)
  97 #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA        (0x1 << 16)
  98 #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA        (0x2 << 16)
  99 #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA        (0x3 << 16)
 100 
 101 #define S3C64XX_SDHCI_CONTROL4_BUSY             (1)
 102 
 103 /**
 104  * struct sdhci_s3c - S3C SDHCI instance
 105  * @host: The SDHCI host created
 106  * @pdev: The platform device we where created from.
 107  * @ioarea: The resource created when we claimed the IO area.
 108  * @pdata: The platform data for this controller.
 109  * @cur_clk: The index of the current bus clock.
 110  * @clk_io: The clock for the internal bus interface.
 111  * @clk_bus: The clocks that are available for the SD/MMC bus clock.
 112  */
 113 struct sdhci_s3c {
 114         struct sdhci_host       *host;
 115         struct platform_device  *pdev;
 116         struct resource         *ioarea;
 117         struct s3c_sdhci_platdata *pdata;
 118         int                     cur_clk;
 119         int                     ext_cd_irq;
 120         int                     ext_cd_gpio;
 121 
 122         struct clk              *clk_io;
 123         struct clk              *clk_bus[MAX_BUS_CLK];
 124         unsigned long           clk_rates[MAX_BUS_CLK];
 125 
 126         bool                    no_divider;
 127 };
 128 
 129 /**
 130  * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
 131  * @sdhci_quirks: sdhci host specific quirks.
 132  *
 133  * Specifies platform specific configuration of sdhci controller.
 134  * Note: A structure for driver specific platform data is used for future
 135  * expansion of its usage.
 136  */
 137 struct sdhci_s3c_drv_data {
 138         unsigned int    sdhci_quirks;
 139         bool            no_divider;
 140 };
 141 
 142 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
 143 {
 144         return sdhci_priv(host);
 145 }
 146 
 147 /**
 148  * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
 149  * @host: The SDHCI host instance.
 150  *
 151  * Callback to return the maximum clock rate acheivable by the controller.
 152 */
 153 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
 154 {
 155         struct sdhci_s3c *ourhost = to_s3c(host);
 156         unsigned long rate, max = 0;
 157         int src;
 158 
 159         for (src = 0; src < MAX_BUS_CLK; src++) {
 160                 rate = ourhost->clk_rates[src];
 161                 if (rate > max)
 162                         max = rate;
 163         }
 164 
 165         return max;
 166 }
 167 
 168 /**
 169  * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
 170  * @ourhost: Our SDHCI instance.
 171  * @src: The source clock index.
 172  * @wanted: The clock frequency wanted.
 173  */
 174 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
 175                                              unsigned int src,
 176                                              unsigned int wanted)
 177 {
 178         unsigned long rate;
 179         struct clk *clksrc = ourhost->clk_bus[src];
 180         int shift;
 181 
 182         if (IS_ERR(clksrc))
 183                 return UINT_MAX;
 184 
 185         /*
 186          * If controller uses a non-standard clock division, find the best clock
 187          * speed possible with selected clock source and skip the division.
 188          */
 189         if (ourhost->no_divider) {
 190                 rate = clk_round_rate(clksrc, wanted);
 191                 return wanted - rate;
 192         }
 193 
 194         rate = ourhost->clk_rates[src];
 195 
 196         for (shift = 0; shift <= 8; ++shift) {
 197                 if ((rate >> shift) <= wanted)
 198                         break;
 199         }
 200 
 201         if (shift > 8) {
 202                 dev_dbg(&ourhost->pdev->dev,
 203                         "clk %d: rate %ld, min rate %lu > wanted %u\n",
 204                         src, rate, rate / 256, wanted);
 205                 return UINT_MAX;
 206         }
 207 
 208         dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
 209                 src, rate, wanted, rate >> shift);
 210 
 211         return wanted - (rate >> shift);
 212 }
 213 
 214 /**
 215  * sdhci_s3c_set_clock - callback on clock change
 216  * @host: The SDHCI host being changed
 217  * @clock: The clock rate being requested.
 218  *
 219  * When the card's clock is going to be changed, look at the new frequency
 220  * and find the best clock source to go with it.
 221 */
 222 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
 223 {
 224         struct sdhci_s3c *ourhost = to_s3c(host);
 225         unsigned int best = UINT_MAX;
 226         unsigned int delta;
 227         int best_src = 0;
 228         int src;
 229         u32 ctrl;
 230 
 231         host->mmc->actual_clock = 0;
 232 
 233         /* don't bother if the clock is going off. */
 234         if (clock == 0) {
 235                 sdhci_set_clock(host, clock);
 236                 return;
 237         }
 238 
 239         for (src = 0; src < MAX_BUS_CLK; src++) {
 240                 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
 241                 if (delta < best) {
 242                         best = delta;
 243                         best_src = src;
 244                 }
 245         }
 246 
 247         dev_dbg(&ourhost->pdev->dev,
 248                 "selected source %d, clock %d, delta %d\n",
 249                  best_src, clock, best);
 250 
 251         /* select the new clock source */
 252         if (ourhost->cur_clk != best_src) {
 253                 struct clk *clk = ourhost->clk_bus[best_src];
 254 
 255                 clk_prepare_enable(clk);
 256                 if (ourhost->cur_clk >= 0)
 257                         clk_disable_unprepare(
 258                                         ourhost->clk_bus[ourhost->cur_clk]);
 259 
 260                 ourhost->cur_clk = best_src;
 261                 host->max_clk = ourhost->clk_rates[best_src];
 262         }
 263 
 264         /* turn clock off to card before changing clock source */
 265         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 266 
 267         ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
 268         ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
 269         ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
 270         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
 271 
 272         /* reprogram default hardware configuration */
 273         writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
 274                 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
 275 
 276         ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
 277         ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
 278                   S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
 279                   S3C_SDHCI_CTRL2_ENFBCLKRX |
 280                   S3C_SDHCI_CTRL2_DFCNT_NONE |
 281                   S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
 282         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
 283 
 284         /* reconfigure the controller for new clock rate */
 285         ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
 286         if (clock < 25 * 1000000)
 287                 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
 288         writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
 289 
 290         sdhci_set_clock(host, clock);
 291 }
 292 
 293 /**
 294  * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
 295  * @host: The SDHCI host being queried
 296  *
 297  * To init mmc host properly a minimal clock value is needed. For high system
 298  * bus clock's values the standard formula gives values out of allowed range.
 299  * The clock still can be set to lower values, if clock source other then
 300  * system bus is selected.
 301 */
 302 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
 303 {
 304         struct sdhci_s3c *ourhost = to_s3c(host);
 305         unsigned long rate, min = ULONG_MAX;
 306         int src;
 307 
 308         for (src = 0; src < MAX_BUS_CLK; src++) {
 309                 rate = ourhost->clk_rates[src] / 256;
 310                 if (!rate)
 311                         continue;
 312                 if (rate < min)
 313                         min = rate;
 314         }
 315 
 316         return min;
 317 }
 318 
 319 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
 320 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
 321 {
 322         struct sdhci_s3c *ourhost = to_s3c(host);
 323         unsigned long rate, max = 0;
 324         int src;
 325 
 326         for (src = 0; src < MAX_BUS_CLK; src++) {
 327                 struct clk *clk;
 328 
 329                 clk = ourhost->clk_bus[src];
 330                 if (IS_ERR(clk))
 331                         continue;
 332 
 333                 rate = clk_round_rate(clk, ULONG_MAX);
 334                 if (rate > max)
 335                         max = rate;
 336         }
 337 
 338         return max;
 339 }
 340 
 341 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
 342 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
 343 {
 344         struct sdhci_s3c *ourhost = to_s3c(host);
 345         unsigned long rate, min = ULONG_MAX;
 346         int src;
 347 
 348         for (src = 0; src < MAX_BUS_CLK; src++) {
 349                 struct clk *clk;
 350 
 351                 clk = ourhost->clk_bus[src];
 352                 if (IS_ERR(clk))
 353                         continue;
 354 
 355                 rate = clk_round_rate(clk, 0);
 356                 if (rate < min)
 357                         min = rate;
 358         }
 359 
 360         return min;
 361 }
 362 
 363 /* sdhci_cmu_set_clock - callback on clock change.*/
 364 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
 365 {
 366         struct sdhci_s3c *ourhost = to_s3c(host);
 367         struct device *dev = &ourhost->pdev->dev;
 368         unsigned long timeout;
 369         u16 clk = 0;
 370         int ret;
 371 
 372         host->mmc->actual_clock = 0;
 373 
 374         /* If the clock is going off, set to 0 at clock control register */
 375         if (clock == 0) {
 376                 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 377                 return;
 378         }
 379 
 380         sdhci_s3c_set_clock(host, clock);
 381 
 382         /* Reset SD Clock Enable */
 383         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 384         clk &= ~SDHCI_CLOCK_CARD_EN;
 385         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 386 
 387         ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
 388         if (ret != 0) {
 389                 dev_err(dev, "%s: failed to set clock rate %uHz\n",
 390                         mmc_hostname(host->mmc), clock);
 391                 return;
 392         }
 393 
 394         clk = SDHCI_CLOCK_INT_EN;
 395         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 396 
 397         /* Wait max 20 ms */
 398         timeout = 20;
 399         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 400                 & SDHCI_CLOCK_INT_STABLE)) {
 401                 if (timeout == 0) {
 402                         dev_err(dev, "%s: Internal clock never stabilised.\n",
 403                                 mmc_hostname(host->mmc));
 404                         return;
 405                 }
 406                 timeout--;
 407                 mdelay(1);
 408         }
 409 
 410         clk |= SDHCI_CLOCK_CARD_EN;
 411         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 412 }
 413 
 414 static struct sdhci_ops sdhci_s3c_ops = {
 415         .get_max_clock          = sdhci_s3c_get_max_clk,
 416         .set_clock              = sdhci_s3c_set_clock,
 417         .get_min_clock          = sdhci_s3c_get_min_clock,
 418         .set_bus_width          = sdhci_set_bus_width,
 419         .reset                  = sdhci_reset,
 420         .set_uhs_signaling      = sdhci_set_uhs_signaling,
 421 };
 422 
 423 #ifdef CONFIG_OF
 424 static int sdhci_s3c_parse_dt(struct device *dev,
 425                 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
 426 {
 427         struct device_node *node = dev->of_node;
 428         u32 max_width;
 429 
 430         /* if the bus-width property is not specified, assume width as 1 */
 431         if (of_property_read_u32(node, "bus-width", &max_width))
 432                 max_width = 1;
 433         pdata->max_width = max_width;
 434 
 435         /* get the card detection method */
 436         if (of_get_property(node, "broken-cd", NULL)) {
 437                 pdata->cd_type = S3C_SDHCI_CD_NONE;
 438                 return 0;
 439         }
 440 
 441         if (of_get_property(node, "non-removable", NULL)) {
 442                 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
 443                 return 0;
 444         }
 445 
 446         if (of_get_named_gpio(node, "cd-gpios", 0))
 447                 return 0;
 448 
 449         /* assuming internal card detect that will be configured by pinctrl */
 450         pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
 451         return 0;
 452 }
 453 #else
 454 static int sdhci_s3c_parse_dt(struct device *dev,
 455                 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
 456 {
 457         return -EINVAL;
 458 }
 459 #endif
 460 
 461 static const struct of_device_id sdhci_s3c_dt_match[];
 462 
 463 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
 464                         struct platform_device *pdev)
 465 {
 466 #ifdef CONFIG_OF
 467         if (pdev->dev.of_node) {
 468                 const struct of_device_id *match;
 469                 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
 470                 return (struct sdhci_s3c_drv_data *)match->data;
 471         }
 472 #endif
 473         return (struct sdhci_s3c_drv_data *)
 474                         platform_get_device_id(pdev)->driver_data;
 475 }
 476 
 477 static int sdhci_s3c_probe(struct platform_device *pdev)
 478 {
 479         struct s3c_sdhci_platdata *pdata;
 480         struct sdhci_s3c_drv_data *drv_data;
 481         struct device *dev = &pdev->dev;
 482         struct sdhci_host *host;
 483         struct sdhci_s3c *sc;
 484         struct resource *res;
 485         int ret, irq, ptr, clks;
 486 
 487         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
 488                 dev_err(dev, "no device data specified\n");
 489                 return -ENOENT;
 490         }
 491 
 492         irq = platform_get_irq(pdev, 0);
 493         if (irq < 0)
 494                 return irq;
 495 
 496         host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
 497         if (IS_ERR(host)) {
 498                 dev_err(dev, "sdhci_alloc_host() failed\n");
 499                 return PTR_ERR(host);
 500         }
 501         sc = sdhci_priv(host);
 502 
 503         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 504         if (!pdata) {
 505                 ret = -ENOMEM;
 506                 goto err_pdata_io_clk;
 507         }
 508 
 509         if (pdev->dev.of_node) {
 510                 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
 511                 if (ret)
 512                         goto err_pdata_io_clk;
 513         } else {
 514                 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
 515                 sc->ext_cd_gpio = -1; /* invalid gpio number */
 516         }
 517 
 518         drv_data = sdhci_s3c_get_driver_data(pdev);
 519 
 520         sc->host = host;
 521         sc->pdev = pdev;
 522         sc->pdata = pdata;
 523         sc->cur_clk = -1;
 524 
 525         platform_set_drvdata(pdev, host);
 526 
 527         sc->clk_io = devm_clk_get(dev, "hsmmc");
 528         if (IS_ERR(sc->clk_io)) {
 529                 dev_err(dev, "failed to get io clock\n");
 530                 ret = PTR_ERR(sc->clk_io);
 531                 goto err_pdata_io_clk;
 532         }
 533 
 534         /* enable the local io clock and keep it running for the moment. */
 535         clk_prepare_enable(sc->clk_io);
 536 
 537         for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
 538                 char name[14];
 539 
 540                 snprintf(name, 14, "mmc_busclk.%d", ptr);
 541                 sc->clk_bus[ptr] = devm_clk_get(dev, name);
 542                 if (IS_ERR(sc->clk_bus[ptr]))
 543                         continue;
 544 
 545                 clks++;
 546                 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
 547 
 548                 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
 549                                 ptr, name, sc->clk_rates[ptr]);
 550         }
 551 
 552         if (clks == 0) {
 553                 dev_err(dev, "failed to find any bus clocks\n");
 554                 ret = -ENOENT;
 555                 goto err_no_busclks;
 556         }
 557 
 558         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 559         host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
 560         if (IS_ERR(host->ioaddr)) {
 561                 ret = PTR_ERR(host->ioaddr);
 562                 goto err_req_regs;
 563         }
 564 
 565         /* Ensure we have minimal gpio selected CMD/CLK/Detect */
 566         if (pdata->cfg_gpio)
 567                 pdata->cfg_gpio(pdev, pdata->max_width);
 568 
 569         host->hw_name = "samsung-hsmmc";
 570         host->ops = &sdhci_s3c_ops;
 571         host->quirks = 0;
 572         host->quirks2 = 0;
 573         host->irq = irq;
 574 
 575         /* Setup quirks for the controller */
 576         host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
 577         host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
 578         if (drv_data) {
 579                 host->quirks |= drv_data->sdhci_quirks;
 580                 sc->no_divider = drv_data->no_divider;
 581         }
 582 
 583 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
 584 
 585         /* we currently see overruns on errors, so disable the SDMA
 586          * support as well. */
 587         host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
 588 
 589 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
 590 
 591         /* It seems we do not get an DATA transfer complete on non-busy
 592          * transfers, not sure if this is a problem with this specific
 593          * SDHCI block, or a missing configuration that needs to be set. */
 594         host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
 595 
 596         /* This host supports the Auto CMD12 */
 597         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 598 
 599         /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
 600         host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
 601 
 602         if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
 603             pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
 604                 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 605 
 606         if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
 607                 host->mmc->caps = MMC_CAP_NONREMOVABLE;
 608 
 609         switch (pdata->max_width) {
 610         case 8:
 611                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 612                 /* Fall through */
 613         case 4:
 614                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
 615                 break;
 616         }
 617 
 618         if (pdata->pm_caps)
 619                 host->mmc->pm_caps |= pdata->pm_caps;
 620 
 621         host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
 622                          SDHCI_QUIRK_32BIT_DMA_SIZE);
 623 
 624         /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
 625         host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
 626 
 627         /*
 628          * If controller does not have internal clock divider,
 629          * we can use overriding functions instead of default.
 630          */
 631         if (sc->no_divider) {
 632                 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
 633                 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
 634                 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
 635         }
 636 
 637         /* It supports additional host capabilities if needed */
 638         if (pdata->host_caps)
 639                 host->mmc->caps |= pdata->host_caps;
 640 
 641         if (pdata->host_caps2)
 642                 host->mmc->caps2 |= pdata->host_caps2;
 643 
 644         pm_runtime_enable(&pdev->dev);
 645         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 646         pm_runtime_use_autosuspend(&pdev->dev);
 647         pm_suspend_ignore_children(&pdev->dev, 1);
 648 
 649         ret = mmc_of_parse(host->mmc);
 650         if (ret)
 651                 goto err_req_regs;
 652 
 653         ret = sdhci_add_host(host);
 654         if (ret)
 655                 goto err_req_regs;
 656 
 657 #ifdef CONFIG_PM
 658         if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
 659                 clk_disable_unprepare(sc->clk_io);
 660 #endif
 661         return 0;
 662 
 663  err_req_regs:
 664         pm_runtime_disable(&pdev->dev);
 665 
 666  err_no_busclks:
 667         clk_disable_unprepare(sc->clk_io);
 668 
 669  err_pdata_io_clk:
 670         sdhci_free_host(host);
 671 
 672         return ret;
 673 }
 674 
 675 static int sdhci_s3c_remove(struct platform_device *pdev)
 676 {
 677         struct sdhci_host *host =  platform_get_drvdata(pdev);
 678         struct sdhci_s3c *sc = sdhci_priv(host);
 679 
 680         if (sc->ext_cd_irq)
 681                 free_irq(sc->ext_cd_irq, sc);
 682 
 683 #ifdef CONFIG_PM
 684         if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
 685                 clk_prepare_enable(sc->clk_io);
 686 #endif
 687         sdhci_remove_host(host, 1);
 688 
 689         pm_runtime_dont_use_autosuspend(&pdev->dev);
 690         pm_runtime_disable(&pdev->dev);
 691 
 692         clk_disable_unprepare(sc->clk_io);
 693 
 694         sdhci_free_host(host);
 695 
 696         return 0;
 697 }
 698 
 699 #ifdef CONFIG_PM_SLEEP
 700 static int sdhci_s3c_suspend(struct device *dev)
 701 {
 702         struct sdhci_host *host = dev_get_drvdata(dev);
 703 
 704         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 705                 mmc_retune_needed(host->mmc);
 706 
 707         return sdhci_suspend_host(host);
 708 }
 709 
 710 static int sdhci_s3c_resume(struct device *dev)
 711 {
 712         struct sdhci_host *host = dev_get_drvdata(dev);
 713 
 714         return sdhci_resume_host(host);
 715 }
 716 #endif
 717 
 718 #ifdef CONFIG_PM
 719 static int sdhci_s3c_runtime_suspend(struct device *dev)
 720 {
 721         struct sdhci_host *host = dev_get_drvdata(dev);
 722         struct sdhci_s3c *ourhost = to_s3c(host);
 723         struct clk *busclk = ourhost->clk_io;
 724         int ret;
 725 
 726         ret = sdhci_runtime_suspend_host(host);
 727 
 728         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 729                 mmc_retune_needed(host->mmc);
 730 
 731         if (ourhost->cur_clk >= 0)
 732                 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
 733         clk_disable_unprepare(busclk);
 734         return ret;
 735 }
 736 
 737 static int sdhci_s3c_runtime_resume(struct device *dev)
 738 {
 739         struct sdhci_host *host = dev_get_drvdata(dev);
 740         struct sdhci_s3c *ourhost = to_s3c(host);
 741         struct clk *busclk = ourhost->clk_io;
 742         int ret;
 743 
 744         clk_prepare_enable(busclk);
 745         if (ourhost->cur_clk >= 0)
 746                 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
 747         ret = sdhci_runtime_resume_host(host, 0);
 748         return ret;
 749 }
 750 #endif
 751 
 752 static const struct dev_pm_ops sdhci_s3c_pmops = {
 753         SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
 754         SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
 755                            NULL)
 756 };
 757 
 758 static const struct platform_device_id sdhci_s3c_driver_ids[] = {
 759         {
 760                 .name           = "s3c-sdhci",
 761                 .driver_data    = (kernel_ulong_t)NULL,
 762         },
 763         { }
 764 };
 765 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
 766 
 767 #ifdef CONFIG_OF
 768 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
 769         .no_divider = true,
 770 };
 771 
 772 static const struct of_device_id sdhci_s3c_dt_match[] = {
 773         { .compatible = "samsung,s3c6410-sdhci", },
 774         { .compatible = "samsung,exynos4210-sdhci",
 775                 .data = &exynos4_sdhci_drv_data },
 776         {},
 777 };
 778 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
 779 #endif
 780 
 781 static struct platform_driver sdhci_s3c_driver = {
 782         .probe          = sdhci_s3c_probe,
 783         .remove         = sdhci_s3c_remove,
 784         .id_table       = sdhci_s3c_driver_ids,
 785         .driver         = {
 786                 .name   = "s3c-sdhci",
 787                 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
 788                 .pm     = &sdhci_s3c_pmops,
 789         },
 790 };
 791 
 792 module_platform_driver(sdhci_s3c_driver);
 793 
 794 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
 795 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
 796 MODULE_LICENSE("GPL v2");
 797 MODULE_ALIAS("platform:s3c-sdhci");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/mmc/host/sdhci-s3c.c

DEFINITIONS
