root/drivers/mmc/host/sdhci-of-arasan.c

DEFINITIONS

1. sdhci_arasan_syscon_write
2. sdhci_arasan_set_clock
3. sdhci_arasan_hs400_enhanced_strobe
4. sdhci_arasan_reset
5. sdhci_arasan_voltage_switch
6. sdhci_arasan_set_power
7. sdhci_arasan_cqhci_irq
8. sdhci_arasan_dumpregs
9. sdhci_arasan_cqe_enable
10. sdhci_arasan_suspend
11. sdhci_arasan_resume
12. sdhci_arasan_sdcardclk_recalc_rate
13. sdhci_arasan_update_clockmultiplier
14. sdhci_arasan_update_baseclkfreq
15. sdhci_arasan_register_sdclk
16. sdhci_arasan_unregister_sdclk
17. sdhci_arasan_add_host
18. sdhci_arasan_probe
19. sdhci_arasan_remove

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Arasan Secure Digital Host Controller Interface.
   4  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
   5  * Copyright (c) 2012 Wind River Systems, Inc.
   6  * Copyright (C) 2013 Pengutronix e.K.
   7  * Copyright (C) 2013 Xilinx Inc.
   8  *
   9  * Based on sdhci-of-esdhc.c
  10  *
  11  * Copyright (c) 2007 Freescale Semiconductor, Inc.
  12  * Copyright (c) 2009 MontaVista Software, Inc.
  13  *
  14  * Authors: Xiaobo Xie <X.Xie@freescale.com>
  15  *          Anton Vorontsov <avorontsov@ru.mvista.com>
  16  */
  17 
  18 #include <linux/clk-provider.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/of_device.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/regmap.h>
  24 #include <linux/of.h>
  25 
  26 #include "cqhci.h"
  27 #include "sdhci-pltfm.h"
  28 
  29 #define SDHCI_ARASAN_VENDOR_REGISTER    0x78
  30 #define SDHCI_ARASAN_CQE_BASE_ADDR      0x200
  31 #define VENDOR_ENHANCED_STROBE          BIT(0)
  32 
  33 #define PHY_CLK_TOO_SLOW_HZ             400000
  34 
  35 /*
  36  * On some SoCs the syscon area has a feature where the upper 16-bits of
  37  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
  38  * atomic updates of the register without locking.  This macro is used on SoCs
  39  * that have that feature.
  40  */
  41 #define HIWORD_UPDATE(val, mask, shift) \
  42                 ((val) << (shift) | (mask) << ((shift) + 16))
  43 
  44 /**
  45  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
  46  *
  47  * @reg:        Offset within the syscon of the register containing this field
  48  * @width:      Number of bits for this field
  49  * @shift:      Bit offset within @reg of this field (or -1 if not avail)
  50  */
  51 struct sdhci_arasan_soc_ctl_field {
  52         u32 reg;
  53         u16 width;
  54         s16 shift;
  55 };
  56 
  57 /**
  58  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
  59  *
  60  * It's up to the licensee of the Arsan IP block to make these available
  61  * somewhere if needed.  Presumably these will be scattered somewhere that's
  62  * accessible via the syscon API.
  63  *
  64  * @baseclkfreq:        Where to find corecfg_baseclkfreq
  65  * @clockmultiplier:    Where to find corecfg_clockmultiplier
  66  * @hiword_update:      If true, use HIWORD_UPDATE to access the syscon
  67  */
  68 struct sdhci_arasan_soc_ctl_map {
  69         struct sdhci_arasan_soc_ctl_field       baseclkfreq;
  70         struct sdhci_arasan_soc_ctl_field       clockmultiplier;
  71         bool                                    hiword_update;
  72 };
  73 
  74 /**
  75  * struct sdhci_arasan_data
  76  * @host:               Pointer to the main SDHCI host structure.
  77  * @clk_ahb:            Pointer to the AHB clock
  78  * @phy:                Pointer to the generic phy
  79  * @is_phy_on:          True if the PHY is on; false if not.
  80  * @sdcardclk_hw:       Struct for the clock we might provide to a PHY.
  81  * @sdcardclk:          Pointer to normal 'struct clock' for sdcardclk_hw.
  82  * @soc_ctl_base:       Pointer to regmap for syscon for soc_ctl registers.
  83  * @soc_ctl_map:        Map to get offsets into soc_ctl registers.
  84  */
  85 struct sdhci_arasan_data {
  86         struct sdhci_host *host;
  87         struct clk      *clk_ahb;
  88         struct phy      *phy;
  89         bool            is_phy_on;
  90 
  91         bool            has_cqe;
  92         struct clk_hw   sdcardclk_hw;
  93         struct clk      *sdcardclk;
  94 
  95         struct regmap   *soc_ctl_base;
  96         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
  97         unsigned int    quirks; /* Arasan deviations from spec */
  98 
  99 /* Controller does not have CD wired and will not function normally without */
 100 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
 101 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
 102  * internal clock even when the clock isn't stable */
 103 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
 104 };
 105 
 106 struct sdhci_arasan_of_data {
 107         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
 108         const struct sdhci_pltfm_data *pdata;
 109 };
 110 
 111 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
 112         .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
 113         .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
 114         .hiword_update = true,
 115 };
 116 
 117 static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
 118         .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
 119         .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
 120         .hiword_update = false,
 121 };
 122 
 123 /**
 124  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
 125  *
 126  * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
 127  * Note that if a field is specified as not available (shift < 0) then
 128  * this function will silently return an error code.  It will be noisy
 129  * and print errors for any other (unexpected) errors.
 130  *
 131  * @host:       The sdhci_host
 132  * @fld:        The field to write to
 133  * @val:        The value to write
 134  */
 135 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
 136                                    const struct sdhci_arasan_soc_ctl_field *fld,
 137                                    u32 val)
 138 {
 139         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 140         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 141         struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
 142         u32 reg = fld->reg;
 143         u16 width = fld->width;
 144         s16 shift = fld->shift;
 145         int ret;
 146 
 147         /*
 148          * Silently return errors for shift < 0 so caller doesn't have
 149          * to check for fields which are optional.  For fields that
 150          * are required then caller needs to do something special
 151          * anyway.
 152          */
 153         if (shift < 0)
 154                 return -EINVAL;
 155 
 156         if (sdhci_arasan->soc_ctl_map->hiword_update)
 157                 ret = regmap_write(soc_ctl_base, reg,
 158                                    HIWORD_UPDATE(val, GENMASK(width, 0),
 159                                                  shift));
 160         else
 161                 ret = regmap_update_bits(soc_ctl_base, reg,
 162                                          GENMASK(shift + width, shift),
 163                                          val << shift);
 164 
 165         /* Yell about (unexpected) regmap errors */
 166         if (ret)
 167                 pr_warn("%s: Regmap write fail: %d\n",
 168                          mmc_hostname(host->mmc), ret);
 169 
 170         return ret;
 171 }
 172 
 173 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
 174 {
 175         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 176         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 177         bool ctrl_phy = false;
 178 
 179         if (!IS_ERR(sdhci_arasan->phy)) {
 180                 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
 181                         /*
 182                          * If PHY off, set clock to max speed and power PHY on.
 183                          *
 184                          * Although PHY docs apparently suggest power cycling
 185                          * when changing the clock the PHY doesn't like to be
 186                          * powered on while at low speeds like those used in ID
 187                          * mode.  Even worse is powering the PHY on while the
 188                          * clock is off.
 189                          *
 190                          * To workaround the PHY limitations, the best we can
 191                          * do is to power it on at a faster speed and then slam
 192                          * through low speeds without power cycling.
 193                          */
 194                         sdhci_set_clock(host, host->max_clk);
 195                         phy_power_on(sdhci_arasan->phy);
 196                         sdhci_arasan->is_phy_on = true;
 197 
 198                         /*
 199                          * We'll now fall through to the below case with
 200                          * ctrl_phy = false (so we won't turn off/on).  The
 201                          * sdhci_set_clock() will set the real clock.
 202                          */
 203                 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
 204                         /*
 205                          * At higher clock speeds the PHY is fine being power
 206                          * cycled and docs say you _should_ power cycle when
 207                          * changing clock speeds.
 208                          */
 209                         ctrl_phy = true;
 210                 }
 211         }
 212 
 213         if (ctrl_phy && sdhci_arasan->is_phy_on) {
 214                 phy_power_off(sdhci_arasan->phy);
 215                 sdhci_arasan->is_phy_on = false;
 216         }
 217 
 218         sdhci_set_clock(host, clock);
 219 
 220         if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
 221                 /*
 222                  * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
 223                  * after enabling the clock even though the clock is not
 224                  * stable. Trying to use a clock without waiting here results
 225                  * in EILSEQ while detecting some older/slower cards. The
 226                  * chosen delay is the maximum delay from sdhci_set_clock.
 227                  */
 228                 msleep(20);
 229 
 230         if (ctrl_phy) {
 231                 phy_power_on(sdhci_arasan->phy);
 232                 sdhci_arasan->is_phy_on = true;
 233         }
 234 }
 235 
 236 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
 237                                         struct mmc_ios *ios)
 238 {
 239         u32 vendor;
 240         struct sdhci_host *host = mmc_priv(mmc);
 241 
 242         vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
 243         if (ios->enhanced_strobe)
 244                 vendor |= VENDOR_ENHANCED_STROBE;
 245         else
 246                 vendor &= ~VENDOR_ENHANCED_STROBE;
 247 
 248         sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
 249 }
 250 
 251 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
 252 {
 253         u8 ctrl;
 254         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 255         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 256 
 257         sdhci_reset(host, mask);
 258 
 259         if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
 260                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 261                 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
 262                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 263         }
 264 }
 265 
 266 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
 267                                        struct mmc_ios *ios)
 268 {
 269         switch (ios->signal_voltage) {
 270         case MMC_SIGNAL_VOLTAGE_180:
 271                 /*
 272                  * Plese don't switch to 1V8 as arasan,5.1 doesn't
 273                  * actually refer to this setting to indicate the
 274                  * signal voltage and the state machine will be broken
 275                  * actually if we force to enable 1V8. That's something
 276                  * like broken quirk but we could work around here.
 277                  */
 278                 return 0;
 279         case MMC_SIGNAL_VOLTAGE_330:
 280         case MMC_SIGNAL_VOLTAGE_120:
 281                 /* We don't support 3V3 and 1V2 */
 282                 break;
 283         }
 284 
 285         return -EINVAL;
 286 }
 287 
 288 static void sdhci_arasan_set_power(struct sdhci_host *host, unsigned char mode,
 289                      unsigned short vdd)
 290 {
 291         if (!IS_ERR(host->mmc->supply.vmmc)) {
 292                 struct mmc_host *mmc = host->mmc;
 293 
 294                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 295         }
 296         sdhci_set_power_noreg(host, mode, vdd);
 297 }
 298 
 299 static const struct sdhci_ops sdhci_arasan_ops = {
 300         .set_clock = sdhci_arasan_set_clock,
 301         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 302         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 303         .set_bus_width = sdhci_set_bus_width,
 304         .reset = sdhci_arasan_reset,
 305         .set_uhs_signaling = sdhci_set_uhs_signaling,
 306         .set_power = sdhci_arasan_set_power,
 307 };
 308 
 309 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
 310         .ops = &sdhci_arasan_ops,
 311         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 312         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 313                         SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
 314                         SDHCI_QUIRK2_STOP_WITH_TC,
 315 };
 316 
 317 static struct sdhci_arasan_of_data sdhci_arasan_data = {
 318         .pdata = &sdhci_arasan_pdata,
 319 };
 320 
 321 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
 322 {
 323         int cmd_error = 0;
 324         int data_error = 0;
 325 
 326         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
 327                 return intmask;
 328 
 329         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
 330 
 331         return 0;
 332 }
 333 
 334 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
 335 {
 336         sdhci_dumpregs(mmc_priv(mmc));
 337 }
 338 
 339 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
 340 {
 341         struct sdhci_host *host = mmc_priv(mmc);
 342         u32 reg;
 343 
 344         reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
 345         while (reg & SDHCI_DATA_AVAILABLE) {
 346                 sdhci_readl(host, SDHCI_BUFFER);
 347                 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
 348         }
 349 
 350         sdhci_cqe_enable(mmc);
 351 }
 352 
 353 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
 354         .enable         = sdhci_arasan_cqe_enable,
 355         .disable        = sdhci_cqe_disable,
 356         .dumpregs       = sdhci_arasan_dumpregs,
 357 };
 358 
 359 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
 360         .set_clock = sdhci_arasan_set_clock,
 361         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 362         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 363         .set_bus_width = sdhci_set_bus_width,
 364         .reset = sdhci_arasan_reset,
 365         .set_uhs_signaling = sdhci_set_uhs_signaling,
 366         .set_power = sdhci_arasan_set_power,
 367         .irq = sdhci_arasan_cqhci_irq,
 368 };
 369 
 370 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
 371         .ops = &sdhci_arasan_cqe_ops,
 372         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 373         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 374                         SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
 375 };
 376 
 377 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
 378         .soc_ctl_map = &rk3399_soc_ctl_map,
 379         .pdata = &sdhci_arasan_cqe_pdata,
 380 };
 381 
 382 static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
 383         .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
 384         .pdata = &sdhci_arasan_cqe_pdata,
 385 };
 386 
 387 #ifdef CONFIG_PM_SLEEP
 388 /**
 389  * sdhci_arasan_suspend - Suspend method for the driver
 390  * @dev:        Address of the device structure
 391  * Returns 0 on success and error value on error
 392  *
 393  * Put the device in a low power state.
 394  */
 395 static int sdhci_arasan_suspend(struct device *dev)
 396 {
 397         struct sdhci_host *host = dev_get_drvdata(dev);
 398         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 399         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 400         int ret;
 401 
 402         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 403                 mmc_retune_needed(host->mmc);
 404 
 405         if (sdhci_arasan->has_cqe) {
 406                 ret = cqhci_suspend(host->mmc);
 407                 if (ret)
 408                         return ret;
 409         }
 410 
 411         ret = sdhci_suspend_host(host);
 412         if (ret)
 413                 return ret;
 414 
 415         if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
 416                 ret = phy_power_off(sdhci_arasan->phy);
 417                 if (ret) {
 418                         dev_err(dev, "Cannot power off phy.\n");
 419                         sdhci_resume_host(host);
 420                         return ret;
 421                 }
 422                 sdhci_arasan->is_phy_on = false;
 423         }
 424 
 425         clk_disable(pltfm_host->clk);
 426         clk_disable(sdhci_arasan->clk_ahb);
 427 
 428         return 0;
 429 }
 430 
 431 /**
 432  * sdhci_arasan_resume - Resume method for the driver
 433  * @dev:        Address of the device structure
 434  * Returns 0 on success and error value on error
 435  *
 436  * Resume operation after suspend
 437  */
 438 static int sdhci_arasan_resume(struct device *dev)
 439 {
 440         struct sdhci_host *host = dev_get_drvdata(dev);
 441         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 442         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 443         int ret;
 444 
 445         ret = clk_enable(sdhci_arasan->clk_ahb);
 446         if (ret) {
 447                 dev_err(dev, "Cannot enable AHB clock.\n");
 448                 return ret;
 449         }
 450 
 451         ret = clk_enable(pltfm_host->clk);
 452         if (ret) {
 453                 dev_err(dev, "Cannot enable SD clock.\n");
 454                 return ret;
 455         }
 456 
 457         if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
 458                 ret = phy_power_on(sdhci_arasan->phy);
 459                 if (ret) {
 460                         dev_err(dev, "Cannot power on phy.\n");
 461                         return ret;
 462                 }
 463                 sdhci_arasan->is_phy_on = true;
 464         }
 465 
 466         ret = sdhci_resume_host(host);
 467         if (ret) {
 468                 dev_err(dev, "Cannot resume host.\n");
 469                 return ret;
 470         }
 471 
 472         if (sdhci_arasan->has_cqe)
 473                 return cqhci_resume(host->mmc);
 474 
 475         return 0;
 476 }
 477 #endif /* ! CONFIG_PM_SLEEP */
 478 
 479 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
 480                          sdhci_arasan_resume);
 481 
 482 static const struct of_device_id sdhci_arasan_of_match[] = {
 483         /* SoC-specific compatible strings w/ soc_ctl_map */
 484         {
 485                 .compatible = "rockchip,rk3399-sdhci-5.1",
 486                 .data = &sdhci_arasan_rk3399_data,
 487         },
 488         {
 489                 .compatible = "intel,lgm-sdhci-5.1-emmc",
 490                 .data = &intel_lgm_emmc_data,
 491         },
 492         /* Generic compatible below here */
 493         {
 494                 .compatible = "arasan,sdhci-8.9a",
 495                 .data = &sdhci_arasan_data,
 496         },
 497         {
 498                 .compatible = "arasan,sdhci-5.1",
 499                 .data = &sdhci_arasan_data,
 500         },
 501         {
 502                 .compatible = "arasan,sdhci-4.9a",
 503                 .data = &sdhci_arasan_data,
 504         },
 505         { /* sentinel */ }
 506 };
 507 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
 508 
 509 /**
 510  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
 511  *
 512  * Return the current actual rate of the SD card clock.  This can be used
 513  * to communicate with out PHY.
 514  *
 515  * @hw:                 Pointer to the hardware clock structure.
 516  * @parent_rate         The parent rate (should be rate of clk_xin).
 517  * Returns the card clock rate.
 518  */
 519 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
 520                                                       unsigned long parent_rate)
 521 
 522 {
 523         struct sdhci_arasan_data *sdhci_arasan =
 524                 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
 525         struct sdhci_host *host = sdhci_arasan->host;
 526 
 527         return host->mmc->actual_clock;
 528 }
 529 
 530 static const struct clk_ops arasan_sdcardclk_ops = {
 531         .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
 532 };
 533 
 534 /**
 535  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
 536  *
 537  * The corecfg_clockmultiplier is supposed to contain clock multiplier
 538  * value of programmable clock generator.
 539  *
 540  * NOTES:
 541  * - Many existing devices don't seem to do this and work fine.  To keep
 542  *   compatibility for old hardware where the device tree doesn't provide a
 543  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
 544  *   for this platform.
 545  * - The value of corecfg_clockmultiplier should sync with that of corresponding
 546  *   value reading from sdhci_capability_register. So this function is called
 547  *   once at probe time and never called again.
 548  *
 549  * @host:               The sdhci_host
 550  */
 551 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
 552                                                 u32 value)
 553 {
 554         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 555         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 556         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
 557                 sdhci_arasan->soc_ctl_map;
 558 
 559         /* Having a map is optional */
 560         if (!soc_ctl_map)
 561                 return;
 562 
 563         /* If we have a map, we expect to have a syscon */
 564         if (!sdhci_arasan->soc_ctl_base) {
 565                 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
 566                         mmc_hostname(host->mmc));
 567                 return;
 568         }
 569 
 570         sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
 571 }
 572 
 573 /**
 574  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
 575  *
 576  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
 577  * function can be used to make that happen.
 578  *
 579  * NOTES:
 580  * - Many existing devices don't seem to do this and work fine.  To keep
 581  *   compatibility for old hardware where the device tree doesn't provide a
 582  *   register map, this function is a noop if a soc_ctl_map hasn't been provided
 583  *   for this platform.
 584  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
 585  *   to achieve lower clock rates.  That means that this function is called once
 586  *   at probe time and never called again.
 587  *
 588  * @host:               The sdhci_host
 589  */
 590 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
 591 {
 592         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 593         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 594         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
 595                 sdhci_arasan->soc_ctl_map;
 596         u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
 597 
 598         /* Having a map is optional */
 599         if (!soc_ctl_map)
 600                 return;
 601 
 602         /* If we have a map, we expect to have a syscon */
 603         if (!sdhci_arasan->soc_ctl_base) {
 604                 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
 605                         mmc_hostname(host->mmc));
 606                 return;
 607         }
 608 
 609         sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
 610 }
 611 
 612 /**
 613  * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
 614  *
 615  * Some PHY devices need to know what the actual card clock is.  In order for
 616  * them to find out, we'll provide a clock through the common clock framework
 617  * for them to query.
 618  *
 619  * Note: without seriously re-architecting SDHCI's clock code and testing on
 620  * all platforms, there's no way to create a totally beautiful clock here
 621  * with all clock ops implemented.  Instead, we'll just create a clock that can
 622  * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
 623  * framework that we're doing things behind its back.  This should be sufficient
 624  * to create nice clean device tree bindings and later (if needed) we can try
 625  * re-architecting SDHCI if we see some benefit to it.
 626  *
 627  * @sdhci_arasan:       Our private data structure.
 628  * @clk_xin:            Pointer to the functional clock
 629  * @dev:                Pointer to our struct device.
 630  * Returns 0 on success and error value on error
 631  */
 632 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
 633                                        struct clk *clk_xin,
 634                                        struct device *dev)
 635 {
 636         struct device_node *np = dev->of_node;
 637         struct clk_init_data sdcardclk_init;
 638         const char *parent_clk_name;
 639         int ret;
 640 
 641         /* Providing a clock to the PHY is optional; no error if missing */
 642         if (!of_find_property(np, "#clock-cells", NULL))
 643                 return 0;
 644 
 645         ret = of_property_read_string_index(np, "clock-output-names", 0,
 646                                             &sdcardclk_init.name);
 647         if (ret) {
 648                 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
 649                 return ret;
 650         }
 651 
 652         parent_clk_name = __clk_get_name(clk_xin);
 653         sdcardclk_init.parent_names = &parent_clk_name;
 654         sdcardclk_init.num_parents = 1;
 655         sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
 656         sdcardclk_init.ops = &arasan_sdcardclk_ops;
 657 
 658         sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
 659         sdhci_arasan->sdcardclk =
 660                 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
 661         sdhci_arasan->sdcardclk_hw.init = NULL;
 662 
 663         ret = of_clk_add_provider(np, of_clk_src_simple_get,
 664                                   sdhci_arasan->sdcardclk);
 665         if (ret)
 666                 dev_err(dev, "Failed to add clock provider\n");
 667 
 668         return ret;
 669 }
 670 
 671 /**
 672  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
 673  *
 674  * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
 675  * returned success.
 676  *
 677  * @dev:                Pointer to our struct device.
 678  */
 679 static void sdhci_arasan_unregister_sdclk(struct device *dev)
 680 {
 681         struct device_node *np = dev->of_node;
 682 
 683         if (!of_find_property(np, "#clock-cells", NULL))
 684                 return;
 685 
 686         of_clk_del_provider(dev->of_node);
 687 }
 688 
 689 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
 690 {
 691         struct sdhci_host *host = sdhci_arasan->host;
 692         struct cqhci_host *cq_host;
 693         bool dma64;
 694         int ret;
 695 
 696         if (!sdhci_arasan->has_cqe)
 697                 return sdhci_add_host(host);
 698 
 699         ret = sdhci_setup_host(host);
 700         if (ret)
 701                 return ret;
 702 
 703         cq_host = devm_kzalloc(host->mmc->parent,
 704                                sizeof(*cq_host), GFP_KERNEL);
 705         if (!cq_host) {
 706                 ret = -ENOMEM;
 707                 goto cleanup;
 708         }
 709 
 710         cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
 711         cq_host->ops = &sdhci_arasan_cqhci_ops;
 712 
 713         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
 714         if (dma64)
 715                 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
 716 
 717         ret = cqhci_init(cq_host, host->mmc, dma64);
 718         if (ret)
 719                 goto cleanup;
 720 
 721         ret = __sdhci_add_host(host);
 722         if (ret)
 723                 goto cleanup;
 724 
 725         return 0;
 726 
 727 cleanup:
 728         sdhci_cleanup_host(host);
 729         return ret;
 730 }
 731 
 732 static int sdhci_arasan_probe(struct platform_device *pdev)
 733 {
 734         int ret;
 735         const struct of_device_id *match;
 736         struct device_node *node;
 737         struct clk *clk_xin;
 738         struct sdhci_host *host;
 739         struct sdhci_pltfm_host *pltfm_host;
 740         struct sdhci_arasan_data *sdhci_arasan;
 741         struct device_node *np = pdev->dev.of_node;
 742         const struct sdhci_arasan_of_data *data;
 743 
 744         match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
 745         data = match->data;
 746         host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
 747 
 748         if (IS_ERR(host))
 749                 return PTR_ERR(host);
 750 
 751         pltfm_host = sdhci_priv(host);
 752         sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 753         sdhci_arasan->host = host;
 754 
 755         sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
 756 
 757         node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
 758         if (node) {
 759                 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
 760                 of_node_put(node);
 761 
 762                 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
 763                         ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
 764                         if (ret != -EPROBE_DEFER)
 765                                 dev_err(&pdev->dev, "Can't get syscon: %d\n",
 766                                         ret);
 767                         goto err_pltfm_free;
 768                 }
 769         }
 770 
 771         sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
 772         if (IS_ERR(sdhci_arasan->clk_ahb)) {
 773                 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
 774                 ret = PTR_ERR(sdhci_arasan->clk_ahb);
 775                 goto err_pltfm_free;
 776         }
 777 
 778         clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
 779         if (IS_ERR(clk_xin)) {
 780                 dev_err(&pdev->dev, "clk_xin clock not found.\n");
 781                 ret = PTR_ERR(clk_xin);
 782                 goto err_pltfm_free;
 783         }
 784 
 785         ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
 786         if (ret) {
 787                 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
 788                 goto err_pltfm_free;
 789         }
 790 
 791         ret = clk_prepare_enable(clk_xin);
 792         if (ret) {
 793                 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
 794                 goto clk_dis_ahb;
 795         }
 796 
 797         sdhci_get_of_property(pdev);
 798 
 799         if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
 800                 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
 801 
 802         if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
 803                 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
 804 
 805         pltfm_host->clk = clk_xin;
 806 
 807         if (of_device_is_compatible(pdev->dev.of_node,
 808                                     "rockchip,rk3399-sdhci-5.1"))
 809                 sdhci_arasan_update_clockmultiplier(host, 0x0);
 810 
 811         sdhci_arasan_update_baseclkfreq(host);
 812 
 813         ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
 814         if (ret)
 815                 goto clk_disable_all;
 816 
 817         ret = mmc_of_parse(host->mmc);
 818         if (ret) {
 819                 if (ret != -EPROBE_DEFER)
 820                         dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
 821                 goto unreg_clk;
 822         }
 823 
 824         sdhci_arasan->phy = ERR_PTR(-ENODEV);
 825         if (of_device_is_compatible(pdev->dev.of_node,
 826                                     "arasan,sdhci-5.1")) {
 827                 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
 828                                                  "phy_arasan");
 829                 if (IS_ERR(sdhci_arasan->phy)) {
 830                         ret = PTR_ERR(sdhci_arasan->phy);
 831                         dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
 832                         goto unreg_clk;
 833                 }
 834 
 835                 ret = phy_init(sdhci_arasan->phy);
 836                 if (ret < 0) {
 837                         dev_err(&pdev->dev, "phy_init err.\n");
 838                         goto unreg_clk;
 839                 }
 840 
 841                 host->mmc_host_ops.hs400_enhanced_strobe =
 842                                         sdhci_arasan_hs400_enhanced_strobe;
 843                 host->mmc_host_ops.start_signal_voltage_switch =
 844                                         sdhci_arasan_voltage_switch;
 845                 sdhci_arasan->has_cqe = true;
 846                 host->mmc->caps2 |= MMC_CAP2_CQE;
 847 
 848                 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
 849                         host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
 850         }
 851 
 852         ret = sdhci_arasan_add_host(sdhci_arasan);
 853         if (ret)
 854                 goto err_add_host;
 855 
 856         return 0;
 857 
 858 err_add_host:
 859         if (!IS_ERR(sdhci_arasan->phy))
 860                 phy_exit(sdhci_arasan->phy);
 861 unreg_clk:
 862         sdhci_arasan_unregister_sdclk(&pdev->dev);
 863 clk_disable_all:
 864         clk_disable_unprepare(clk_xin);
 865 clk_dis_ahb:
 866         clk_disable_unprepare(sdhci_arasan->clk_ahb);
 867 err_pltfm_free:
 868         sdhci_pltfm_free(pdev);
 869         return ret;
 870 }
 871 
 872 static int sdhci_arasan_remove(struct platform_device *pdev)
 873 {
 874         int ret;
 875         struct sdhci_host *host = platform_get_drvdata(pdev);
 876         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 877         struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
 878         struct clk *clk_ahb = sdhci_arasan->clk_ahb;
 879 
 880         if (!IS_ERR(sdhci_arasan->phy)) {
 881                 if (sdhci_arasan->is_phy_on)
 882                         phy_power_off(sdhci_arasan->phy);
 883                 phy_exit(sdhci_arasan->phy);
 884         }
 885 
 886         sdhci_arasan_unregister_sdclk(&pdev->dev);
 887 
 888         ret = sdhci_pltfm_unregister(pdev);
 889 
 890         clk_disable_unprepare(clk_ahb);
 891 
 892         return ret;
 893 }
 894 
 895 static struct platform_driver sdhci_arasan_driver = {
 896         .driver = {
 897                 .name = "sdhci-arasan",
 898                 .of_match_table = sdhci_arasan_of_match,
 899                 .pm = &sdhci_arasan_dev_pm_ops,
 900         },
 901         .probe = sdhci_arasan_probe,
 902         .remove = sdhci_arasan_remove,
 903 };
 904 
 905 module_platform_driver(sdhci_arasan_driver);
 906 
 907 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
 908 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
 909 MODULE_LICENSE("GPL");