This source file includes following definitions.
- mmci_card_busy
- mmci_reg_delay
- mmci_write_clkreg
- mmci_write_pwrreg
- mmci_write_datactrlreg
- mmci_set_clkreg
- mmci_dma_release
- mmci_dma_setup
- mmci_validate_data
- mmci_prep_data
- mmci_unprep_data
- mmci_get_next_data
- mmci_dma_start
- mmci_dma_finalize
- mmci_dma_error
- mmci_request_end
- mmci_set_mask1
- mmci_stop_data
- mmci_init_sg
- mmci_get_dctrl_cfg
- ux500v2_get_dctrl_cfg
- mmci_dmae_setup
- mmci_dmae_release
- mmci_dma_unmap
- mmci_dmae_error
- mmci_dmae_finalize
- _mmci_dmae_prep_data
- mmci_dmae_prep_data
- mmci_dmae_start
- mmci_dmae_get_next_data
- mmci_dmae_unprep_data
- mmci_variant_init
- ux500v2_variant_init
- mmci_pre_request
- mmci_post_request
- mmci_start_data
- mmci_start_command
- mmci_stop_command
- mmci_data_irq
- mmci_cmd_irq
- mmci_get_rx_fifocnt
- mmci_qcom_get_rx_fifocnt
- mmci_pio_read
- mmci_pio_write
- mmci_pio_irq
- mmci_irq
- mmci_request
- mmci_set_ios
- mmci_get_cd
- mmci_sig_volt_switch
- mmci_of_parse
- mmci_probe
- mmci_remove
- mmci_save
- mmci_restore
- mmci_runtime_suspend
- mmci_runtime_resume
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8 #include <linux/module.h>
9 #include <linux/moduleparam.h>
10 #include <linux/init.h>
11 #include <linux/ioport.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/highmem.h>
20 #include <linux/log2.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/pm.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/card.h>
25 #include <linux/mmc/slot-gpio.h>
26 #include <linux/amba/bus.h>
27 #include <linux/clk.h>
28 #include <linux/scatterlist.h>
29 #include <linux/of.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/amba/mmci.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/types.h>
36 #include <linux/pinctrl/consumer.h>
37 #include <linux/reset.h>
38
39 #include <asm/div64.h>
40 #include <asm/io.h>
41
42 #include "mmci.h"
43
44 #define DRIVER_NAME "mmci-pl18x"
45
46 static void mmci_variant_init(struct mmci_host *host);
47 static void ux500v2_variant_init(struct mmci_host *host);
48
49 static unsigned int fmax = 515633;
50
51 static struct variant_data variant_arm = {
52 .fifosize = 16 * 4,
53 .fifohalfsize = 8 * 4,
54 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
55 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
56 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
57 .cmdreg_srsp = MCI_CPSM_RESPONSE,
58 .datalength_bits = 16,
59 .datactrl_blocksz = 11,
60 .pwrreg_powerup = MCI_PWR_UP,
61 .f_max = 100000000,
62 .reversed_irq_handling = true,
63 .mmcimask1 = true,
64 .irq_pio_mask = MCI_IRQ_PIO_MASK,
65 .start_err = MCI_STARTBITERR,
66 .opendrain = MCI_ROD,
67 .init = mmci_variant_init,
68 };
69
70 static struct variant_data variant_arm_extended_fifo = {
71 .fifosize = 128 * 4,
72 .fifohalfsize = 64 * 4,
73 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
74 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
75 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
76 .cmdreg_srsp = MCI_CPSM_RESPONSE,
77 .datalength_bits = 16,
78 .datactrl_blocksz = 11,
79 .pwrreg_powerup = MCI_PWR_UP,
80 .f_max = 100000000,
81 .mmcimask1 = true,
82 .irq_pio_mask = MCI_IRQ_PIO_MASK,
83 .start_err = MCI_STARTBITERR,
84 .opendrain = MCI_ROD,
85 .init = mmci_variant_init,
86 };
87
88 static struct variant_data variant_arm_extended_fifo_hwfc = {
89 .fifosize = 128 * 4,
90 .fifohalfsize = 64 * 4,
91 .clkreg_enable = MCI_ARM_HWFCEN,
92 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
93 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
94 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
95 .cmdreg_srsp = MCI_CPSM_RESPONSE,
96 .datalength_bits = 16,
97 .datactrl_blocksz = 11,
98 .pwrreg_powerup = MCI_PWR_UP,
99 .f_max = 100000000,
100 .mmcimask1 = true,
101 .irq_pio_mask = MCI_IRQ_PIO_MASK,
102 .start_err = MCI_STARTBITERR,
103 .opendrain = MCI_ROD,
104 .init = mmci_variant_init,
105 };
106
107 static struct variant_data variant_u300 = {
108 .fifosize = 16 * 4,
109 .fifohalfsize = 8 * 4,
110 .clkreg_enable = MCI_ST_U300_HWFCEN,
111 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
112 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
113 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
114 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
115 .cmdreg_srsp = MCI_CPSM_RESPONSE,
116 .datalength_bits = 16,
117 .datactrl_blocksz = 11,
118 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
119 .st_sdio = true,
120 .pwrreg_powerup = MCI_PWR_ON,
121 .f_max = 100000000,
122 .signal_direction = true,
123 .pwrreg_clkgate = true,
124 .pwrreg_nopower = true,
125 .mmcimask1 = true,
126 .irq_pio_mask = MCI_IRQ_PIO_MASK,
127 .start_err = MCI_STARTBITERR,
128 .opendrain = MCI_OD,
129 .init = mmci_variant_init,
130 };
131
132 static struct variant_data variant_nomadik = {
133 .fifosize = 16 * 4,
134 .fifohalfsize = 8 * 4,
135 .clkreg = MCI_CLK_ENABLE,
136 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
137 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
138 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
139 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
140 .cmdreg_srsp = MCI_CPSM_RESPONSE,
141 .datalength_bits = 24,
142 .datactrl_blocksz = 11,
143 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
144 .st_sdio = true,
145 .st_clkdiv = true,
146 .pwrreg_powerup = MCI_PWR_ON,
147 .f_max = 100000000,
148 .signal_direction = true,
149 .pwrreg_clkgate = true,
150 .pwrreg_nopower = true,
151 .mmcimask1 = true,
152 .irq_pio_mask = MCI_IRQ_PIO_MASK,
153 .start_err = MCI_STARTBITERR,
154 .opendrain = MCI_OD,
155 .init = mmci_variant_init,
156 };
157
158 static struct variant_data variant_ux500 = {
159 .fifosize = 30 * 4,
160 .fifohalfsize = 8 * 4,
161 .clkreg = MCI_CLK_ENABLE,
162 .clkreg_enable = MCI_ST_UX500_HWFCEN,
163 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
164 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
165 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
166 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
167 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
168 .cmdreg_srsp = MCI_CPSM_RESPONSE,
169 .datalength_bits = 24,
170 .datactrl_blocksz = 11,
171 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
172 .st_sdio = true,
173 .st_clkdiv = true,
174 .pwrreg_powerup = MCI_PWR_ON,
175 .f_max = 100000000,
176 .signal_direction = true,
177 .pwrreg_clkgate = true,
178 .busy_detect = true,
179 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
180 .busy_detect_flag = MCI_ST_CARDBUSY,
181 .busy_detect_mask = MCI_ST_BUSYENDMASK,
182 .pwrreg_nopower = true,
183 .mmcimask1 = true,
184 .irq_pio_mask = MCI_IRQ_PIO_MASK,
185 .start_err = MCI_STARTBITERR,
186 .opendrain = MCI_OD,
187 .init = mmci_variant_init,
188 };
189
190 static struct variant_data variant_ux500v2 = {
191 .fifosize = 30 * 4,
192 .fifohalfsize = 8 * 4,
193 .clkreg = MCI_CLK_ENABLE,
194 .clkreg_enable = MCI_ST_UX500_HWFCEN,
195 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
196 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
197 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
198 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
199 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
200 .cmdreg_srsp = MCI_CPSM_RESPONSE,
201 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
202 .datalength_bits = 24,
203 .datactrl_blocksz = 11,
204 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
205 .st_sdio = true,
206 .st_clkdiv = true,
207 .pwrreg_powerup = MCI_PWR_ON,
208 .f_max = 100000000,
209 .signal_direction = true,
210 .pwrreg_clkgate = true,
211 .busy_detect = true,
212 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
213 .busy_detect_flag = MCI_ST_CARDBUSY,
214 .busy_detect_mask = MCI_ST_BUSYENDMASK,
215 .pwrreg_nopower = true,
216 .mmcimask1 = true,
217 .irq_pio_mask = MCI_IRQ_PIO_MASK,
218 .start_err = MCI_STARTBITERR,
219 .opendrain = MCI_OD,
220 .init = ux500v2_variant_init,
221 };
222
223 static struct variant_data variant_stm32 = {
224 .fifosize = 32 * 4,
225 .fifohalfsize = 8 * 4,
226 .clkreg = MCI_CLK_ENABLE,
227 .clkreg_enable = MCI_ST_UX500_HWFCEN,
228 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
229 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
230 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
231 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
232 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
233 .cmdreg_srsp = MCI_CPSM_RESPONSE,
234 .irq_pio_mask = MCI_IRQ_PIO_MASK,
235 .datalength_bits = 24,
236 .datactrl_blocksz = 11,
237 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
238 .st_sdio = true,
239 .st_clkdiv = true,
240 .pwrreg_powerup = MCI_PWR_ON,
241 .f_max = 48000000,
242 .pwrreg_clkgate = true,
243 .pwrreg_nopower = true,
244 .init = mmci_variant_init,
245 };
246
247 static struct variant_data variant_stm32_sdmmc = {
248 .fifosize = 16 * 4,
249 .fifohalfsize = 8 * 4,
250 .f_max = 208000000,
251 .stm32_clkdiv = true,
252 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
253 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
254 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
255 .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
256 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP,
257 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
258 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
259 .datactrl_first = true,
260 .datacnt_useless = true,
261 .datalength_bits = 25,
262 .datactrl_blocksz = 14,
263 .stm32_idmabsize_mask = GENMASK(12, 5),
264 .init = sdmmc_variant_init,
265 };
266
267 static struct variant_data variant_qcom = {
268 .fifosize = 16 * 4,
269 .fifohalfsize = 8 * 4,
270 .clkreg = MCI_CLK_ENABLE,
271 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
272 MCI_QCOM_CLK_SELECT_IN_FBCLK,
273 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
274 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
275 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
276 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
277 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
278 .cmdreg_srsp = MCI_CPSM_RESPONSE,
279 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
280 .datalength_bits = 24,
281 .datactrl_blocksz = 11,
282 .pwrreg_powerup = MCI_PWR_UP,
283 .f_max = 208000000,
284 .explicit_mclk_control = true,
285 .qcom_fifo = true,
286 .qcom_dml = true,
287 .mmcimask1 = true,
288 .irq_pio_mask = MCI_IRQ_PIO_MASK,
289 .start_err = MCI_STARTBITERR,
290 .opendrain = MCI_ROD,
291 .init = qcom_variant_init,
292 };
293
294
295 static int mmci_card_busy(struct mmc_host *mmc)
296 {
297 struct mmci_host *host = mmc_priv(mmc);
298 unsigned long flags;
299 int busy = 0;
300
301 spin_lock_irqsave(&host->lock, flags);
302 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
303 busy = 1;
304 spin_unlock_irqrestore(&host->lock, flags);
305
306 return busy;
307 }
308
309 static void mmci_reg_delay(struct mmci_host *host)
310 {
311
312
313
314
315
316
317
318 if (host->cclk < 25000000)
319 udelay(30);
320 else
321 ndelay(120);
322 }
323
324
325
326
327 void mmci_write_clkreg(struct mmci_host *host, u32 clk)
328 {
329 if (host->clk_reg != clk) {
330 host->clk_reg = clk;
331 writel(clk, host->base + MMCICLOCK);
332 }
333 }
334
335
336
337
338 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
339 {
340 if (host->pwr_reg != pwr) {
341 host->pwr_reg = pwr;
342 writel(pwr, host->base + MMCIPOWER);
343 }
344 }
345
346
347
348
349 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
350 {
351
352 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
353
354 if (host->datactrl_reg != datactrl) {
355 host->datactrl_reg = datactrl;
356 writel(datactrl, host->base + MMCIDATACTRL);
357 }
358 }
359
360
361
362
363 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
364 {
365 struct variant_data *variant = host->variant;
366 u32 clk = variant->clkreg;
367
368
369 host->cclk = 0;
370
371 if (desired) {
372 if (variant->explicit_mclk_control) {
373 host->cclk = host->mclk;
374 } else if (desired >= host->mclk) {
375 clk = MCI_CLK_BYPASS;
376 if (variant->st_clkdiv)
377 clk |= MCI_ST_UX500_NEG_EDGE;
378 host->cclk = host->mclk;
379 } else if (variant->st_clkdiv) {
380
381
382
383
384
385
386 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
387 if (clk >= 256)
388 clk = 255;
389 host->cclk = host->mclk / (clk + 2);
390 } else {
391
392
393
394
395 clk = host->mclk / (2 * desired) - 1;
396 if (clk >= 256)
397 clk = 255;
398 host->cclk = host->mclk / (2 * (clk + 1));
399 }
400
401 clk |= variant->clkreg_enable;
402 clk |= MCI_CLK_ENABLE;
403
404
405 }
406
407
408 host->mmc->actual_clock = host->cclk;
409
410 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
411 clk |= MCI_4BIT_BUS;
412 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
413 clk |= variant->clkreg_8bit_bus_enable;
414
415 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
416 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
417 clk |= variant->clkreg_neg_edge_enable;
418
419 mmci_write_clkreg(host, clk);
420 }
421
422 void mmci_dma_release(struct mmci_host *host)
423 {
424 if (host->ops && host->ops->dma_release)
425 host->ops->dma_release(host);
426
427 host->use_dma = false;
428 }
429
430 void mmci_dma_setup(struct mmci_host *host)
431 {
432 if (!host->ops || !host->ops->dma_setup)
433 return;
434
435 if (host->ops->dma_setup(host))
436 return;
437
438
439 host->next_cookie = 1;
440
441 host->use_dma = true;
442 }
443
444
445
446
447 static int mmci_validate_data(struct mmci_host *host,
448 struct mmc_data *data)
449 {
450 if (!data)
451 return 0;
452
453 if (!is_power_of_2(data->blksz)) {
454 dev_err(mmc_dev(host->mmc),
455 "unsupported block size (%d bytes)\n", data->blksz);
456 return -EINVAL;
457 }
458
459 if (host->ops && host->ops->validate_data)
460 return host->ops->validate_data(host, data);
461
462 return 0;
463 }
464
465 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
466 {
467 int err;
468
469 if (!host->ops || !host->ops->prep_data)
470 return 0;
471
472 err = host->ops->prep_data(host, data, next);
473
474 if (next && !err)
475 data->host_cookie = ++host->next_cookie < 0 ?
476 1 : host->next_cookie;
477
478 return err;
479 }
480
481 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
482 int err)
483 {
484 if (host->ops && host->ops->unprep_data)
485 host->ops->unprep_data(host, data, err);
486
487 data->host_cookie = 0;
488 }
489
490 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
491 {
492 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
493
494 if (host->ops && host->ops->get_next_data)
495 host->ops->get_next_data(host, data);
496 }
497
498 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
499 {
500 struct mmc_data *data = host->data;
501 int ret;
502
503 if (!host->use_dma)
504 return -EINVAL;
505
506 ret = mmci_prep_data(host, data, false);
507 if (ret)
508 return ret;
509
510 if (!host->ops || !host->ops->dma_start)
511 return -EINVAL;
512
513
514 dev_vdbg(mmc_dev(host->mmc),
515 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
516 data->sg_len, data->blksz, data->blocks, data->flags);
517
518 host->ops->dma_start(host, &datactrl);
519
520
521 mmci_write_datactrlreg(host, datactrl);
522
523
524
525
526
527
528 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
529 host->base + MMCIMASK0);
530 return 0;
531 }
532
533 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
534 {
535 if (!host->use_dma)
536 return;
537
538 if (host->ops && host->ops->dma_finalize)
539 host->ops->dma_finalize(host, data);
540 }
541
542 void mmci_dma_error(struct mmci_host *host)
543 {
544 if (!host->use_dma)
545 return;
546
547 if (host->ops && host->ops->dma_error)
548 host->ops->dma_error(host);
549 }
550
551 static void
552 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
553 {
554 writel(0, host->base + MMCICOMMAND);
555
556 BUG_ON(host->data);
557
558 host->mrq = NULL;
559 host->cmd = NULL;
560
561 mmc_request_done(host->mmc, mrq);
562 }
563
564 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
565 {
566 void __iomem *base = host->base;
567 struct variant_data *variant = host->variant;
568
569 if (host->singleirq) {
570 unsigned int mask0 = readl(base + MMCIMASK0);
571
572 mask0 &= ~variant->irq_pio_mask;
573 mask0 |= mask;
574
575 writel(mask0, base + MMCIMASK0);
576 }
577
578 if (variant->mmcimask1)
579 writel(mask, base + MMCIMASK1);
580
581 host->mask1_reg = mask;
582 }
583
584 static void mmci_stop_data(struct mmci_host *host)
585 {
586 mmci_write_datactrlreg(host, 0);
587 mmci_set_mask1(host, 0);
588 host->data = NULL;
589 }
590
591 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
592 {
593 unsigned int flags = SG_MITER_ATOMIC;
594
595 if (data->flags & MMC_DATA_READ)
596 flags |= SG_MITER_TO_SG;
597 else
598 flags |= SG_MITER_FROM_SG;
599
600 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
601 }
602
603 static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
604 {
605 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
606 }
607
608 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
609 {
610 return MCI_DPSM_ENABLE | (host->data->blksz << 16);
611 }
612
613
614
615
616
617
618 #ifdef CONFIG_DMA_ENGINE
619 struct mmci_dmae_next {
620 struct dma_async_tx_descriptor *desc;
621 struct dma_chan *chan;
622 };
623
624 struct mmci_dmae_priv {
625 struct dma_chan *cur;
626 struct dma_chan *rx_channel;
627 struct dma_chan *tx_channel;
628 struct dma_async_tx_descriptor *desc_current;
629 struct mmci_dmae_next next_data;
630 };
631
632 int mmci_dmae_setup(struct mmci_host *host)
633 {
634 const char *rxname, *txname;
635 struct mmci_dmae_priv *dmae;
636
637 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
638 if (!dmae)
639 return -ENOMEM;
640
641 host->dma_priv = dmae;
642
643 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
644 "rx");
645 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
646 "tx");
647
648
649
650
651
652
653 if (dmae->rx_channel && !dmae->tx_channel)
654 dmae->tx_channel = dmae->rx_channel;
655
656 if (dmae->rx_channel)
657 rxname = dma_chan_name(dmae->rx_channel);
658 else
659 rxname = "none";
660
661 if (dmae->tx_channel)
662 txname = dma_chan_name(dmae->tx_channel);
663 else
664 txname = "none";
665
666 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
667 rxname, txname);
668
669
670
671
672
673 if (dmae->tx_channel) {
674 struct device *dev = dmae->tx_channel->device->dev;
675 unsigned int max_seg_size = dma_get_max_seg_size(dev);
676
677 if (max_seg_size < host->mmc->max_seg_size)
678 host->mmc->max_seg_size = max_seg_size;
679 }
680 if (dmae->rx_channel) {
681 struct device *dev = dmae->rx_channel->device->dev;
682 unsigned int max_seg_size = dma_get_max_seg_size(dev);
683
684 if (max_seg_size < host->mmc->max_seg_size)
685 host->mmc->max_seg_size = max_seg_size;
686 }
687
688 if (!dmae->tx_channel || !dmae->rx_channel) {
689 mmci_dmae_release(host);
690 return -EINVAL;
691 }
692
693 return 0;
694 }
695
696
697
698
699
700 void mmci_dmae_release(struct mmci_host *host)
701 {
702 struct mmci_dmae_priv *dmae = host->dma_priv;
703
704 if (dmae->rx_channel)
705 dma_release_channel(dmae->rx_channel);
706 if (dmae->tx_channel)
707 dma_release_channel(dmae->tx_channel);
708 dmae->rx_channel = dmae->tx_channel = NULL;
709 }
710
711 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
712 {
713 struct mmci_dmae_priv *dmae = host->dma_priv;
714 struct dma_chan *chan;
715
716 if (data->flags & MMC_DATA_READ)
717 chan = dmae->rx_channel;
718 else
719 chan = dmae->tx_channel;
720
721 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
722 mmc_get_dma_dir(data));
723 }
724
725 void mmci_dmae_error(struct mmci_host *host)
726 {
727 struct mmci_dmae_priv *dmae = host->dma_priv;
728
729 if (!dma_inprogress(host))
730 return;
731
732 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
733 dmaengine_terminate_all(dmae->cur);
734 host->dma_in_progress = false;
735 dmae->cur = NULL;
736 dmae->desc_current = NULL;
737 host->data->host_cookie = 0;
738
739 mmci_dma_unmap(host, host->data);
740 }
741
742 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
743 {
744 struct mmci_dmae_priv *dmae = host->dma_priv;
745 u32 status;
746 int i;
747
748 if (!dma_inprogress(host))
749 return;
750
751
752 for (i = 0; ; i++) {
753 status = readl(host->base + MMCISTATUS);
754 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
755 break;
756 udelay(10);
757 }
758
759
760
761
762
763
764
765 if (status & MCI_RXDATAAVLBLMASK) {
766 mmci_dma_error(host);
767 if (!data->error)
768 data->error = -EIO;
769 } else if (!data->host_cookie) {
770 mmci_dma_unmap(host, data);
771 }
772
773
774
775
776
777 if (status & MCI_RXDATAAVLBLMASK) {
778 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
779 mmci_dma_release(host);
780 }
781
782 host->dma_in_progress = false;
783 dmae->cur = NULL;
784 dmae->desc_current = NULL;
785 }
786
787
788 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
789 struct dma_chan **dma_chan,
790 struct dma_async_tx_descriptor **dma_desc)
791 {
792 struct mmci_dmae_priv *dmae = host->dma_priv;
793 struct variant_data *variant = host->variant;
794 struct dma_slave_config conf = {
795 .src_addr = host->phybase + MMCIFIFO,
796 .dst_addr = host->phybase + MMCIFIFO,
797 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
798 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
799 .src_maxburst = variant->fifohalfsize >> 2,
800 .dst_maxburst = variant->fifohalfsize >> 2,
801 .device_fc = false,
802 };
803 struct dma_chan *chan;
804 struct dma_device *device;
805 struct dma_async_tx_descriptor *desc;
806 int nr_sg;
807 unsigned long flags = DMA_CTRL_ACK;
808
809 if (data->flags & MMC_DATA_READ) {
810 conf.direction = DMA_DEV_TO_MEM;
811 chan = dmae->rx_channel;
812 } else {
813 conf.direction = DMA_MEM_TO_DEV;
814 chan = dmae->tx_channel;
815 }
816
817
818 if (!chan)
819 return -EINVAL;
820
821
822 if (data->blksz * data->blocks <= variant->fifosize)
823 return -EINVAL;
824
825 device = chan->device;
826 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
827 mmc_get_dma_dir(data));
828 if (nr_sg == 0)
829 return -EINVAL;
830
831 if (host->variant->qcom_dml)
832 flags |= DMA_PREP_INTERRUPT;
833
834 dmaengine_slave_config(chan, &conf);
835 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
836 conf.direction, flags);
837 if (!desc)
838 goto unmap_exit;
839
840 *dma_chan = chan;
841 *dma_desc = desc;
842
843 return 0;
844
845 unmap_exit:
846 dma_unmap_sg(device->dev, data->sg, data->sg_len,
847 mmc_get_dma_dir(data));
848 return -ENOMEM;
849 }
850
851 int mmci_dmae_prep_data(struct mmci_host *host,
852 struct mmc_data *data,
853 bool next)
854 {
855 struct mmci_dmae_priv *dmae = host->dma_priv;
856 struct mmci_dmae_next *nd = &dmae->next_data;
857
858 if (!host->use_dma)
859 return -EINVAL;
860
861 if (next)
862 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
863
864 if (dmae->cur && dmae->desc_current)
865 return 0;
866
867
868 return _mmci_dmae_prep_data(host, data, &dmae->cur,
869 &dmae->desc_current);
870 }
871
872 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
873 {
874 struct mmci_dmae_priv *dmae = host->dma_priv;
875
876 host->dma_in_progress = true;
877 dmaengine_submit(dmae->desc_current);
878 dma_async_issue_pending(dmae->cur);
879
880 *datactrl |= MCI_DPSM_DMAENABLE;
881
882 return 0;
883 }
884
885 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
886 {
887 struct mmci_dmae_priv *dmae = host->dma_priv;
888 struct mmci_dmae_next *next = &dmae->next_data;
889
890 if (!host->use_dma)
891 return;
892
893 WARN_ON(!data->host_cookie && (next->desc || next->chan));
894
895 dmae->desc_current = next->desc;
896 dmae->cur = next->chan;
897 next->desc = NULL;
898 next->chan = NULL;
899 }
900
901 void mmci_dmae_unprep_data(struct mmci_host *host,
902 struct mmc_data *data, int err)
903
904 {
905 struct mmci_dmae_priv *dmae = host->dma_priv;
906
907 if (!host->use_dma)
908 return;
909
910 mmci_dma_unmap(host, data);
911
912 if (err) {
913 struct mmci_dmae_next *next = &dmae->next_data;
914 struct dma_chan *chan;
915 if (data->flags & MMC_DATA_READ)
916 chan = dmae->rx_channel;
917 else
918 chan = dmae->tx_channel;
919 dmaengine_terminate_all(chan);
920
921 if (dmae->desc_current == next->desc)
922 dmae->desc_current = NULL;
923
924 if (dmae->cur == next->chan) {
925 host->dma_in_progress = false;
926 dmae->cur = NULL;
927 }
928
929 next->desc = NULL;
930 next->chan = NULL;
931 }
932 }
933
934 static struct mmci_host_ops mmci_variant_ops = {
935 .prep_data = mmci_dmae_prep_data,
936 .unprep_data = mmci_dmae_unprep_data,
937 .get_datactrl_cfg = mmci_get_dctrl_cfg,
938 .get_next_data = mmci_dmae_get_next_data,
939 .dma_setup = mmci_dmae_setup,
940 .dma_release = mmci_dmae_release,
941 .dma_start = mmci_dmae_start,
942 .dma_finalize = mmci_dmae_finalize,
943 .dma_error = mmci_dmae_error,
944 };
945 #else
946 static struct mmci_host_ops mmci_variant_ops = {
947 .get_datactrl_cfg = mmci_get_dctrl_cfg,
948 };
949 #endif
950
951 void mmci_variant_init(struct mmci_host *host)
952 {
953 host->ops = &mmci_variant_ops;
954 }
955
956 void ux500v2_variant_init(struct mmci_host *host)
957 {
958 host->ops = &mmci_variant_ops;
959 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
960 }
961
962 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
963 {
964 struct mmci_host *host = mmc_priv(mmc);
965 struct mmc_data *data = mrq->data;
966
967 if (!data)
968 return;
969
970 WARN_ON(data->host_cookie);
971
972 if (mmci_validate_data(host, data))
973 return;
974
975 mmci_prep_data(host, data, true);
976 }
977
978 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
979 int err)
980 {
981 struct mmci_host *host = mmc_priv(mmc);
982 struct mmc_data *data = mrq->data;
983
984 if (!data || !data->host_cookie)
985 return;
986
987 mmci_unprep_data(host, data, err);
988 }
989
990 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
991 {
992 struct variant_data *variant = host->variant;
993 unsigned int datactrl, timeout, irqmask;
994 unsigned long long clks;
995 void __iomem *base;
996
997 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
998 data->blksz, data->blocks, data->flags);
999
1000 host->data = data;
1001 host->size = data->blksz * data->blocks;
1002 data->bytes_xfered = 0;
1003
1004 clks = (unsigned long long)data->timeout_ns * host->cclk;
1005 do_div(clks, NSEC_PER_SEC);
1006
1007 timeout = data->timeout_clks + (unsigned int)clks;
1008
1009 base = host->base;
1010 writel(timeout, base + MMCIDATATIMER);
1011 writel(host->size, base + MMCIDATALENGTH);
1012
1013 datactrl = host->ops->get_datactrl_cfg(host);
1014 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
1015
1016 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
1017 u32 clk;
1018
1019 datactrl |= variant->datactrl_mask_sdio;
1020
1021
1022
1023
1024
1025
1026
1027 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
1028 (host->size < 8 ||
1029 (host->size <= 8 && host->mclk > 50000000)))
1030 clk = host->clk_reg & ~variant->clkreg_enable;
1031 else
1032 clk = host->clk_reg | variant->clkreg_enable;
1033
1034 mmci_write_clkreg(host, clk);
1035 }
1036
1037 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
1038 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
1039 datactrl |= variant->datactrl_mask_ddrmode;
1040
1041
1042
1043
1044
1045 if (!mmci_dma_start(host, datactrl))
1046 return;
1047
1048
1049 mmci_init_sg(host, data);
1050
1051 if (data->flags & MMC_DATA_READ) {
1052 irqmask = MCI_RXFIFOHALFFULLMASK;
1053
1054
1055
1056
1057
1058
1059 if (host->size < variant->fifohalfsize)
1060 irqmask |= MCI_RXDATAAVLBLMASK;
1061 } else {
1062
1063
1064
1065
1066 irqmask = MCI_TXFIFOHALFEMPTYMASK;
1067 }
1068
1069 mmci_write_datactrlreg(host, datactrl);
1070 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
1071 mmci_set_mask1(host, irqmask);
1072 }
1073
1074 static void
1075 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1076 {
1077 void __iomem *base = host->base;
1078
1079 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1080 cmd->opcode, cmd->arg, cmd->flags);
1081
1082 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
1083 writel(0, base + MMCICOMMAND);
1084 mmci_reg_delay(host);
1085 }
1086
1087 if (host->variant->cmdreg_stop &&
1088 cmd->opcode == MMC_STOP_TRANSMISSION)
1089 c |= host->variant->cmdreg_stop;
1090
1091 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
1092 if (cmd->flags & MMC_RSP_PRESENT) {
1093 if (cmd->flags & MMC_RSP_136)
1094 c |= host->variant->cmdreg_lrsp_crc;
1095 else if (cmd->flags & MMC_RSP_CRC)
1096 c |= host->variant->cmdreg_srsp_crc;
1097 else
1098 c |= host->variant->cmdreg_srsp;
1099 }
1100 if (0)
1101 c |= MCI_CPSM_INTERRUPT;
1102
1103 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
1104 c |= host->variant->data_cmd_enable;
1105
1106 host->cmd = cmd;
1107
1108 writel(cmd->arg, base + MMCIARGUMENT);
1109 writel(c, base + MMCICOMMAND);
1110 }
1111
1112 static void mmci_stop_command(struct mmci_host *host)
1113 {
1114 host->stop_abort.error = 0;
1115 mmci_start_command(host, &host->stop_abort, 0);
1116 }
1117
1118 static void
1119 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1120 unsigned int status)
1121 {
1122 unsigned int status_err;
1123
1124
1125 if (!data)
1126 return;
1127
1128
1129 status_err = status & (host->variant->start_err |
1130 MCI_DATACRCFAIL | MCI_DATATIMEOUT |
1131 MCI_TXUNDERRUN | MCI_RXOVERRUN);
1132
1133 if (status_err) {
1134 u32 remain, success;
1135
1136
1137 mmci_dma_error(host);
1138
1139
1140
1141
1142
1143
1144
1145
1146 if (!host->variant->datacnt_useless) {
1147 remain = readl(host->base + MMCIDATACNT);
1148 success = data->blksz * data->blocks - remain;
1149 } else {
1150 success = 0;
1151 }
1152
1153 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
1154 status_err, success);
1155 if (status_err & MCI_DATACRCFAIL) {
1156
1157 success -= 1;
1158 data->error = -EILSEQ;
1159 } else if (status_err & MCI_DATATIMEOUT) {
1160 data->error = -ETIMEDOUT;
1161 } else if (status_err & MCI_STARTBITERR) {
1162 data->error = -ECOMM;
1163 } else if (status_err & MCI_TXUNDERRUN) {
1164 data->error = -EIO;
1165 } else if (status_err & MCI_RXOVERRUN) {
1166 if (success > host->variant->fifosize)
1167 success -= host->variant->fifosize;
1168 else
1169 success = 0;
1170 data->error = -EIO;
1171 }
1172 data->bytes_xfered = round_down(success, data->blksz);
1173 }
1174
1175 if (status & MCI_DATABLOCKEND)
1176 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
1177
1178 if (status & MCI_DATAEND || data->error) {
1179 mmci_dma_finalize(host, data);
1180
1181 mmci_stop_data(host);
1182
1183 if (!data->error)
1184
1185 data->bytes_xfered = data->blksz * data->blocks;
1186
1187 if (!data->stop) {
1188 if (host->variant->cmdreg_stop && data->error)
1189 mmci_stop_command(host);
1190 else
1191 mmci_request_end(host, data->mrq);
1192 } else if (host->mrq->sbc && !data->error) {
1193 mmci_request_end(host, data->mrq);
1194 } else {
1195 mmci_start_command(host, data->stop, 0);
1196 }
1197 }
1198 }
1199
1200 static void
1201 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1202 unsigned int status)
1203 {
1204 void __iomem *base = host->base;
1205 bool sbc, busy_resp;
1206
1207 if (!cmd)
1208 return;
1209
1210 sbc = (cmd == host->mrq->sbc);
1211 busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
1212
1213
1214
1215
1216
1217
1218 if (!((status|host->busy_status) &
1219 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
1220 return;
1221
1222
1223 if (busy_resp && host->variant->busy_detect) {
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238 if (!host->busy_status &&
1239 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1240 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1241
1242 writel(readl(base + MMCIMASK0) |
1243 host->variant->busy_detect_mask,
1244 base + MMCIMASK0);
1245
1246 host->busy_status =
1247 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1248 return;
1249 }
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262 if (host->busy_status &&
1263 (status & host->variant->busy_detect_flag)) {
1264 writel(host->variant->busy_detect_mask,
1265 host->base + MMCICLEAR);
1266 return;
1267 }
1268
1269
1270
1271
1272
1273
1274
1275 if (host->busy_status) {
1276
1277 writel(host->variant->busy_detect_mask,
1278 host->base + MMCICLEAR);
1279
1280 writel(readl(base + MMCIMASK0) &
1281 ~host->variant->busy_detect_mask,
1282 base + MMCIMASK0);
1283 host->busy_status = 0;
1284 }
1285 }
1286
1287 host->cmd = NULL;
1288
1289 if (status & MCI_CMDTIMEOUT) {
1290 cmd->error = -ETIMEDOUT;
1291 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1292 cmd->error = -EILSEQ;
1293 } else {
1294 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1295 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1296 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1297 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1298 }
1299
1300 if ((!sbc && !cmd->data) || cmd->error) {
1301 if (host->data) {
1302
1303 mmci_dma_error(host);
1304
1305 mmci_stop_data(host);
1306 if (host->variant->cmdreg_stop && cmd->error) {
1307 mmci_stop_command(host);
1308 return;
1309 }
1310 }
1311 mmci_request_end(host, host->mrq);
1312 } else if (sbc) {
1313 mmci_start_command(host, host->mrq->cmd, 0);
1314 } else if (!host->variant->datactrl_first &&
1315 !(cmd->data->flags & MMC_DATA_READ)) {
1316 mmci_start_data(host, cmd->data);
1317 }
1318 }
1319
1320 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1321 {
1322 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1323 }
1324
1325 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1326 {
1327
1328
1329
1330
1331 if (status & MCI_RXFIFOHALFFULL)
1332 return host->variant->fifohalfsize;
1333 else if (status & MCI_RXDATAAVLBL)
1334 return 4;
1335
1336 return 0;
1337 }
1338
1339 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1340 {
1341 void __iomem *base = host->base;
1342 char *ptr = buffer;
1343 u32 status = readl(host->base + MMCISTATUS);
1344 int host_remain = host->size;
1345
1346 do {
1347 int count = host->get_rx_fifocnt(host, status, host_remain);
1348
1349 if (count > remain)
1350 count = remain;
1351
1352 if (count <= 0)
1353 break;
1354
1355
1356
1357
1358
1359
1360
1361 if (unlikely(count & 0x3)) {
1362 if (count < 4) {
1363 unsigned char buf[4];
1364 ioread32_rep(base + MMCIFIFO, buf, 1);
1365 memcpy(ptr, buf, count);
1366 } else {
1367 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1368 count &= ~0x3;
1369 }
1370 } else {
1371 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1372 }
1373
1374 ptr += count;
1375 remain -= count;
1376 host_remain -= count;
1377
1378 if (remain == 0)
1379 break;
1380
1381 status = readl(base + MMCISTATUS);
1382 } while (status & MCI_RXDATAAVLBL);
1383
1384 return ptr - buffer;
1385 }
1386
1387 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1388 {
1389 struct variant_data *variant = host->variant;
1390 void __iomem *base = host->base;
1391 char *ptr = buffer;
1392
1393 do {
1394 unsigned int count, maxcnt;
1395
1396 maxcnt = status & MCI_TXFIFOEMPTY ?
1397 variant->fifosize : variant->fifohalfsize;
1398 count = min(remain, maxcnt);
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1409
1410 ptr += count;
1411 remain -= count;
1412
1413 if (remain == 0)
1414 break;
1415
1416 status = readl(base + MMCISTATUS);
1417 } while (status & MCI_TXFIFOHALFEMPTY);
1418
1419 return ptr - buffer;
1420 }
1421
1422
1423
1424
1425 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1426 {
1427 struct mmci_host *host = dev_id;
1428 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1429 struct variant_data *variant = host->variant;
1430 void __iomem *base = host->base;
1431 u32 status;
1432
1433 status = readl(base + MMCISTATUS);
1434
1435 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1436
1437 do {
1438 unsigned int remain, len;
1439 char *buffer;
1440
1441
1442
1443
1444
1445
1446
1447
1448 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1449 break;
1450
1451 if (!sg_miter_next(sg_miter))
1452 break;
1453
1454 buffer = sg_miter->addr;
1455 remain = sg_miter->length;
1456
1457 len = 0;
1458 if (status & MCI_RXACTIVE)
1459 len = mmci_pio_read(host, buffer, remain);
1460 if (status & MCI_TXACTIVE)
1461 len = mmci_pio_write(host, buffer, remain, status);
1462
1463 sg_miter->consumed = len;
1464
1465 host->size -= len;
1466 remain -= len;
1467
1468 if (remain)
1469 break;
1470
1471 status = readl(base + MMCISTATUS);
1472 } while (1);
1473
1474 sg_miter_stop(sg_miter);
1475
1476
1477
1478
1479
1480 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1481 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1482
1483
1484
1485
1486
1487
1488
1489 if (host->size == 0) {
1490 mmci_set_mask1(host, 0);
1491 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1492 }
1493
1494 return IRQ_HANDLED;
1495 }
1496
1497
1498
1499
1500 static irqreturn_t mmci_irq(int irq, void *dev_id)
1501 {
1502 struct mmci_host *host = dev_id;
1503 u32 status;
1504 int ret = 0;
1505
1506 spin_lock(&host->lock);
1507
1508 do {
1509 status = readl(host->base + MMCISTATUS);
1510
1511 if (host->singleirq) {
1512 if (status & host->mask1_reg)
1513 mmci_pio_irq(irq, dev_id);
1514
1515 status &= ~host->variant->irq_pio_mask;
1516 }
1517
1518
1519
1520
1521
1522 status &= readl(host->base + MMCIMASK0);
1523 if (host->variant->busy_detect)
1524 writel(status & ~host->variant->busy_detect_mask,
1525 host->base + MMCICLEAR);
1526 else
1527 writel(status, host->base + MMCICLEAR);
1528
1529 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1530
1531 if (host->variant->reversed_irq_handling) {
1532 mmci_data_irq(host, host->data, status);
1533 mmci_cmd_irq(host, host->cmd, status);
1534 } else {
1535 mmci_cmd_irq(host, host->cmd, status);
1536 mmci_data_irq(host, host->data, status);
1537 }
1538
1539
1540
1541
1542
1543 if (host->variant->busy_detect_flag)
1544 status &= ~host->variant->busy_detect_flag;
1545
1546 ret = 1;
1547 } while (status);
1548
1549 spin_unlock(&host->lock);
1550
1551 return IRQ_RETVAL(ret);
1552 }
1553
1554 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1555 {
1556 struct mmci_host *host = mmc_priv(mmc);
1557 unsigned long flags;
1558
1559 WARN_ON(host->mrq != NULL);
1560
1561 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1562 if (mrq->cmd->error) {
1563 mmc_request_done(mmc, mrq);
1564 return;
1565 }
1566
1567 spin_lock_irqsave(&host->lock, flags);
1568
1569 host->mrq = mrq;
1570
1571 if (mrq->data)
1572 mmci_get_next_data(host, mrq->data);
1573
1574 if (mrq->data &&
1575 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
1576 mmci_start_data(host, mrq->data);
1577
1578 if (mrq->sbc)
1579 mmci_start_command(host, mrq->sbc, 0);
1580 else
1581 mmci_start_command(host, mrq->cmd, 0);
1582
1583 spin_unlock_irqrestore(&host->lock, flags);
1584 }
1585
1586 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1587 {
1588 struct mmci_host *host = mmc_priv(mmc);
1589 struct variant_data *variant = host->variant;
1590 u32 pwr = 0;
1591 unsigned long flags;
1592 int ret;
1593
1594 if (host->plat->ios_handler &&
1595 host->plat->ios_handler(mmc_dev(mmc), ios))
1596 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1597
1598 switch (ios->power_mode) {
1599 case MMC_POWER_OFF:
1600 if (!IS_ERR(mmc->supply.vmmc))
1601 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1602
1603 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1604 regulator_disable(mmc->supply.vqmmc);
1605 host->vqmmc_enabled = false;
1606 }
1607
1608 break;
1609 case MMC_POWER_UP:
1610 if (!IS_ERR(mmc->supply.vmmc))
1611 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1612
1613
1614
1615
1616
1617
1618 pwr |= variant->pwrreg_powerup;
1619
1620 break;
1621 case MMC_POWER_ON:
1622 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1623 ret = regulator_enable(mmc->supply.vqmmc);
1624 if (ret < 0)
1625 dev_err(mmc_dev(mmc),
1626 "failed to enable vqmmc regulator\n");
1627 else
1628 host->vqmmc_enabled = true;
1629 }
1630
1631 pwr |= MCI_PWR_ON;
1632 break;
1633 }
1634
1635 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1636
1637
1638
1639
1640
1641 pwr |= host->pwr_reg_add;
1642
1643 if (ios->bus_width == MMC_BUS_WIDTH_4)
1644 pwr &= ~MCI_ST_DATA74DIREN;
1645 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1646 pwr &= (~MCI_ST_DATA74DIREN &
1647 ~MCI_ST_DATA31DIREN &
1648 ~MCI_ST_DATA2DIREN);
1649 }
1650
1651 if (variant->opendrain) {
1652 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1653 pwr |= variant->opendrain;
1654 } else {
1655
1656
1657
1658
1659 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1660 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1661 else
1662 pinctrl_select_state(host->pinctrl, host->pins_default);
1663 }
1664
1665
1666
1667
1668
1669 if (!ios->clock && variant->pwrreg_clkgate)
1670 pwr &= ~MCI_PWR_ON;
1671
1672 if (host->variant->explicit_mclk_control &&
1673 ios->clock != host->clock_cache) {
1674 ret = clk_set_rate(host->clk, ios->clock);
1675 if (ret < 0)
1676 dev_err(mmc_dev(host->mmc),
1677 "Error setting clock rate (%d)\n", ret);
1678 else
1679 host->mclk = clk_get_rate(host->clk);
1680 }
1681 host->clock_cache = ios->clock;
1682
1683 spin_lock_irqsave(&host->lock, flags);
1684
1685 if (host->ops && host->ops->set_clkreg)
1686 host->ops->set_clkreg(host, ios->clock);
1687 else
1688 mmci_set_clkreg(host, ios->clock);
1689
1690 if (host->ops && host->ops->set_pwrreg)
1691 host->ops->set_pwrreg(host, pwr);
1692 else
1693 mmci_write_pwrreg(host, pwr);
1694
1695 mmci_reg_delay(host);
1696
1697 spin_unlock_irqrestore(&host->lock, flags);
1698 }
1699
1700 static int mmci_get_cd(struct mmc_host *mmc)
1701 {
1702 struct mmci_host *host = mmc_priv(mmc);
1703 struct mmci_platform_data *plat = host->plat;
1704 unsigned int status = mmc_gpio_get_cd(mmc);
1705
1706 if (status == -ENOSYS) {
1707 if (!plat->status)
1708 return 1;
1709
1710 status = plat->status(mmc_dev(host->mmc));
1711 }
1712 return status;
1713 }
1714
1715 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1716 {
1717 int ret = 0;
1718
1719 if (!IS_ERR(mmc->supply.vqmmc)) {
1720
1721 switch (ios->signal_voltage) {
1722 case MMC_SIGNAL_VOLTAGE_330:
1723 ret = regulator_set_voltage(mmc->supply.vqmmc,
1724 2700000, 3600000);
1725 break;
1726 case MMC_SIGNAL_VOLTAGE_180:
1727 ret = regulator_set_voltage(mmc->supply.vqmmc,
1728 1700000, 1950000);
1729 break;
1730 case MMC_SIGNAL_VOLTAGE_120:
1731 ret = regulator_set_voltage(mmc->supply.vqmmc,
1732 1100000, 1300000);
1733 break;
1734 }
1735
1736 if (ret)
1737 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1738 }
1739
1740 return ret;
1741 }
1742
1743 static struct mmc_host_ops mmci_ops = {
1744 .request = mmci_request,
1745 .pre_req = mmci_pre_request,
1746 .post_req = mmci_post_request,
1747 .set_ios = mmci_set_ios,
1748 .get_ro = mmc_gpio_get_ro,
1749 .get_cd = mmci_get_cd,
1750 .start_signal_voltage_switch = mmci_sig_volt_switch,
1751 };
1752
1753 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1754 {
1755 struct mmci_host *host = mmc_priv(mmc);
1756 int ret = mmc_of_parse(mmc);
1757
1758 if (ret)
1759 return ret;
1760
1761 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1762 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1763 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1764 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1765 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1766 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1767 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1768 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1769 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1770 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1771 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1772 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1773 if (of_get_property(np, "st,sig-dir", NULL))
1774 host->pwr_reg_add |= MCI_STM32_DIRPOL;
1775 if (of_get_property(np, "st,neg-edge", NULL))
1776 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
1777 if (of_get_property(np, "st,use-ckin", NULL))
1778 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
1779
1780 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1781 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1782 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1783 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1784
1785 return 0;
1786 }
1787
1788 static int mmci_probe(struct amba_device *dev,
1789 const struct amba_id *id)
1790 {
1791 struct mmci_platform_data *plat = dev->dev.platform_data;
1792 struct device_node *np = dev->dev.of_node;
1793 struct variant_data *variant = id->data;
1794 struct mmci_host *host;
1795 struct mmc_host *mmc;
1796 int ret;
1797
1798
1799 if (!plat && !np) {
1800 dev_err(&dev->dev, "No plat data or DT found\n");
1801 return -EINVAL;
1802 }
1803
1804 if (!plat) {
1805 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1806 if (!plat)
1807 return -ENOMEM;
1808 }
1809
1810 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1811 if (!mmc)
1812 return -ENOMEM;
1813
1814 ret = mmci_of_parse(np, mmc);
1815 if (ret)
1816 goto host_free;
1817
1818 host = mmc_priv(mmc);
1819 host->mmc = mmc;
1820
1821
1822
1823
1824
1825 if (!variant->opendrain) {
1826 host->pinctrl = devm_pinctrl_get(&dev->dev);
1827 if (IS_ERR(host->pinctrl)) {
1828 dev_err(&dev->dev, "failed to get pinctrl");
1829 ret = PTR_ERR(host->pinctrl);
1830 goto host_free;
1831 }
1832
1833 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1834 PINCTRL_STATE_DEFAULT);
1835 if (IS_ERR(host->pins_default)) {
1836 dev_err(mmc_dev(mmc), "Can't select default pins\n");
1837 ret = PTR_ERR(host->pins_default);
1838 goto host_free;
1839 }
1840
1841 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1842 MMCI_PINCTRL_STATE_OPENDRAIN);
1843 if (IS_ERR(host->pins_opendrain)) {
1844 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
1845 ret = PTR_ERR(host->pins_opendrain);
1846 goto host_free;
1847 }
1848 }
1849
1850 host->hw_designer = amba_manf(dev);
1851 host->hw_revision = amba_rev(dev);
1852 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1853 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1854
1855 host->clk = devm_clk_get(&dev->dev, NULL);
1856 if (IS_ERR(host->clk)) {
1857 ret = PTR_ERR(host->clk);
1858 goto host_free;
1859 }
1860
1861 ret = clk_prepare_enable(host->clk);
1862 if (ret)
1863 goto host_free;
1864
1865 if (variant->qcom_fifo)
1866 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1867 else
1868 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1869
1870 host->plat = plat;
1871 host->variant = variant;
1872 host->mclk = clk_get_rate(host->clk);
1873
1874
1875
1876
1877
1878 if (host->mclk > variant->f_max) {
1879 ret = clk_set_rate(host->clk, variant->f_max);
1880 if (ret < 0)
1881 goto clk_disable;
1882 host->mclk = clk_get_rate(host->clk);
1883 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1884 host->mclk);
1885 }
1886
1887 host->phybase = dev->res.start;
1888 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1889 if (IS_ERR(host->base)) {
1890 ret = PTR_ERR(host->base);
1891 goto clk_disable;
1892 }
1893
1894 if (variant->init)
1895 variant->init(host);
1896
1897
1898
1899
1900
1901
1902
1903 if (variant->st_clkdiv)
1904 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1905 else if (variant->stm32_clkdiv)
1906 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
1907 else if (variant->explicit_mclk_control)
1908 mmc->f_min = clk_round_rate(host->clk, 100000);
1909 else
1910 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1911
1912
1913
1914
1915
1916
1917 if (mmc->f_max)
1918 mmc->f_max = variant->explicit_mclk_control ?
1919 min(variant->f_max, mmc->f_max) :
1920 min(host->mclk, mmc->f_max);
1921 else
1922 mmc->f_max = variant->explicit_mclk_control ?
1923 fmax : min(host->mclk, fmax);
1924
1925
1926 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1927
1928 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
1929 if (IS_ERR(host->rst)) {
1930 ret = PTR_ERR(host->rst);
1931 goto clk_disable;
1932 }
1933
1934
1935 ret = mmc_regulator_get_supply(mmc);
1936 if (ret)
1937 goto clk_disable;
1938
1939 if (!mmc->ocr_avail)
1940 mmc->ocr_avail = plat->ocr_mask;
1941 else if (plat->ocr_mask)
1942 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1943
1944
1945 mmc->caps |= MMC_CAP_CMD23;
1946
1947
1948
1949
1950 if (variant->busy_detect) {
1951 mmci_ops.card_busy = mmci_card_busy;
1952
1953
1954
1955
1956 if (variant->busy_dpsm_flag)
1957 mmci_write_datactrlreg(host,
1958 host->variant->busy_dpsm_flag);
1959 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1960 mmc->max_busy_timeout = 0;
1961 }
1962
1963
1964 host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
1965 host->stop_abort.arg = 0;
1966 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
1967
1968 mmc->ops = &mmci_ops;
1969
1970
1971 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1972
1973
1974
1975
1976 mmc->max_segs = NR_SG;
1977
1978
1979
1980
1981
1982
1983 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1984
1985
1986
1987
1988
1989 mmc->max_seg_size = mmc->max_req_size;
1990
1991
1992
1993
1994 mmc->max_blk_size = 1 << variant->datactrl_blocksz;
1995
1996
1997
1998
1999
2000 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
2001
2002 spin_lock_init(&host->lock);
2003
2004 writel(0, host->base + MMCIMASK0);
2005
2006 if (variant->mmcimask1)
2007 writel(0, host->base + MMCIMASK1);
2008
2009 writel(0xfff, host->base + MMCICLEAR);
2010
2011
2012
2013
2014
2015
2016
2017
2018 if (!np) {
2019 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
2020 if (ret == -EPROBE_DEFER)
2021 goto clk_disable;
2022
2023 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0, NULL);
2024 if (ret == -EPROBE_DEFER)
2025 goto clk_disable;
2026 }
2027
2028 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
2029 DRIVER_NAME " (cmd)", host);
2030 if (ret)
2031 goto clk_disable;
2032
2033 if (!dev->irq[1])
2034 host->singleirq = true;
2035 else {
2036 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
2037 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2038 if (ret)
2039 goto clk_disable;
2040 }
2041
2042 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
2043
2044 amba_set_drvdata(dev, mmc);
2045
2046 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
2047 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
2048 amba_rev(dev), (unsigned long long)dev->res.start,
2049 dev->irq[0], dev->irq[1]);
2050
2051 mmci_dma_setup(host);
2052
2053 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
2054 pm_runtime_use_autosuspend(&dev->dev);
2055
2056 mmc_add_host(mmc);
2057
2058 pm_runtime_put(&dev->dev);
2059 return 0;
2060
2061 clk_disable:
2062 clk_disable_unprepare(host->clk);
2063 host_free:
2064 mmc_free_host(mmc);
2065 return ret;
2066 }
2067
2068 static int mmci_remove(struct amba_device *dev)
2069 {
2070 struct mmc_host *mmc = amba_get_drvdata(dev);
2071
2072 if (mmc) {
2073 struct mmci_host *host = mmc_priv(mmc);
2074 struct variant_data *variant = host->variant;
2075
2076
2077
2078
2079
2080 pm_runtime_get_sync(&dev->dev);
2081
2082 mmc_remove_host(mmc);
2083
2084 writel(0, host->base + MMCIMASK0);
2085
2086 if (variant->mmcimask1)
2087 writel(0, host->base + MMCIMASK1);
2088
2089 writel(0, host->base + MMCICOMMAND);
2090 writel(0, host->base + MMCIDATACTRL);
2091
2092 mmci_dma_release(host);
2093 clk_disable_unprepare(host->clk);
2094 mmc_free_host(mmc);
2095 }
2096
2097 return 0;
2098 }
2099
2100 #ifdef CONFIG_PM
2101 static void mmci_save(struct mmci_host *host)
2102 {
2103 unsigned long flags;
2104
2105 spin_lock_irqsave(&host->lock, flags);
2106
2107 writel(0, host->base + MMCIMASK0);
2108 if (host->variant->pwrreg_nopower) {
2109 writel(0, host->base + MMCIDATACTRL);
2110 writel(0, host->base + MMCIPOWER);
2111 writel(0, host->base + MMCICLOCK);
2112 }
2113 mmci_reg_delay(host);
2114
2115 spin_unlock_irqrestore(&host->lock, flags);
2116 }
2117
2118 static void mmci_restore(struct mmci_host *host)
2119 {
2120 unsigned long flags;
2121
2122 spin_lock_irqsave(&host->lock, flags);
2123
2124 if (host->variant->pwrreg_nopower) {
2125 writel(host->clk_reg, host->base + MMCICLOCK);
2126 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2127 writel(host->pwr_reg, host->base + MMCIPOWER);
2128 }
2129 writel(MCI_IRQENABLE | host->variant->start_err,
2130 host->base + MMCIMASK0);
2131 mmci_reg_delay(host);
2132
2133 spin_unlock_irqrestore(&host->lock, flags);
2134 }
2135
2136 static int mmci_runtime_suspend(struct device *dev)
2137 {
2138 struct amba_device *adev = to_amba_device(dev);
2139 struct mmc_host *mmc = amba_get_drvdata(adev);
2140
2141 if (mmc) {
2142 struct mmci_host *host = mmc_priv(mmc);
2143 pinctrl_pm_select_sleep_state(dev);
2144 mmci_save(host);
2145 clk_disable_unprepare(host->clk);
2146 }
2147
2148 return 0;
2149 }
2150
2151 static int mmci_runtime_resume(struct device *dev)
2152 {
2153 struct amba_device *adev = to_amba_device(dev);
2154 struct mmc_host *mmc = amba_get_drvdata(adev);
2155
2156 if (mmc) {
2157 struct mmci_host *host = mmc_priv(mmc);
2158 clk_prepare_enable(host->clk);
2159 mmci_restore(host);
2160 pinctrl_pm_select_default_state(dev);
2161 }
2162
2163 return 0;
2164 }
2165 #endif
2166
2167 static const struct dev_pm_ops mmci_dev_pm_ops = {
2168 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2169 pm_runtime_force_resume)
2170 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
2171 };
2172
2173 static const struct amba_id mmci_ids[] = {
2174 {
2175 .id = 0x00041180,
2176 .mask = 0xff0fffff,
2177 .data = &variant_arm,
2178 },
2179 {
2180 .id = 0x01041180,
2181 .mask = 0xff0fffff,
2182 .data = &variant_arm_extended_fifo,
2183 },
2184 {
2185 .id = 0x02041180,
2186 .mask = 0xff0fffff,
2187 .data = &variant_arm_extended_fifo_hwfc,
2188 },
2189 {
2190 .id = 0x00041181,
2191 .mask = 0x000fffff,
2192 .data = &variant_arm,
2193 },
2194
2195 {
2196 .id = 0x00180180,
2197 .mask = 0x00ffffff,
2198 .data = &variant_u300,
2199 },
2200 {
2201 .id = 0x10180180,
2202 .mask = 0xf0ffffff,
2203 .data = &variant_nomadik,
2204 },
2205 {
2206 .id = 0x00280180,
2207 .mask = 0x00ffffff,
2208 .data = &variant_nomadik,
2209 },
2210 {
2211 .id = 0x00480180,
2212 .mask = 0xf0ffffff,
2213 .data = &variant_ux500,
2214 },
2215 {
2216 .id = 0x10480180,
2217 .mask = 0xf0ffffff,
2218 .data = &variant_ux500v2,
2219 },
2220 {
2221 .id = 0x00880180,
2222 .mask = 0x00ffffff,
2223 .data = &variant_stm32,
2224 },
2225 {
2226 .id = 0x10153180,
2227 .mask = 0xf0ffffff,
2228 .data = &variant_stm32_sdmmc,
2229 },
2230
2231 {
2232 .id = 0x00051180,
2233 .mask = 0x000fffff,
2234 .data = &variant_qcom,
2235 },
2236 { 0, 0 },
2237 };
2238
2239 MODULE_DEVICE_TABLE(amba, mmci_ids);
2240
2241 static struct amba_driver mmci_driver = {
2242 .drv = {
2243 .name = DRIVER_NAME,
2244 .pm = &mmci_dev_pm_ops,
2245 },
2246 .probe = mmci_probe,
2247 .remove = mmci_remove,
2248 .id_table = mmci_ids,
2249 };
2250
2251 module_amba_driver(mmci_driver);
2252
2253 module_param(fmax, uint, 0444);
2254
2255 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
2256 MODULE_LICENSE("GPL");