root/drivers/mmc/host/dw_mmc-zx.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _DW_MMC_ZX_H_
   3 #define _DW_MMC_ZX_H_
   4 
   5 /* ZX296718 SoC specific DLL register offset. */
   6 #define LB_AON_EMMC_CFG_REG0  0x1B0
   7 #define LB_AON_EMMC_CFG_REG1  0x1B4
   8 #define LB_AON_EMMC_CFG_REG2  0x1B8
   9 
  10 /* LB_AON_EMMC_CFG_REG0 register defines */
  11 #define PARA_DLL_START(x)       ((x) & 0xFF)
  12 #define PARA_DLL_START_MASK     0xFF
  13 #define DLL_REG_SET             BIT(8)
  14 #define PARA_DLL_LOCK_NUM(x)    (((x) & 7) << 16)
  15 #define PARA_DLL_LOCK_NUM_MASK  (7 << 16)
  16 #define PARA_PHASE_DET_SEL(x)   (((x) & 7) << 20)
  17 #define PARA_PHASE_DET_SEL_MASK (7 << 20)
  18 #define PARA_DLL_BYPASS_MODE    BIT(23)
  19 #define PARA_HALF_CLK_MODE      BIT(24)
  20 
  21 /* LB_AON_EMMC_CFG_REG1 register defines */
  22 #define READ_DQS_DELAY(x)       ((x) & 0x7F)
  23 #define READ_DQS_DELAY_MASK     (0x7F)
  24 #define READ_DQS_BYPASS_MODE    BIT(7)
  25 #define CLK_SAMP_DELAY(x)       (((x) & 0x7F) << 8)
  26 #define CLK_SAMP_DELAY_MASK     (0x7F << 8)
  27 #define CLK_SAMP_BYPASS_MODE    BIT(15)
  28 
  29 /* LB_AON_EMMC_CFG_REG2 register defines */
  30 #define ZX_DLL_LOCKED           BIT(2)
  31 
  32 #endif /* _DW_MMC_ZX_H_ */