drivers/mmc/host/mtk-sd.c

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This source file includes following definitions.
sdr_set_bits
sdr_clr_bits
sdr_set_field
sdr_get_field
msdc_reset_hw
msdc_dma_calcs
msdc_dma_setup
msdc_prepare_data
msdc_unprepare_data
msdc_set_timeout
msdc_gate_clock
msdc_ungate_clock
msdc_set_mclk
msdc_cmd_find_resp
msdc_cmd_prepare_raw_cmd
msdc_start_data
msdc_auto_cmd_done
msdc_track_cmd_data
msdc_request_done
msdc_cmd_done
msdc_cmd_is_ready
msdc_start_command
msdc_cmd_next
msdc_ops_request
msdc_pre_req
msdc_post_req
msdc_data_xfer_next
msdc_data_xfer_done
msdc_set_buswidth
msdc_ops_switch_volt
msdc_card_busy
msdc_request_timeout
__msdc_enable_sdio_irq
msdc_enable_sdio_irq
msdc_irq
msdc_init_hw
msdc_deinit_hw
msdc_init_gpd_bd
msdc_ops_set_ios
test_delay_bit
get_delay_len
get_best_delay
msdc_set_cmd_delay
msdc_set_data_delay
msdc_tune_response
hs400_tune_response
msdc_tune_data
msdc_tune_together
msdc_execute_tuning
msdc_prepare_hs400_tuning
msdc_hw_reset
msdc_ack_sdio_irq
msdc_get_cd
msdc_of_property_parse
msdc_drv_probe
msdc_drv_remove
msdc_save_reg
msdc_restore_reg
msdc_runtime_suspend
msdc_runtime_resume
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2015 MediaTek Inc.
   4  * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
   5  */
   6 
   7 #include <linux/module.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/ioport.h>
  12 #include <linux/irq.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/pinctrl/consumer.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/slab.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 
  26 #include <linux/mmc/card.h>
  27 #include <linux/mmc/core.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sd.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33 
  34 #define MAX_BD_NUM          1024
  35 
  36 /*--------------------------------------------------------------------------*/
  37 /* Common Definition                                                        */
  38 /*--------------------------------------------------------------------------*/
  39 #define MSDC_BUS_1BITS          0x0
  40 #define MSDC_BUS_4BITS          0x1
  41 #define MSDC_BUS_8BITS          0x2
  42 
  43 #define MSDC_BURST_64B          0x6
  44 
  45 /*--------------------------------------------------------------------------*/
  46 /* Register Offset                                                          */
  47 /*--------------------------------------------------------------------------*/
  48 #define MSDC_CFG         0x0
  49 #define MSDC_IOCON       0x04
  50 #define MSDC_PS          0x08
  51 #define MSDC_INT         0x0c
  52 #define MSDC_INTEN       0x10
  53 #define MSDC_FIFOCS      0x14
  54 #define SDC_CFG          0x30
  55 #define SDC_CMD          0x34
  56 #define SDC_ARG          0x38
  57 #define SDC_STS          0x3c
  58 #define SDC_RESP0        0x40
  59 #define SDC_RESP1        0x44
  60 #define SDC_RESP2        0x48
  61 #define SDC_RESP3        0x4c
  62 #define SDC_BLK_NUM      0x50
  63 #define SDC_ADV_CFG0     0x64
  64 #define EMMC_IOCON       0x7c
  65 #define SDC_ACMD_RESP    0x80
  66 #define DMA_SA_H4BIT     0x8c
  67 #define MSDC_DMA_SA      0x90
  68 #define MSDC_DMA_CTRL    0x98
  69 #define MSDC_DMA_CFG     0x9c
  70 #define MSDC_PATCH_BIT   0xb0
  71 #define MSDC_PATCH_BIT1  0xb4
  72 #define MSDC_PATCH_BIT2  0xb8
  73 #define MSDC_PAD_TUNE    0xec
  74 #define MSDC_PAD_TUNE0   0xf0
  75 #define PAD_DS_TUNE      0x188
  76 #define PAD_CMD_TUNE     0x18c
  77 #define EMMC50_CFG0      0x208
  78 #define EMMC50_CFG3      0x220
  79 #define SDC_FIFO_CFG     0x228
  80 
  81 /*--------------------------------------------------------------------------*/
  82 /* Top Pad Register Offset                                                  */
  83 /*--------------------------------------------------------------------------*/
  84 #define EMMC_TOP_CONTROL        0x00
  85 #define EMMC_TOP_CMD            0x04
  86 #define EMMC50_PAD_DS_TUNE      0x0c
  87 
  88 /*--------------------------------------------------------------------------*/
  89 /* Register Mask                                                            */
  90 /*--------------------------------------------------------------------------*/
  91 
  92 /* MSDC_CFG mask */
  93 #define MSDC_CFG_MODE           (0x1 << 0)      /* RW */
  94 #define MSDC_CFG_CKPDN          (0x1 << 1)      /* RW */
  95 #define MSDC_CFG_RST            (0x1 << 2)      /* RW */
  96 #define MSDC_CFG_PIO            (0x1 << 3)      /* RW */
  97 #define MSDC_CFG_CKDRVEN        (0x1 << 4)      /* RW */
  98 #define MSDC_CFG_BV18SDT        (0x1 << 5)      /* RW */
  99 #define MSDC_CFG_BV18PSS        (0x1 << 6)      /* R  */
 100 #define MSDC_CFG_CKSTB          (0x1 << 7)      /* R  */
 101 #define MSDC_CFG_CKDIV          (0xff << 8)     /* RW */
 102 #define MSDC_CFG_CKMOD          (0x3 << 16)     /* RW */
 103 #define MSDC_CFG_HS400_CK_MODE  (0x1 << 18)     /* RW */
 104 #define MSDC_CFG_HS400_CK_MODE_EXTRA  (0x1 << 22)       /* RW */
 105 #define MSDC_CFG_CKDIV_EXTRA    (0xfff << 8)    /* RW */
 106 #define MSDC_CFG_CKMOD_EXTRA    (0x3 << 20)     /* RW */
 107 
 108 /* MSDC_IOCON mask */
 109 #define MSDC_IOCON_SDR104CKS    (0x1 << 0)      /* RW */
 110 #define MSDC_IOCON_RSPL         (0x1 << 1)      /* RW */
 111 #define MSDC_IOCON_DSPL         (0x1 << 2)      /* RW */
 112 #define MSDC_IOCON_DDLSEL       (0x1 << 3)      /* RW */
 113 #define MSDC_IOCON_DDR50CKD     (0x1 << 4)      /* RW */
 114 #define MSDC_IOCON_DSPLSEL      (0x1 << 5)      /* RW */
 115 #define MSDC_IOCON_W_DSPL       (0x1 << 8)      /* RW */
 116 #define MSDC_IOCON_D0SPL        (0x1 << 16)     /* RW */
 117 #define MSDC_IOCON_D1SPL        (0x1 << 17)     /* RW */
 118 #define MSDC_IOCON_D2SPL        (0x1 << 18)     /* RW */
 119 #define MSDC_IOCON_D3SPL        (0x1 << 19)     /* RW */
 120 #define MSDC_IOCON_D4SPL        (0x1 << 20)     /* RW */
 121 #define MSDC_IOCON_D5SPL        (0x1 << 21)     /* RW */
 122 #define MSDC_IOCON_D6SPL        (0x1 << 22)     /* RW */
 123 #define MSDC_IOCON_D7SPL        (0x1 << 23)     /* RW */
 124 #define MSDC_IOCON_RISCSZ       (0x3 << 24)     /* RW */
 125 
 126 /* MSDC_PS mask */
 127 #define MSDC_PS_CDEN            (0x1 << 0)      /* RW */
 128 #define MSDC_PS_CDSTS           (0x1 << 1)      /* R  */
 129 #define MSDC_PS_CDDEBOUNCE      (0xf << 12)     /* RW */
 130 #define MSDC_PS_DAT             (0xff << 16)    /* R  */
 131 #define MSDC_PS_CMD             (0x1 << 24)     /* R  */
 132 #define MSDC_PS_WP              (0x1 << 31)     /* R  */
 133 
 134 /* MSDC_INT mask */
 135 #define MSDC_INT_MMCIRQ         (0x1 << 0)      /* W1C */
 136 #define MSDC_INT_CDSC           (0x1 << 1)      /* W1C */
 137 #define MSDC_INT_ACMDRDY        (0x1 << 3)      /* W1C */
 138 #define MSDC_INT_ACMDTMO        (0x1 << 4)      /* W1C */
 139 #define MSDC_INT_ACMDCRCERR     (0x1 << 5)      /* W1C */
 140 #define MSDC_INT_DMAQ_EMPTY     (0x1 << 6)      /* W1C */
 141 #define MSDC_INT_SDIOIRQ        (0x1 << 7)      /* W1C */
 142 #define MSDC_INT_CMDRDY         (0x1 << 8)      /* W1C */
 143 #define MSDC_INT_CMDTMO         (0x1 << 9)      /* W1C */
 144 #define MSDC_INT_RSPCRCERR      (0x1 << 10)     /* W1C */
 145 #define MSDC_INT_CSTA           (0x1 << 11)     /* R */
 146 #define MSDC_INT_XFER_COMPL     (0x1 << 12)     /* W1C */
 147 #define MSDC_INT_DXFER_DONE     (0x1 << 13)     /* W1C */
 148 #define MSDC_INT_DATTMO         (0x1 << 14)     /* W1C */
 149 #define MSDC_INT_DATCRCERR      (0x1 << 15)     /* W1C */
 150 #define MSDC_INT_ACMD19_DONE    (0x1 << 16)     /* W1C */
 151 #define MSDC_INT_DMA_BDCSERR    (0x1 << 17)     /* W1C */
 152 #define MSDC_INT_DMA_GPDCSERR   (0x1 << 18)     /* W1C */
 153 #define MSDC_INT_DMA_PROTECT    (0x1 << 19)     /* W1C */
 154 
 155 /* MSDC_INTEN mask */
 156 #define MSDC_INTEN_MMCIRQ       (0x1 << 0)      /* RW */
 157 #define MSDC_INTEN_CDSC         (0x1 << 1)      /* RW */
 158 #define MSDC_INTEN_ACMDRDY      (0x1 << 3)      /* RW */
 159 #define MSDC_INTEN_ACMDTMO      (0x1 << 4)      /* RW */
 160 #define MSDC_INTEN_ACMDCRCERR   (0x1 << 5)      /* RW */
 161 #define MSDC_INTEN_DMAQ_EMPTY   (0x1 << 6)      /* RW */
 162 #define MSDC_INTEN_SDIOIRQ      (0x1 << 7)      /* RW */
 163 #define MSDC_INTEN_CMDRDY       (0x1 << 8)      /* RW */
 164 #define MSDC_INTEN_CMDTMO       (0x1 << 9)      /* RW */
 165 #define MSDC_INTEN_RSPCRCERR    (0x1 << 10)     /* RW */
 166 #define MSDC_INTEN_CSTA         (0x1 << 11)     /* RW */
 167 #define MSDC_INTEN_XFER_COMPL   (0x1 << 12)     /* RW */
 168 #define MSDC_INTEN_DXFER_DONE   (0x1 << 13)     /* RW */
 169 #define MSDC_INTEN_DATTMO       (0x1 << 14)     /* RW */
 170 #define MSDC_INTEN_DATCRCERR    (0x1 << 15)     /* RW */
 171 #define MSDC_INTEN_ACMD19_DONE  (0x1 << 16)     /* RW */
 172 #define MSDC_INTEN_DMA_BDCSERR  (0x1 << 17)     /* RW */
 173 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18)     /* RW */
 174 #define MSDC_INTEN_DMA_PROTECT  (0x1 << 19)     /* RW */
 175 
 176 /* MSDC_FIFOCS mask */
 177 #define MSDC_FIFOCS_RXCNT       (0xff << 0)     /* R */
 178 #define MSDC_FIFOCS_TXCNT       (0xff << 16)    /* R */
 179 #define MSDC_FIFOCS_CLR         (0x1 << 31)     /* RW */
 180 
 181 /* SDC_CFG mask */
 182 #define SDC_CFG_SDIOINTWKUP     (0x1 << 0)      /* RW */
 183 #define SDC_CFG_INSWKUP         (0x1 << 1)      /* RW */
 184 #define SDC_CFG_BUSWIDTH        (0x3 << 16)     /* RW */
 185 #define SDC_CFG_SDIO            (0x1 << 19)     /* RW */
 186 #define SDC_CFG_SDIOIDE         (0x1 << 20)     /* RW */
 187 #define SDC_CFG_INTATGAP        (0x1 << 21)     /* RW */
 188 #define SDC_CFG_DTOC            (0xff << 24)    /* RW */
 189 
 190 /* SDC_STS mask */
 191 #define SDC_STS_SDCBUSY         (0x1 << 0)      /* RW */
 192 #define SDC_STS_CMDBUSY         (0x1 << 1)      /* RW */
 193 #define SDC_STS_SWR_COMPL       (0x1 << 31)     /* RW */
 194 
 195 #define SDC_DAT1_IRQ_TRIGGER    (0x1 << 19)     /* RW */
 196 /* SDC_ADV_CFG0 mask */
 197 #define SDC_RX_ENHANCE_EN       (0x1 << 20)     /* RW */
 198 
 199 /* DMA_SA_H4BIT mask */
 200 #define DMA_ADDR_HIGH_4BIT      (0xf << 0)      /* RW */
 201 
 202 /* MSDC_DMA_CTRL mask */
 203 #define MSDC_DMA_CTRL_START     (0x1 << 0)      /* W */
 204 #define MSDC_DMA_CTRL_STOP      (0x1 << 1)      /* W */
 205 #define MSDC_DMA_CTRL_RESUME    (0x1 << 2)      /* W */
 206 #define MSDC_DMA_CTRL_MODE      (0x1 << 8)      /* RW */
 207 #define MSDC_DMA_CTRL_LASTBUF   (0x1 << 10)     /* RW */
 208 #define MSDC_DMA_CTRL_BRUSTSZ   (0x7 << 12)     /* RW */
 209 
 210 /* MSDC_DMA_CFG mask */
 211 #define MSDC_DMA_CFG_STS        (0x1 << 0)      /* R */
 212 #define MSDC_DMA_CFG_DECSEN     (0x1 << 1)      /* RW */
 213 #define MSDC_DMA_CFG_AHBHPROT2  (0x2 << 8)      /* RW */
 214 #define MSDC_DMA_CFG_ACTIVEEN   (0x2 << 12)     /* RW */
 215 #define MSDC_DMA_CFG_CS12B16B   (0x1 << 16)     /* RW */
 216 
 217 /* MSDC_PATCH_BIT mask */
 218 #define MSDC_PATCH_BIT_ODDSUPP    (0x1 <<  1)   /* RW */
 219 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 <<  7)
 220 #define MSDC_CKGEN_MSDC_DLY_SEL   (0x1f << 10)
 221 #define MSDC_PATCH_BIT_IODSSEL    (0x1 << 16)   /* RW */
 222 #define MSDC_PATCH_BIT_IOINTSEL   (0x1 << 17)   /* RW */
 223 #define MSDC_PATCH_BIT_BUSYDLY    (0xf << 18)   /* RW */
 224 #define MSDC_PATCH_BIT_WDOD       (0xf << 22)   /* RW */
 225 #define MSDC_PATCH_BIT_IDRTSEL    (0x1 << 26)   /* RW */
 226 #define MSDC_PATCH_BIT_CMDFSEL    (0x1 << 27)   /* RW */
 227 #define MSDC_PATCH_BIT_INTDLSEL   (0x1 << 28)   /* RW */
 228 #define MSDC_PATCH_BIT_SPCPUSH    (0x1 << 29)   /* RW */
 229 #define MSDC_PATCH_BIT_DECRCTMO   (0x1 << 30)   /* RW */
 230 
 231 #define MSDC_PATCH_BIT1_CMDTA     (0x7 << 3)    /* RW */
 232 #define MSDC_PATCH_BIT1_STOP_DLY  (0xf << 8)    /* RW */
 233 
 234 #define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
 235 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28)   /* RW */
 236 #define MSDC_PB2_SUPPORT_64G      (0x1 << 1)    /* RW */
 237 #define MSDC_PB2_RESPWAIT         (0x3 << 2)    /* RW */
 238 #define MSDC_PB2_RESPSTSENSEL     (0x7 << 16)   /* RW */
 239 #define MSDC_PB2_CRCSTSENSEL      (0x7 << 29)   /* RW */
 240 
 241 #define MSDC_PAD_TUNE_DATWRDLY    (0x1f <<  0)  /* RW */
 242 #define MSDC_PAD_TUNE_DATRRDLY    (0x1f <<  8)  /* RW */
 243 #define MSDC_PAD_TUNE_CMDRDLY     (0x1f << 16)  /* RW */
 244 #define MSDC_PAD_TUNE_CMDRRDLY    (0x1f << 22)  /* RW */
 245 #define MSDC_PAD_TUNE_CLKTDLY     (0x1f << 27)  /* RW */
 246 #define MSDC_PAD_TUNE_RXDLYSEL    (0x1 << 15)   /* RW */
 247 #define MSDC_PAD_TUNE_RD_SEL      (0x1 << 13)   /* RW */
 248 #define MSDC_PAD_TUNE_CMD_SEL     (0x1 << 21)   /* RW */
 249 
 250 #define PAD_DS_TUNE_DLY1          (0x1f << 2)   /* RW */
 251 #define PAD_DS_TUNE_DLY2          (0x1f << 7)   /* RW */
 252 #define PAD_DS_TUNE_DLY3          (0x1f << 12)  /* RW */
 253 
 254 #define PAD_CMD_TUNE_RX_DLY3      (0x1f << 1)  /* RW */
 255 
 256 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0)   /* RW */
 257 #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
 258 #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
 259 
 260 #define EMMC50_CFG3_OUTS_WR       (0x1f << 0)  /* RW */
 261 
 262 #define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
 263 #define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
 264 
 265 /* EMMC_TOP_CONTROL mask */
 266 #define PAD_RXDLY_SEL           (0x1 << 0)      /* RW */
 267 #define DELAY_EN                (0x1 << 1)      /* RW */
 268 #define PAD_DAT_RD_RXDLY2       (0x1f << 2)     /* RW */
 269 #define PAD_DAT_RD_RXDLY        (0x1f << 7)     /* RW */
 270 #define PAD_DAT_RD_RXDLY2_SEL   (0x1 << 12)     /* RW */
 271 #define PAD_DAT_RD_RXDLY_SEL    (0x1 << 13)     /* RW */
 272 #define DATA_K_VALUE_SEL        (0x1 << 14)     /* RW */
 273 #define SDC_RX_ENH_EN           (0x1 << 15)     /* TW */
 274 
 275 /* EMMC_TOP_CMD mask */
 276 #define PAD_CMD_RXDLY2          (0x1f << 0)     /* RW */
 277 #define PAD_CMD_RXDLY           (0x1f << 5)     /* RW */
 278 #define PAD_CMD_RD_RXDLY2_SEL   (0x1 << 10)     /* RW */
 279 #define PAD_CMD_RD_RXDLY_SEL    (0x1 << 11)     /* RW */
 280 #define PAD_CMD_TX_DLY          (0x1f << 12)    /* RW */
 281 
 282 #define REQ_CMD_EIO  (0x1 << 0)
 283 #define REQ_CMD_TMO  (0x1 << 1)
 284 #define REQ_DAT_ERR  (0x1 << 2)
 285 #define REQ_STOP_EIO (0x1 << 3)
 286 #define REQ_STOP_TMO (0x1 << 4)
 287 #define REQ_CMD_BUSY (0x1 << 5)
 288 
 289 #define MSDC_PREPARE_FLAG (0x1 << 0)
 290 #define MSDC_ASYNC_FLAG (0x1 << 1)
 291 #define MSDC_MMAP_FLAG (0x1 << 2)
 292 
 293 #define MTK_MMC_AUTOSUSPEND_DELAY       50
 294 #define CMD_TIMEOUT         (HZ/10 * 5) /* 100ms x5 */
 295 #define DAT_TIMEOUT         (HZ    * 5) /* 1000ms x5 */
 296 
 297 #define DEFAULT_DEBOUNCE        (8)     /* 8 cycles CD debounce */
 298 
 299 #define PAD_DELAY_MAX   32 /* PAD delay cells */
 300 /*--------------------------------------------------------------------------*/
 301 /* Descriptor Structure                                                     */
 302 /*--------------------------------------------------------------------------*/
 303 struct mt_gpdma_desc {
 304         u32 gpd_info;
 305 #define GPDMA_DESC_HWO          (0x1 << 0)
 306 #define GPDMA_DESC_BDP          (0x1 << 1)
 307 #define GPDMA_DESC_CHECKSUM     (0xff << 8) /* bit8 ~ bit15 */
 308 #define GPDMA_DESC_INT          (0x1 << 16)
 309 #define GPDMA_DESC_NEXT_H4      (0xf << 24)
 310 #define GPDMA_DESC_PTR_H4       (0xf << 28)
 311         u32 next;
 312         u32 ptr;
 313         u32 gpd_data_len;
 314 #define GPDMA_DESC_BUFLEN       (0xffff) /* bit0 ~ bit15 */
 315 #define GPDMA_DESC_EXTLEN       (0xff << 16) /* bit16 ~ bit23 */
 316         u32 arg;
 317         u32 blknum;
 318         u32 cmd;
 319 };
 320 
 321 struct mt_bdma_desc {
 322         u32 bd_info;
 323 #define BDMA_DESC_EOL           (0x1 << 0)
 324 #define BDMA_DESC_CHECKSUM      (0xff << 8) /* bit8 ~ bit15 */
 325 #define BDMA_DESC_BLKPAD        (0x1 << 17)
 326 #define BDMA_DESC_DWPAD         (0x1 << 18)
 327 #define BDMA_DESC_NEXT_H4       (0xf << 24)
 328 #define BDMA_DESC_PTR_H4        (0xf << 28)
 329         u32 next;
 330         u32 ptr;
 331         u32 bd_data_len;
 332 #define BDMA_DESC_BUFLEN        (0xffff) /* bit0 ~ bit15 */
 333 #define BDMA_DESC_BUFLEN_EXT    (0xffffff) /* bit0 ~ bit23 */
 334 };
 335 
 336 struct msdc_dma {
 337         struct scatterlist *sg; /* I/O scatter list */
 338         struct mt_gpdma_desc *gpd;              /* pointer to gpd array */
 339         struct mt_bdma_desc *bd;                /* pointer to bd array */
 340         dma_addr_t gpd_addr;    /* the physical address of gpd array */
 341         dma_addr_t bd_addr;     /* the physical address of bd array */
 342 };
 343 
 344 struct msdc_save_para {
 345         u32 msdc_cfg;
 346         u32 iocon;
 347         u32 sdc_cfg;
 348         u32 pad_tune;
 349         u32 patch_bit0;
 350         u32 patch_bit1;
 351         u32 patch_bit2;
 352         u32 pad_ds_tune;
 353         u32 pad_cmd_tune;
 354         u32 emmc50_cfg0;
 355         u32 emmc50_cfg3;
 356         u32 sdc_fifo_cfg;
 357         u32 emmc_top_control;
 358         u32 emmc_top_cmd;
 359         u32 emmc50_pad_ds_tune;
 360 };
 361 
 362 struct mtk_mmc_compatible {
 363         u8 clk_div_bits;
 364         bool hs400_tune; /* only used for MT8173 */
 365         u32 pad_tune_reg;
 366         bool async_fifo;
 367         bool data_tune;
 368         bool busy_check;
 369         bool stop_clk_fix;
 370         bool enhance_rx;
 371         bool support_64g;
 372         bool use_internal_cd;
 373 };
 374 
 375 struct msdc_tune_para {
 376         u32 iocon;
 377         u32 pad_tune;
 378         u32 pad_cmd_tune;
 379         u32 emmc_top_control;
 380         u32 emmc_top_cmd;
 381 };
 382 
 383 struct msdc_delay_phase {
 384         u8 maxlen;
 385         u8 start;
 386         u8 final_phase;
 387 };
 388 
 389 struct msdc_host {
 390         struct device *dev;
 391         const struct mtk_mmc_compatible *dev_comp;
 392         struct mmc_host *mmc;   /* mmc structure */
 393         int cmd_rsp;
 394 
 395         spinlock_t lock;
 396         struct mmc_request *mrq;
 397         struct mmc_command *cmd;
 398         struct mmc_data *data;
 399         int error;
 400 
 401         void __iomem *base;             /* host base address */
 402         void __iomem *top_base;         /* host top register base address */
 403 
 404         struct msdc_dma dma;    /* dma channel */
 405         u64 dma_mask;
 406 
 407         u32 timeout_ns;         /* data timeout ns */
 408         u32 timeout_clks;       /* data timeout clks */
 409 
 410         struct pinctrl *pinctrl;
 411         struct pinctrl_state *pins_default;
 412         struct pinctrl_state *pins_uhs;
 413         struct delayed_work req_timeout;
 414         int irq;                /* host interrupt */
 415 
 416         struct clk *src_clk;    /* msdc source clock */
 417         struct clk *h_clk;      /* msdc h_clk */
 418         struct clk *bus_clk;    /* bus clock which used to access register */
 419         struct clk *src_clk_cg; /* msdc source clock control gate */
 420         u32 mclk;               /* mmc subsystem clock frequency */
 421         u32 src_clk_freq;       /* source clock frequency */
 422         unsigned char timing;
 423         bool vqmmc_enabled;
 424         u32 latch_ck;
 425         u32 hs400_ds_delay;
 426         u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
 427         u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
 428         bool hs400_cmd_resp_sel_rising;
 429                                  /* cmd response sample selection for HS400 */
 430         bool hs400_mode;        /* current eMMC will run at hs400 mode */
 431         bool internal_cd;       /* Use internal card-detect logic */
 432         struct msdc_save_para save_para; /* used when gate HCLK */
 433         struct msdc_tune_para def_tune_para; /* default tune setting */
 434         struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
 435 };
 436 
 437 static const struct mtk_mmc_compatible mt8135_compat = {
 438         .clk_div_bits = 8,
 439         .hs400_tune = false,
 440         .pad_tune_reg = MSDC_PAD_TUNE,
 441         .async_fifo = false,
 442         .data_tune = false,
 443         .busy_check = false,
 444         .stop_clk_fix = false,
 445         .enhance_rx = false,
 446         .support_64g = false,
 447 };
 448 
 449 static const struct mtk_mmc_compatible mt8173_compat = {
 450         .clk_div_bits = 8,
 451         .hs400_tune = true,
 452         .pad_tune_reg = MSDC_PAD_TUNE,
 453         .async_fifo = false,
 454         .data_tune = false,
 455         .busy_check = false,
 456         .stop_clk_fix = false,
 457         .enhance_rx = false,
 458         .support_64g = false,
 459 };
 460 
 461 static const struct mtk_mmc_compatible mt8183_compat = {
 462         .clk_div_bits = 12,
 463         .hs400_tune = false,
 464         .pad_tune_reg = MSDC_PAD_TUNE0,
 465         .async_fifo = true,
 466         .data_tune = true,
 467         .busy_check = true,
 468         .stop_clk_fix = true,
 469         .enhance_rx = true,
 470         .support_64g = true,
 471 };
 472 
 473 static const struct mtk_mmc_compatible mt2701_compat = {
 474         .clk_div_bits = 12,
 475         .hs400_tune = false,
 476         .pad_tune_reg = MSDC_PAD_TUNE0,
 477         .async_fifo = true,
 478         .data_tune = true,
 479         .busy_check = false,
 480         .stop_clk_fix = false,
 481         .enhance_rx = false,
 482         .support_64g = false,
 483 };
 484 
 485 static const struct mtk_mmc_compatible mt2712_compat = {
 486         .clk_div_bits = 12,
 487         .hs400_tune = false,
 488         .pad_tune_reg = MSDC_PAD_TUNE0,
 489         .async_fifo = true,
 490         .data_tune = true,
 491         .busy_check = true,
 492         .stop_clk_fix = true,
 493         .enhance_rx = true,
 494         .support_64g = true,
 495 };
 496 
 497 static const struct mtk_mmc_compatible mt7622_compat = {
 498         .clk_div_bits = 12,
 499         .hs400_tune = false,
 500         .pad_tune_reg = MSDC_PAD_TUNE0,
 501         .async_fifo = true,
 502         .data_tune = true,
 503         .busy_check = true,
 504         .stop_clk_fix = true,
 505         .enhance_rx = true,
 506         .support_64g = false,
 507 };
 508 
 509 static const struct mtk_mmc_compatible mt8516_compat = {
 510         .clk_div_bits = 12,
 511         .hs400_tune = false,
 512         .pad_tune_reg = MSDC_PAD_TUNE0,
 513         .async_fifo = true,
 514         .data_tune = true,
 515         .busy_check = true,
 516         .stop_clk_fix = true,
 517 };
 518 
 519 static const struct mtk_mmc_compatible mt7620_compat = {
 520         .clk_div_bits = 8,
 521         .hs400_tune = false,
 522         .pad_tune_reg = MSDC_PAD_TUNE,
 523         .async_fifo = false,
 524         .data_tune = false,
 525         .busy_check = false,
 526         .stop_clk_fix = false,
 527         .enhance_rx = false,
 528         .use_internal_cd = true,
 529 };
 530 
 531 static const struct of_device_id msdc_of_ids[] = {
 532         { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
 533         { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
 534         { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
 535         { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
 536         { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
 537         { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
 538         { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
 539         { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
 540         {}
 541 };
 542 MODULE_DEVICE_TABLE(of, msdc_of_ids);
 543 
 544 static void sdr_set_bits(void __iomem *reg, u32 bs)
 545 {
 546         u32 val = readl(reg);
 547 
 548         val |= bs;
 549         writel(val, reg);
 550 }
 551 
 552 static void sdr_clr_bits(void __iomem *reg, u32 bs)
 553 {
 554         u32 val = readl(reg);
 555 
 556         val &= ~bs;
 557         writel(val, reg);
 558 }
 559 
 560 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
 561 {
 562         unsigned int tv = readl(reg);
 563 
 564         tv &= ~field;
 565         tv |= ((val) << (ffs((unsigned int)field) - 1));
 566         writel(tv, reg);
 567 }
 568 
 569 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
 570 {
 571         unsigned int tv = readl(reg);
 572 
 573         *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
 574 }
 575 
 576 static void msdc_reset_hw(struct msdc_host *host)
 577 {
 578         u32 val;
 579 
 580         sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
 581         while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
 582                 cpu_relax();
 583 
 584         sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
 585         while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
 586                 cpu_relax();
 587 
 588         val = readl(host->base + MSDC_INT);
 589         writel(val, host->base + MSDC_INT);
 590 }
 591 
 592 static void msdc_cmd_next(struct msdc_host *host,
 593                 struct mmc_request *mrq, struct mmc_command *cmd);
 594 
 595 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
 596                         MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
 597                         MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
 598 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
 599                         MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
 600                         MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
 601 
 602 static u8 msdc_dma_calcs(u8 *buf, u32 len)
 603 {
 604         u32 i, sum = 0;
 605 
 606         for (i = 0; i < len; i++)
 607                 sum += buf[i];
 608         return 0xff - (u8) sum;
 609 }
 610 
 611 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
 612                 struct mmc_data *data)
 613 {
 614         unsigned int j, dma_len;
 615         dma_addr_t dma_address;
 616         u32 dma_ctrl;
 617         struct scatterlist *sg;
 618         struct mt_gpdma_desc *gpd;
 619         struct mt_bdma_desc *bd;
 620 
 621         sg = data->sg;
 622 
 623         gpd = dma->gpd;
 624         bd = dma->bd;
 625 
 626         /* modify gpd */
 627         gpd->gpd_info |= GPDMA_DESC_HWO;
 628         gpd->gpd_info |= GPDMA_DESC_BDP;
 629         /* need to clear first. use these bits to calc checksum */
 630         gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
 631         gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
 632 
 633         /* modify bd */
 634         for_each_sg(data->sg, sg, data->sg_count, j) {
 635                 dma_address = sg_dma_address(sg);
 636                 dma_len = sg_dma_len(sg);
 637 
 638                 /* init bd */
 639                 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
 640                 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
 641                 bd[j].ptr = lower_32_bits(dma_address);
 642                 if (host->dev_comp->support_64g) {
 643                         bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
 644                         bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
 645                                          << 28;
 646                 }
 647 
 648                 if (host->dev_comp->support_64g) {
 649                         bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
 650                         bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
 651                 } else {
 652                         bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
 653                         bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
 654                 }
 655 
 656                 if (j == data->sg_count - 1) /* the last bd */
 657                         bd[j].bd_info |= BDMA_DESC_EOL;
 658                 else
 659                         bd[j].bd_info &= ~BDMA_DESC_EOL;
 660 
 661                 /* checksume need to clear first */
 662                 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
 663                 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
 664         }
 665 
 666         sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
 667         dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
 668         dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
 669         dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
 670         writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
 671         if (host->dev_comp->support_64g)
 672                 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
 673                               upper_32_bits(dma->gpd_addr) & 0xf);
 674         writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
 675 }
 676 
 677 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
 678 {
 679         struct mmc_data *data = mrq->data;
 680 
 681         if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
 682                 data->host_cookie |= MSDC_PREPARE_FLAG;
 683                 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
 684                                             mmc_get_dma_dir(data));
 685         }
 686 }
 687 
 688 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
 689 {
 690         struct mmc_data *data = mrq->data;
 691 
 692         if (data->host_cookie & MSDC_ASYNC_FLAG)
 693                 return;
 694 
 695         if (data->host_cookie & MSDC_PREPARE_FLAG) {
 696                 dma_unmap_sg(host->dev, data->sg, data->sg_len,
 697                              mmc_get_dma_dir(data));
 698                 data->host_cookie &= ~MSDC_PREPARE_FLAG;
 699         }
 700 }
 701 
 702 /* clock control primitives */
 703 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
 704 {
 705         u32 timeout, clk_ns;
 706         u32 mode = 0;
 707 
 708         host->timeout_ns = ns;
 709         host->timeout_clks = clks;
 710         if (host->mmc->actual_clock == 0) {
 711                 timeout = 0;
 712         } else {
 713                 clk_ns  = 1000000000UL / host->mmc->actual_clock;
 714                 timeout = (ns + clk_ns - 1) / clk_ns + clks;
 715                 /* in 1048576 sclk cycle unit */
 716                 timeout = (timeout + (0x1 << 20) - 1) >> 20;
 717                 if (host->dev_comp->clk_div_bits == 8)
 718                         sdr_get_field(host->base + MSDC_CFG,
 719                                       MSDC_CFG_CKMOD, &mode);
 720                 else
 721                         sdr_get_field(host->base + MSDC_CFG,
 722                                       MSDC_CFG_CKMOD_EXTRA, &mode);
 723                 /*DDR mode will double the clk cycles for data timeout */
 724                 timeout = mode >= 2 ? timeout * 2 : timeout;
 725                 timeout = timeout > 1 ? timeout - 1 : 0;
 726                 timeout = timeout > 255 ? 255 : timeout;
 727         }
 728         sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
 729 }
 730 
 731 static void msdc_gate_clock(struct msdc_host *host)
 732 {
 733         clk_disable_unprepare(host->src_clk_cg);
 734         clk_disable_unprepare(host->src_clk);
 735         clk_disable_unprepare(host->bus_clk);
 736         clk_disable_unprepare(host->h_clk);
 737 }
 738 
 739 static void msdc_ungate_clock(struct msdc_host *host)
 740 {
 741         clk_prepare_enable(host->h_clk);
 742         clk_prepare_enable(host->bus_clk);
 743         clk_prepare_enable(host->src_clk);
 744         clk_prepare_enable(host->src_clk_cg);
 745         while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
 746                 cpu_relax();
 747 }
 748 
 749 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
 750 {
 751         u32 mode;
 752         u32 flags;
 753         u32 div;
 754         u32 sclk;
 755         u32 tune_reg = host->dev_comp->pad_tune_reg;
 756 
 757         if (!hz) {
 758                 dev_dbg(host->dev, "set mclk to 0\n");
 759                 host->mclk = 0;
 760                 host->mmc->actual_clock = 0;
 761                 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 762                 return;
 763         }
 764 
 765         flags = readl(host->base + MSDC_INTEN);
 766         sdr_clr_bits(host->base + MSDC_INTEN, flags);
 767         if (host->dev_comp->clk_div_bits == 8)
 768                 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
 769         else
 770                 sdr_clr_bits(host->base + MSDC_CFG,
 771                              MSDC_CFG_HS400_CK_MODE_EXTRA);
 772         if (timing == MMC_TIMING_UHS_DDR50 ||
 773             timing == MMC_TIMING_MMC_DDR52 ||
 774             timing == MMC_TIMING_MMC_HS400) {
 775                 if (timing == MMC_TIMING_MMC_HS400)
 776                         mode = 0x3;
 777                 else
 778                         mode = 0x2; /* ddr mode and use divisor */
 779 
 780                 if (hz >= (host->src_clk_freq >> 2)) {
 781                         div = 0; /* mean div = 1/4 */
 782                         sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
 783                 } else {
 784                         div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
 785                         sclk = (host->src_clk_freq >> 2) / div;
 786                         div = (div >> 1);
 787                 }
 788 
 789                 if (timing == MMC_TIMING_MMC_HS400 &&
 790                     hz >= (host->src_clk_freq >> 1)) {
 791                         if (host->dev_comp->clk_div_bits == 8)
 792                                 sdr_set_bits(host->base + MSDC_CFG,
 793                                              MSDC_CFG_HS400_CK_MODE);
 794                         else
 795                                 sdr_set_bits(host->base + MSDC_CFG,
 796                                              MSDC_CFG_HS400_CK_MODE_EXTRA);
 797                         sclk = host->src_clk_freq >> 1;
 798                         div = 0; /* div is ignore when bit18 is set */
 799                 }
 800         } else if (hz >= host->src_clk_freq) {
 801                 mode = 0x1; /* no divisor */
 802                 div = 0;
 803                 sclk = host->src_clk_freq;
 804         } else {
 805                 mode = 0x0; /* use divisor */
 806                 if (hz >= (host->src_clk_freq >> 1)) {
 807                         div = 0; /* mean div = 1/2 */
 808                         sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
 809                 } else {
 810                         div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
 811                         sclk = (host->src_clk_freq >> 2) / div;
 812                 }
 813         }
 814         sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 815         /*
 816          * As src_clk/HCLK use the same bit to gate/ungate,
 817          * So if want to only gate src_clk, need gate its parent(mux).
 818          */
 819         if (host->src_clk_cg)
 820                 clk_disable_unprepare(host->src_clk_cg);
 821         else
 822                 clk_disable_unprepare(clk_get_parent(host->src_clk));
 823         if (host->dev_comp->clk_div_bits == 8)
 824                 sdr_set_field(host->base + MSDC_CFG,
 825                               MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
 826                               (mode << 8) | div);
 827         else
 828                 sdr_set_field(host->base + MSDC_CFG,
 829                               MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
 830                               (mode << 12) | div);
 831         if (host->src_clk_cg)
 832                 clk_prepare_enable(host->src_clk_cg);
 833         else
 834                 clk_prepare_enable(clk_get_parent(host->src_clk));
 835 
 836         while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
 837                 cpu_relax();
 838         sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 839         host->mmc->actual_clock = sclk;
 840         host->mclk = hz;
 841         host->timing = timing;
 842         /* need because clk changed. */
 843         msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
 844         sdr_set_bits(host->base + MSDC_INTEN, flags);
 845 
 846         /*
 847          * mmc_select_hs400() will drop to 50Mhz and High speed mode,
 848          * tune result of hs200/200Mhz is not suitable for 50Mhz
 849          */
 850         if (host->mmc->actual_clock <= 52000000) {
 851                 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
 852                 if (host->top_base) {
 853                         writel(host->def_tune_para.emmc_top_control,
 854                                host->top_base + EMMC_TOP_CONTROL);
 855                         writel(host->def_tune_para.emmc_top_cmd,
 856                                host->top_base + EMMC_TOP_CMD);
 857                 } else {
 858                         writel(host->def_tune_para.pad_tune,
 859                                host->base + tune_reg);
 860                 }
 861         } else {
 862                 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
 863                 writel(host->saved_tune_para.pad_cmd_tune,
 864                        host->base + PAD_CMD_TUNE);
 865                 if (host->top_base) {
 866                         writel(host->saved_tune_para.emmc_top_control,
 867                                host->top_base + EMMC_TOP_CONTROL);
 868                         writel(host->saved_tune_para.emmc_top_cmd,
 869                                host->top_base + EMMC_TOP_CMD);
 870                 } else {
 871                         writel(host->saved_tune_para.pad_tune,
 872                                host->base + tune_reg);
 873                 }
 874         }
 875 
 876         if (timing == MMC_TIMING_MMC_HS400 &&
 877             host->dev_comp->hs400_tune)
 878                 sdr_set_field(host->base + tune_reg,
 879                               MSDC_PAD_TUNE_CMDRRDLY,
 880                               host->hs400_cmd_int_delay);
 881         dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock,
 882                 timing);
 883 }
 884 
 885 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
 886                 struct mmc_request *mrq, struct mmc_command *cmd)
 887 {
 888         u32 resp;
 889 
 890         switch (mmc_resp_type(cmd)) {
 891                 /* Actually, R1, R5, R6, R7 are the same */
 892         case MMC_RSP_R1:
 893                 resp = 0x1;
 894                 break;
 895         case MMC_RSP_R1B:
 896                 resp = 0x7;
 897                 break;
 898         case MMC_RSP_R2:
 899                 resp = 0x2;
 900                 break;
 901         case MMC_RSP_R3:
 902                 resp = 0x3;
 903                 break;
 904         case MMC_RSP_NONE:
 905         default:
 906                 resp = 0x0;
 907                 break;
 908         }
 909 
 910         return resp;
 911 }
 912 
 913 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
 914                 struct mmc_request *mrq, struct mmc_command *cmd)
 915 {
 916         /* rawcmd :
 917          * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
 918          * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
 919          */
 920         u32 opcode = cmd->opcode;
 921         u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
 922         u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
 923 
 924         host->cmd_rsp = resp;
 925 
 926         if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
 927             opcode == MMC_STOP_TRANSMISSION)
 928                 rawcmd |= (0x1 << 14);
 929         else if (opcode == SD_SWITCH_VOLTAGE)
 930                 rawcmd |= (0x1 << 30);
 931         else if (opcode == SD_APP_SEND_SCR ||
 932                  opcode == SD_APP_SEND_NUM_WR_BLKS ||
 933                  (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
 934                  (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
 935                  (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
 936                 rawcmd |= (0x1 << 11);
 937 
 938         if (cmd->data) {
 939                 struct mmc_data *data = cmd->data;
 940 
 941                 if (mmc_op_multi(opcode)) {
 942                         if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
 943                             !(mrq->sbc->arg & 0xFFFF0000))
 944                                 rawcmd |= 0x2 << 28; /* AutoCMD23 */
 945                 }
 946 
 947                 rawcmd |= ((data->blksz & 0xFFF) << 16);
 948                 if (data->flags & MMC_DATA_WRITE)
 949                         rawcmd |= (0x1 << 13);
 950                 if (data->blocks > 1)
 951                         rawcmd |= (0x2 << 11);
 952                 else
 953                         rawcmd |= (0x1 << 11);
 954                 /* Always use dma mode */
 955                 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
 956 
 957                 if (host->timeout_ns != data->timeout_ns ||
 958                     host->timeout_clks != data->timeout_clks)
 959                         msdc_set_timeout(host, data->timeout_ns,
 960                                         data->timeout_clks);
 961 
 962                 writel(data->blocks, host->base + SDC_BLK_NUM);
 963         }
 964         return rawcmd;
 965 }
 966 
 967 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
 968                             struct mmc_command *cmd, struct mmc_data *data)
 969 {
 970         bool read;
 971 
 972         WARN_ON(host->data);
 973         host->data = data;
 974         read = data->flags & MMC_DATA_READ;
 975 
 976         mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
 977         msdc_dma_setup(host, &host->dma, data);
 978         sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
 979         sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
 980         dev_dbg(host->dev, "DMA start\n");
 981         dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
 982                         __func__, cmd->opcode, data->blocks, read);
 983 }
 984 
 985 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
 986                 struct mmc_command *cmd)
 987 {
 988         u32 *rsp = cmd->resp;
 989 
 990         rsp[0] = readl(host->base + SDC_ACMD_RESP);
 991 
 992         if (events & MSDC_INT_ACMDRDY) {
 993                 cmd->error = 0;
 994         } else {
 995                 msdc_reset_hw(host);
 996                 if (events & MSDC_INT_ACMDCRCERR) {
 997                         cmd->error = -EILSEQ;
 998                         host->error |= REQ_STOP_EIO;
 999                 } else if (events & MSDC_INT_ACMDTMO) {
1000                         cmd->error = -ETIMEDOUT;
1001                         host->error |= REQ_STOP_TMO;
1002                 }
1003                 dev_err(host->dev,
1004                         "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1005                         __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1006         }
1007         return cmd->error;
1008 }
1009 
1010 static void msdc_track_cmd_data(struct msdc_host *host,
1011                                 struct mmc_command *cmd, struct mmc_data *data)
1012 {
1013         if (host->error)
1014                 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1015                         __func__, cmd->opcode, cmd->arg, host->error);
1016 }
1017 
1018 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1019 {
1020         unsigned long flags;
1021         bool ret;
1022 
1023         ret = cancel_delayed_work(&host->req_timeout);
1024         if (!ret) {
1025                 /* delay work already running */
1026                 return;
1027         }
1028         spin_lock_irqsave(&host->lock, flags);
1029         host->mrq = NULL;
1030         spin_unlock_irqrestore(&host->lock, flags);
1031 
1032         msdc_track_cmd_data(host, mrq->cmd, mrq->data);
1033         if (mrq->data)
1034                 msdc_unprepare_data(host, mrq);
1035         if (host->error)
1036                 msdc_reset_hw(host);
1037         mmc_request_done(host->mmc, mrq);
1038 }
1039 
1040 /* returns true if command is fully handled; returns false otherwise */
1041 static bool msdc_cmd_done(struct msdc_host *host, int events,
1042                           struct mmc_request *mrq, struct mmc_command *cmd)
1043 {
1044         bool done = false;
1045         bool sbc_error;
1046         unsigned long flags;
1047         u32 *rsp = cmd->resp;
1048 
1049         if (mrq->sbc && cmd == mrq->cmd &&
1050             (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1051                                    | MSDC_INT_ACMDTMO)))
1052                 msdc_auto_cmd_done(host, events, mrq->sbc);
1053 
1054         sbc_error = mrq->sbc && mrq->sbc->error;
1055 
1056         if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1057                                         | MSDC_INT_RSPCRCERR
1058                                         | MSDC_INT_CMDTMO)))
1059                 return done;
1060 
1061         spin_lock_irqsave(&host->lock, flags);
1062         done = !host->cmd;
1063         host->cmd = NULL;
1064         spin_unlock_irqrestore(&host->lock, flags);
1065 
1066         if (done)
1067                 return true;
1068 
1069         sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1070 
1071         if (cmd->flags & MMC_RSP_PRESENT) {
1072                 if (cmd->flags & MMC_RSP_136) {
1073                         rsp[0] = readl(host->base + SDC_RESP3);
1074                         rsp[1] = readl(host->base + SDC_RESP2);
1075                         rsp[2] = readl(host->base + SDC_RESP1);
1076                         rsp[3] = readl(host->base + SDC_RESP0);
1077                 } else {
1078                         rsp[0] = readl(host->base + SDC_RESP0);
1079                 }
1080         }
1081 
1082         if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1083                 if (events & MSDC_INT_CMDTMO ||
1084                     (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
1085                      cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1086                         /*
1087                          * should not clear fifo/interrupt as the tune data
1088                          * may have alreay come when cmd19/cmd21 gets response
1089                          * CRC error.
1090                          */
1091                         msdc_reset_hw(host);
1092                 if (events & MSDC_INT_RSPCRCERR) {
1093                         cmd->error = -EILSEQ;
1094                         host->error |= REQ_CMD_EIO;
1095                 } else if (events & MSDC_INT_CMDTMO) {
1096                         cmd->error = -ETIMEDOUT;
1097                         host->error |= REQ_CMD_TMO;
1098                 }
1099         }
1100         if (cmd->error)
1101                 dev_dbg(host->dev,
1102                                 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1103                                 __func__, cmd->opcode, cmd->arg, rsp[0],
1104                                 cmd->error);
1105 
1106         msdc_cmd_next(host, mrq, cmd);
1107         return true;
1108 }
1109 
1110 /* It is the core layer's responsibility to ensure card status
1111  * is correct before issue a request. but host design do below
1112  * checks recommended.
1113  */
1114 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1115                 struct mmc_request *mrq, struct mmc_command *cmd)
1116 {
1117         /* The max busy time we can endure is 20ms */
1118         unsigned long tmo = jiffies + msecs_to_jiffies(20);
1119 
1120         while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
1121                         time_before(jiffies, tmo))
1122                 cpu_relax();
1123         if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
1124                 dev_err(host->dev, "CMD bus busy detected\n");
1125                 host->error |= REQ_CMD_BUSY;
1126                 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1127                 return false;
1128         }
1129 
1130         if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1131                 tmo = jiffies + msecs_to_jiffies(20);
1132                 /* R1B or with data, should check SDCBUSY */
1133                 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1134                                 time_before(jiffies, tmo))
1135                         cpu_relax();
1136                 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1137                         dev_err(host->dev, "Controller busy detected\n");
1138                         host->error |= REQ_CMD_BUSY;
1139                         msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1140                         return false;
1141                 }
1142         }
1143         return true;
1144 }
1145 
1146 static void msdc_start_command(struct msdc_host *host,
1147                 struct mmc_request *mrq, struct mmc_command *cmd)
1148 {
1149         u32 rawcmd;
1150         unsigned long flags;
1151 
1152         WARN_ON(host->cmd);
1153         host->cmd = cmd;
1154 
1155         mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1156         if (!msdc_cmd_is_ready(host, mrq, cmd))
1157                 return;
1158 
1159         if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1160             readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1161                 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1162                 msdc_reset_hw(host);
1163         }
1164 
1165         cmd->error = 0;
1166         rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1167 
1168         spin_lock_irqsave(&host->lock, flags);
1169         sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1170         spin_unlock_irqrestore(&host->lock, flags);
1171 
1172         writel(cmd->arg, host->base + SDC_ARG);
1173         writel(rawcmd, host->base + SDC_CMD);
1174 }
1175 
1176 static void msdc_cmd_next(struct msdc_host *host,
1177                 struct mmc_request *mrq, struct mmc_command *cmd)
1178 {
1179         if ((cmd->error &&
1180             !(cmd->error == -EILSEQ &&
1181               (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1182                cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
1183             (mrq->sbc && mrq->sbc->error))
1184                 msdc_request_done(host, mrq);
1185         else if (cmd == mrq->sbc)
1186                 msdc_start_command(host, mrq, mrq->cmd);
1187         else if (!cmd->data)
1188                 msdc_request_done(host, mrq);
1189         else
1190                 msdc_start_data(host, mrq, cmd, cmd->data);
1191 }
1192 
1193 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1194 {
1195         struct msdc_host *host = mmc_priv(mmc);
1196 
1197         host->error = 0;
1198         WARN_ON(host->mrq);
1199         host->mrq = mrq;
1200 
1201         if (mrq->data)
1202                 msdc_prepare_data(host, mrq);
1203 
1204         /* if SBC is required, we have HW option and SW option.
1205          * if HW option is enabled, and SBC does not have "special" flags,
1206          * use HW option,  otherwise use SW option
1207          */
1208         if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1209             (mrq->sbc->arg & 0xFFFF0000)))
1210                 msdc_start_command(host, mrq, mrq->sbc);
1211         else
1212                 msdc_start_command(host, mrq, mrq->cmd);
1213 }
1214 
1215 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1216 {
1217         struct msdc_host *host = mmc_priv(mmc);
1218         struct mmc_data *data = mrq->data;
1219 
1220         if (!data)
1221                 return;
1222 
1223         msdc_prepare_data(host, mrq);
1224         data->host_cookie |= MSDC_ASYNC_FLAG;
1225 }
1226 
1227 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1228                 int err)
1229 {
1230         struct msdc_host *host = mmc_priv(mmc);
1231         struct mmc_data *data;
1232 
1233         data = mrq->data;
1234         if (!data)
1235                 return;
1236         if (data->host_cookie) {
1237                 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1238                 msdc_unprepare_data(host, mrq);
1239         }
1240 }
1241 
1242 static void msdc_data_xfer_next(struct msdc_host *host,
1243                                 struct mmc_request *mrq, struct mmc_data *data)
1244 {
1245         if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1246             !mrq->sbc)
1247                 msdc_start_command(host, mrq, mrq->stop);
1248         else
1249                 msdc_request_done(host, mrq);
1250 }
1251 
1252 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
1253                                 struct mmc_request *mrq, struct mmc_data *data)
1254 {
1255         struct mmc_command *stop = data->stop;
1256         unsigned long flags;
1257         bool done;
1258         unsigned int check_data = events &
1259             (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1260              | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1261              | MSDC_INT_DMA_PROTECT);
1262 
1263         spin_lock_irqsave(&host->lock, flags);
1264         done = !host->data;
1265         if (check_data)
1266                 host->data = NULL;
1267         spin_unlock_irqrestore(&host->lock, flags);
1268 
1269         if (done)
1270                 return true;
1271 
1272         if (check_data || (stop && stop->error)) {
1273                 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1274                                 readl(host->base + MSDC_DMA_CFG));
1275                 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1276                                 1);
1277                 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1278                         cpu_relax();
1279                 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1280                 dev_dbg(host->dev, "DMA stop\n");
1281 
1282                 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1283                         data->bytes_xfered = data->blocks * data->blksz;
1284                 } else {
1285                         dev_dbg(host->dev, "interrupt events: %x\n", events);
1286                         msdc_reset_hw(host);
1287                         host->error |= REQ_DAT_ERR;
1288                         data->bytes_xfered = 0;
1289 
1290                         if (events & MSDC_INT_DATTMO)
1291                                 data->error = -ETIMEDOUT;
1292                         else if (events & MSDC_INT_DATCRCERR)
1293                                 data->error = -EILSEQ;
1294 
1295                         dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1296                                 __func__, mrq->cmd->opcode, data->blocks);
1297                         dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1298                                 (int)data->error, data->bytes_xfered);
1299                 }
1300 
1301                 msdc_data_xfer_next(host, mrq, data);
1302                 done = true;
1303         }
1304         return done;
1305 }
1306 
1307 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1308 {
1309         u32 val = readl(host->base + SDC_CFG);
1310 
1311         val &= ~SDC_CFG_BUSWIDTH;
1312 
1313         switch (width) {
1314         default:
1315         case MMC_BUS_WIDTH_1:
1316                 val |= (MSDC_BUS_1BITS << 16);
1317                 break;
1318         case MMC_BUS_WIDTH_4:
1319                 val |= (MSDC_BUS_4BITS << 16);
1320                 break;
1321         case MMC_BUS_WIDTH_8:
1322                 val |= (MSDC_BUS_8BITS << 16);
1323                 break;
1324         }
1325 
1326         writel(val, host->base + SDC_CFG);
1327         dev_dbg(host->dev, "Bus Width = %d", width);
1328 }
1329 
1330 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1331 {
1332         struct msdc_host *host = mmc_priv(mmc);
1333         int ret = 0;
1334 
1335         if (!IS_ERR(mmc->supply.vqmmc)) {
1336                 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1337                     ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1338                         dev_err(host->dev, "Unsupported signal voltage!\n");
1339                         return -EINVAL;
1340                 }
1341 
1342                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1343                 if (ret) {
1344                         dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1345                                 ret, ios->signal_voltage);
1346                 } else {
1347                         /* Apply different pinctrl settings for different signal voltage */
1348                         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1349                                 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1350                         else
1351                                 pinctrl_select_state(host->pinctrl, host->pins_default);
1352                 }
1353         }
1354         return ret;
1355 }
1356 
1357 static int msdc_card_busy(struct mmc_host *mmc)
1358 {
1359         struct msdc_host *host = mmc_priv(mmc);
1360         u32 status = readl(host->base + MSDC_PS);
1361 
1362         /* only check if data0 is low */
1363         return !(status & BIT(16));
1364 }
1365 
1366 static void msdc_request_timeout(struct work_struct *work)
1367 {
1368         struct msdc_host *host = container_of(work, struct msdc_host,
1369                         req_timeout.work);
1370 
1371         /* simulate HW timeout status */
1372         dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1373         if (host->mrq) {
1374                 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1375                                 host->mrq, host->mrq->cmd->opcode);
1376                 if (host->cmd) {
1377                         dev_err(host->dev, "%s: aborting cmd=%d\n",
1378                                         __func__, host->cmd->opcode);
1379                         msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1380                                         host->cmd);
1381                 } else if (host->data) {
1382                         dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1383                                         __func__, host->mrq->cmd->opcode,
1384                                         host->data->blocks);
1385                         msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1386                                         host->data);
1387                 }
1388         }
1389 }
1390 
1391 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1392 {
1393         if (enb) {
1394                 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1395                 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1396         } else {
1397                 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1398                 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1399         }
1400 }
1401 
1402 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1403 {
1404         unsigned long flags;
1405         struct msdc_host *host = mmc_priv(mmc);
1406 
1407         spin_lock_irqsave(&host->lock, flags);
1408         __msdc_enable_sdio_irq(host, enb);
1409         spin_unlock_irqrestore(&host->lock, flags);
1410 
1411         if (enb)
1412                 pm_runtime_get_noresume(host->dev);
1413         else
1414                 pm_runtime_put_noidle(host->dev);
1415 }
1416 
1417 static irqreturn_t msdc_irq(int irq, void *dev_id)
1418 {
1419         struct msdc_host *host = (struct msdc_host *) dev_id;
1420 
1421         while (true) {
1422                 unsigned long flags;
1423                 struct mmc_request *mrq;
1424                 struct mmc_command *cmd;
1425                 struct mmc_data *data;
1426                 u32 events, event_mask;
1427 
1428                 spin_lock_irqsave(&host->lock, flags);
1429                 events = readl(host->base + MSDC_INT);
1430                 event_mask = readl(host->base + MSDC_INTEN);
1431                 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1432                         __msdc_enable_sdio_irq(host, 0);
1433                 /* clear interrupts */
1434                 writel(events & event_mask, host->base + MSDC_INT);
1435 
1436                 mrq = host->mrq;
1437                 cmd = host->cmd;
1438                 data = host->data;
1439                 spin_unlock_irqrestore(&host->lock, flags);
1440 
1441                 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1442                         sdio_signal_irq(host->mmc);
1443 
1444                 if ((events & event_mask) & MSDC_INT_CDSC) {
1445                         if (host->internal_cd)
1446                                 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
1447                         events &= ~MSDC_INT_CDSC;
1448                 }
1449 
1450                 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1451                         break;
1452 
1453                 if (!mrq) {
1454                         dev_err(host->dev,
1455                                 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1456                                 __func__, events, event_mask);
1457                         WARN_ON(1);
1458                         break;
1459                 }
1460 
1461                 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1462 
1463                 if (cmd)
1464                         msdc_cmd_done(host, events, mrq, cmd);
1465                 else if (data)
1466                         msdc_data_xfer_done(host, events, mrq, data);
1467         }
1468 
1469         return IRQ_HANDLED;
1470 }
1471 
1472 static void msdc_init_hw(struct msdc_host *host)
1473 {
1474         u32 val;
1475         u32 tune_reg = host->dev_comp->pad_tune_reg;
1476 
1477         /* Configure to MMC/SD mode, clock free running */
1478         sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1479 
1480         /* Reset */
1481         msdc_reset_hw(host);
1482 
1483         /* Disable and clear all interrupts */
1484         writel(0, host->base + MSDC_INTEN);
1485         val = readl(host->base + MSDC_INT);
1486         writel(val, host->base + MSDC_INT);
1487 
1488         /* Configure card detection */
1489         if (host->internal_cd) {
1490                 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1491                               DEFAULT_DEBOUNCE);
1492                 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1493                 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1494                 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1495         } else {
1496                 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1497                 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1498                 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1499         }
1500 
1501         if (host->top_base) {
1502                 writel(0, host->top_base + EMMC_TOP_CONTROL);
1503                 writel(0, host->top_base + EMMC_TOP_CMD);
1504         } else {
1505                 writel(0, host->base + tune_reg);
1506         }
1507         writel(0, host->base + MSDC_IOCON);
1508         sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1509         writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1510         sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1511         writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1512         sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1513 
1514         if (host->dev_comp->stop_clk_fix) {
1515                 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1516                               MSDC_PATCH_BIT1_STOP_DLY, 3);
1517                 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1518                              SDC_FIFO_CFG_WRVALIDSEL);
1519                 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1520                              SDC_FIFO_CFG_RDVALIDSEL);
1521         }
1522 
1523         if (host->dev_comp->busy_check)
1524                 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1525 
1526         if (host->dev_comp->async_fifo) {
1527                 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1528                               MSDC_PB2_RESPWAIT, 3);
1529                 if (host->dev_comp->enhance_rx) {
1530                         if (host->top_base)
1531                                 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1532                                              SDC_RX_ENH_EN);
1533                         else
1534                                 sdr_set_bits(host->base + SDC_ADV_CFG0,
1535                                              SDC_RX_ENHANCE_EN);
1536                 } else {
1537                         sdr_set_field(host->base + MSDC_PATCH_BIT2,
1538                                       MSDC_PB2_RESPSTSENSEL, 2);
1539                         sdr_set_field(host->base + MSDC_PATCH_BIT2,
1540                                       MSDC_PB2_CRCSTSENSEL, 2);
1541                 }
1542                 /* use async fifo, then no need tune internal delay */
1543                 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1544                              MSDC_PATCH_BIT2_CFGRESP);
1545                 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1546                              MSDC_PATCH_BIT2_CFGCRCSTS);
1547         }
1548 
1549         if (host->dev_comp->support_64g)
1550                 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1551                              MSDC_PB2_SUPPORT_64G);
1552         if (host->dev_comp->data_tune) {
1553                 if (host->top_base) {
1554                         sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1555                                      PAD_DAT_RD_RXDLY_SEL);
1556                         sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1557                                      DATA_K_VALUE_SEL);
1558                         sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1559                                      PAD_CMD_RD_RXDLY_SEL);
1560                 } else {
1561                         sdr_set_bits(host->base + tune_reg,
1562                                      MSDC_PAD_TUNE_RD_SEL |
1563                                      MSDC_PAD_TUNE_CMD_SEL);
1564                 }
1565         } else {
1566                 /* choose clock tune */
1567                 if (host->top_base)
1568                         sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1569                                      PAD_RXDLY_SEL);
1570                 else
1571                         sdr_set_bits(host->base + tune_reg,
1572                                      MSDC_PAD_TUNE_RXDLYSEL);
1573         }
1574 
1575         /* Configure to enable SDIO mode.
1576          * it's must otherwise sdio cmd5 failed
1577          */
1578         sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1579 
1580         /* Config SDIO device detect interrupt function */
1581         sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1582         sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1583 
1584         /* Configure to default data timeout */
1585         sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1586 
1587         host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1588         host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1589         if (host->top_base) {
1590                 host->def_tune_para.emmc_top_control =
1591                         readl(host->top_base + EMMC_TOP_CONTROL);
1592                 host->def_tune_para.emmc_top_cmd =
1593                         readl(host->top_base + EMMC_TOP_CMD);
1594                 host->saved_tune_para.emmc_top_control =
1595                         readl(host->top_base + EMMC_TOP_CONTROL);
1596                 host->saved_tune_para.emmc_top_cmd =
1597                         readl(host->top_base + EMMC_TOP_CMD);
1598         } else {
1599                 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1600                 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1601         }
1602         dev_dbg(host->dev, "init hardware done!");
1603 }
1604 
1605 static void msdc_deinit_hw(struct msdc_host *host)
1606 {
1607         u32 val;
1608 
1609         if (host->internal_cd) {
1610                 /* Disabled card-detect */
1611                 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1612                 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1613         }
1614 
1615         /* Disable and clear all interrupts */
1616         writel(0, host->base + MSDC_INTEN);
1617 
1618         val = readl(host->base + MSDC_INT);
1619         writel(val, host->base + MSDC_INT);
1620 }
1621 
1622 /* init gpd and bd list in msdc_drv_probe */
1623 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1624 {
1625         struct mt_gpdma_desc *gpd = dma->gpd;
1626         struct mt_bdma_desc *bd = dma->bd;
1627         dma_addr_t dma_addr;
1628         int i;
1629 
1630         memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1631 
1632         dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1633         gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1634         /* gpd->next is must set for desc DMA
1635          * That's why must alloc 2 gpd structure.
1636          */
1637         gpd->next = lower_32_bits(dma_addr);
1638         if (host->dev_comp->support_64g)
1639                 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1640 
1641         dma_addr = dma->bd_addr;
1642         gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1643         if (host->dev_comp->support_64g)
1644                 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1645 
1646         memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1647         for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1648                 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1649                 bd[i].next = lower_32_bits(dma_addr);
1650                 if (host->dev_comp->support_64g)
1651                         bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1652         }
1653 }
1654 
1655 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1656 {
1657         struct msdc_host *host = mmc_priv(mmc);
1658         int ret;
1659 
1660         msdc_set_buswidth(host, ios->bus_width);
1661 
1662         /* Suspend/Resume will do power off/on */
1663         switch (ios->power_mode) {
1664         case MMC_POWER_UP:
1665                 if (!IS_ERR(mmc->supply.vmmc)) {
1666                         msdc_init_hw(host);
1667                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1668                                         ios->vdd);
1669                         if (ret) {
1670                                 dev_err(host->dev, "Failed to set vmmc power!\n");
1671                                 return;
1672                         }
1673                 }
1674                 break;
1675         case MMC_POWER_ON:
1676                 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1677                         ret = regulator_enable(mmc->supply.vqmmc);
1678                         if (ret)
1679                                 dev_err(host->dev, "Failed to set vqmmc power!\n");
1680                         else
1681                                 host->vqmmc_enabled = true;
1682                 }
1683                 break;
1684         case MMC_POWER_OFF:
1685                 if (!IS_ERR(mmc->supply.vmmc))
1686                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1687 
1688                 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1689                         regulator_disable(mmc->supply.vqmmc);
1690                         host->vqmmc_enabled = false;
1691                 }
1692                 break;
1693         default:
1694                 break;
1695         }
1696 
1697         if (host->mclk != ios->clock || host->timing != ios->timing)
1698                 msdc_set_mclk(host, ios->timing, ios->clock);
1699 }
1700 
1701 static u32 test_delay_bit(u32 delay, u32 bit)
1702 {
1703         bit %= PAD_DELAY_MAX;
1704         return delay & (1 << bit);
1705 }
1706 
1707 static int get_delay_len(u32 delay, u32 start_bit)
1708 {
1709         int i;
1710 
1711         for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1712                 if (test_delay_bit(delay, start_bit + i) == 0)
1713                         return i;
1714         }
1715         return PAD_DELAY_MAX - start_bit;
1716 }
1717 
1718 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1719 {
1720         int start = 0, len = 0;
1721         int start_final = 0, len_final = 0;
1722         u8 final_phase = 0xff;
1723         struct msdc_delay_phase delay_phase = { 0, };
1724 
1725         if (delay == 0) {
1726                 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1727                 delay_phase.final_phase = final_phase;
1728                 return delay_phase;
1729         }
1730 
1731         while (start < PAD_DELAY_MAX) {
1732                 len = get_delay_len(delay, start);
1733                 if (len_final < len) {
1734                         start_final = start;
1735                         len_final = len;
1736                 }
1737                 start += len ? len : 1;
1738                 if (len >= 12 && start_final < 4)
1739                         break;
1740         }
1741 
1742         /* The rule is that to find the smallest delay cell */
1743         if (start_final == 0)
1744                 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1745         else
1746                 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1747         dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1748                  delay, len_final, final_phase);
1749 
1750         delay_phase.maxlen = len_final;
1751         delay_phase.start = start_final;
1752         delay_phase.final_phase = final_phase;
1753         return delay_phase;
1754 }
1755 
1756 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1757 {
1758         u32 tune_reg = host->dev_comp->pad_tune_reg;
1759 
1760         if (host->top_base)
1761                 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1762                               value);
1763         else
1764                 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1765                               value);
1766 }
1767 
1768 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1769 {
1770         u32 tune_reg = host->dev_comp->pad_tune_reg;
1771 
1772         if (host->top_base)
1773                 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1774                               PAD_DAT_RD_RXDLY, value);
1775         else
1776                 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1777                               value);
1778 }
1779 
1780 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1781 {
1782         struct msdc_host *host = mmc_priv(mmc);
1783         u32 rise_delay = 0, fall_delay = 0;
1784         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1785         struct msdc_delay_phase internal_delay_phase;
1786         u8 final_delay, final_maxlen;
1787         u32 internal_delay = 0;
1788         u32 tune_reg = host->dev_comp->pad_tune_reg;
1789         int cmd_err;
1790         int i, j;
1791 
1792         if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1793             mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1794                 sdr_set_field(host->base + tune_reg,
1795                               MSDC_PAD_TUNE_CMDRRDLY,
1796                               host->hs200_cmd_int_delay);
1797 
1798         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1799         for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1800                 msdc_set_cmd_delay(host, i);
1801                 /*
1802                  * Using the same parameters, it may sometimes pass the test,
1803                  * but sometimes it may fail. To make sure the parameters are
1804                  * more stable, we test each set of parameters 3 times.
1805                  */
1806                 for (j = 0; j < 3; j++) {
1807                         mmc_send_tuning(mmc, opcode, &cmd_err);
1808                         if (!cmd_err) {
1809                                 rise_delay |= (1 << i);
1810                         } else {
1811                                 rise_delay &= ~(1 << i);
1812                                 break;
1813                         }
1814                 }
1815         }
1816         final_rise_delay = get_best_delay(host, rise_delay);
1817         /* if rising edge has enough margin, then do not scan falling edge */
1818         if (final_rise_delay.maxlen >= 12 ||
1819             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1820                 goto skip_fall;
1821 
1822         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1823         for (i = 0; i < PAD_DELAY_MAX; i++) {
1824                 msdc_set_cmd_delay(host, i);
1825                 /*
1826                  * Using the same parameters, it may sometimes pass the test,
1827                  * but sometimes it may fail. To make sure the parameters are
1828                  * more stable, we test each set of parameters 3 times.
1829                  */
1830                 for (j = 0; j < 3; j++) {
1831                         mmc_send_tuning(mmc, opcode, &cmd_err);
1832                         if (!cmd_err) {
1833                                 fall_delay |= (1 << i);
1834                         } else {
1835                                 fall_delay &= ~(1 << i);
1836                                 break;
1837                         }
1838                 }
1839         }
1840         final_fall_delay = get_best_delay(host, fall_delay);
1841 
1842 skip_fall:
1843         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1844         if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1845                 final_maxlen = final_fall_delay.maxlen;
1846         if (final_maxlen == final_rise_delay.maxlen) {
1847                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1848                 final_delay = final_rise_delay.final_phase;
1849         } else {
1850                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1851                 final_delay = final_fall_delay.final_phase;
1852         }
1853         msdc_set_cmd_delay(host, final_delay);
1854 
1855         if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1856                 goto skip_internal;
1857 
1858         for (i = 0; i < PAD_DELAY_MAX; i++) {
1859                 sdr_set_field(host->base + tune_reg,
1860                               MSDC_PAD_TUNE_CMDRRDLY, i);
1861                 mmc_send_tuning(mmc, opcode, &cmd_err);
1862                 if (!cmd_err)
1863                         internal_delay |= (1 << i);
1864         }
1865         dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1866         internal_delay_phase = get_best_delay(host, internal_delay);
1867         sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
1868                       internal_delay_phase.final_phase);
1869 skip_internal:
1870         dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1871         return final_delay == 0xff ? -EIO : 0;
1872 }
1873 
1874 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
1875 {
1876         struct msdc_host *host = mmc_priv(mmc);
1877         u32 cmd_delay = 0;
1878         struct msdc_delay_phase final_cmd_delay = { 0,};
1879         u8 final_delay;
1880         int cmd_err;
1881         int i, j;
1882 
1883         /* select EMMC50 PAD CMD tune */
1884         sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1885         sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
1886 
1887         if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1888             mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1889                 sdr_set_field(host->base + MSDC_PAD_TUNE,
1890                               MSDC_PAD_TUNE_CMDRRDLY,
1891                               host->hs200_cmd_int_delay);
1892 
1893         if (host->hs400_cmd_resp_sel_rising)
1894                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1895         else
1896                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1897         for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1898                 sdr_set_field(host->base + PAD_CMD_TUNE,
1899                               PAD_CMD_TUNE_RX_DLY3, i);
1900                 /*
1901                  * Using the same parameters, it may sometimes pass the test,
1902                  * but sometimes it may fail. To make sure the parameters are
1903                  * more stable, we test each set of parameters 3 times.
1904                  */
1905                 for (j = 0; j < 3; j++) {
1906                         mmc_send_tuning(mmc, opcode, &cmd_err);
1907                         if (!cmd_err) {
1908                                 cmd_delay |= (1 << i);
1909                         } else {
1910                                 cmd_delay &= ~(1 << i);
1911                                 break;
1912                         }
1913                 }
1914         }
1915         final_cmd_delay = get_best_delay(host, cmd_delay);
1916         sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
1917                       final_cmd_delay.final_phase);
1918         final_delay = final_cmd_delay.final_phase;
1919 
1920         dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1921         return final_delay == 0xff ? -EIO : 0;
1922 }
1923 
1924 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1925 {
1926         struct msdc_host *host = mmc_priv(mmc);
1927         u32 rise_delay = 0, fall_delay = 0;
1928         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1929         u8 final_delay, final_maxlen;
1930         int i, ret;
1931 
1932         sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1933                       host->latch_ck);
1934         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1935         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1936         for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1937                 msdc_set_data_delay(host, i);
1938                 ret = mmc_send_tuning(mmc, opcode, NULL);
1939                 if (!ret)
1940                         rise_delay |= (1 << i);
1941         }
1942         final_rise_delay = get_best_delay(host, rise_delay);
1943         /* if rising edge has enough margin, then do not scan falling edge */
1944         if (final_rise_delay.maxlen >= 12 ||
1945             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1946                 goto skip_fall;
1947 
1948         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1949         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1950         for (i = 0; i < PAD_DELAY_MAX; i++) {
1951                 msdc_set_data_delay(host, i);
1952                 ret = mmc_send_tuning(mmc, opcode, NULL);
1953                 if (!ret)
1954                         fall_delay |= (1 << i);
1955         }
1956         final_fall_delay = get_best_delay(host, fall_delay);
1957 
1958 skip_fall:
1959         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1960         if (final_maxlen == final_rise_delay.maxlen) {
1961                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1962                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1963                 final_delay = final_rise_delay.final_phase;
1964         } else {
1965                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1966                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1967                 final_delay = final_fall_delay.final_phase;
1968         }
1969         msdc_set_data_delay(host, final_delay);
1970 
1971         dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
1972         return final_delay == 0xff ? -EIO : 0;
1973 }
1974 
1975 /*
1976  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1977  * together, which can save the tuning time.
1978  */
1979 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
1980 {
1981         struct msdc_host *host = mmc_priv(mmc);
1982         u32 rise_delay = 0, fall_delay = 0;
1983         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1984         u8 final_delay, final_maxlen;
1985         int i, ret;
1986 
1987         sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1988                       host->latch_ck);
1989 
1990         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1991         sdr_clr_bits(host->base + MSDC_IOCON,
1992                      MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1993         for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1994                 msdc_set_cmd_delay(host, i);
1995                 msdc_set_data_delay(host, i);
1996                 ret = mmc_send_tuning(mmc, opcode, NULL);
1997                 if (!ret)
1998                         rise_delay |= (1 << i);
1999         }
2000         final_rise_delay = get_best_delay(host, rise_delay);
2001         /* if rising edge has enough margin, then do not scan falling edge */
2002         if (final_rise_delay.maxlen >= 12 ||
2003             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2004                 goto skip_fall;
2005 
2006         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2007         sdr_set_bits(host->base + MSDC_IOCON,
2008                      MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2009         for (i = 0; i < PAD_DELAY_MAX; i++) {
2010                 msdc_set_cmd_delay(host, i);
2011                 msdc_set_data_delay(host, i);
2012                 ret = mmc_send_tuning(mmc, opcode, NULL);
2013                 if (!ret)
2014                         fall_delay |= (1 << i);
2015         }
2016         final_fall_delay = get_best_delay(host, fall_delay);
2017 
2018 skip_fall:
2019         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2020         if (final_maxlen == final_rise_delay.maxlen) {
2021                 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2022                 sdr_clr_bits(host->base + MSDC_IOCON,
2023                              MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2024                 final_delay = final_rise_delay.final_phase;
2025         } else {
2026                 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2027                 sdr_set_bits(host->base + MSDC_IOCON,
2028                              MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2029                 final_delay = final_fall_delay.final_phase;
2030         }
2031 
2032         msdc_set_cmd_delay(host, final_delay);
2033         msdc_set_data_delay(host, final_delay);
2034 
2035         dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2036         return final_delay == 0xff ? -EIO : 0;
2037 }
2038 
2039 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2040 {
2041         struct msdc_host *host = mmc_priv(mmc);
2042         int ret;
2043         u32 tune_reg = host->dev_comp->pad_tune_reg;
2044 
2045         if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2046                 ret = msdc_tune_together(mmc, opcode);
2047                 if (host->hs400_mode) {
2048                         sdr_clr_bits(host->base + MSDC_IOCON,
2049                                      MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2050                         msdc_set_data_delay(host, 0);
2051                 }
2052                 goto tune_done;
2053         }
2054         if (host->hs400_mode &&
2055             host->dev_comp->hs400_tune)
2056                 ret = hs400_tune_response(mmc, opcode);
2057         else
2058                 ret = msdc_tune_response(mmc, opcode);
2059         if (ret == -EIO) {
2060                 dev_err(host->dev, "Tune response fail!\n");
2061                 return ret;
2062         }
2063         if (host->hs400_mode == false) {
2064                 ret = msdc_tune_data(mmc, opcode);
2065                 if (ret == -EIO)
2066                         dev_err(host->dev, "Tune data fail!\n");
2067         }
2068 
2069 tune_done:
2070         host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2071         host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2072         host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2073         if (host->top_base) {
2074                 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2075                                 EMMC_TOP_CONTROL);
2076                 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2077                                 EMMC_TOP_CMD);
2078         }
2079         return ret;
2080 }
2081 
2082 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2083 {
2084         struct msdc_host *host = mmc_priv(mmc);
2085         host->hs400_mode = true;
2086 
2087         if (host->top_base)
2088                 writel(host->hs400_ds_delay,
2089                        host->top_base + EMMC50_PAD_DS_TUNE);
2090         else
2091                 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2092         /* hs400 mode must set it to 0 */
2093         sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2094         /* to improve read performance, set outstanding to 2 */
2095         sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2096 
2097         return 0;
2098 }
2099 
2100 static void msdc_hw_reset(struct mmc_host *mmc)
2101 {
2102         struct msdc_host *host = mmc_priv(mmc);
2103 
2104         sdr_set_bits(host->base + EMMC_IOCON, 1);
2105         udelay(10); /* 10us is enough */
2106         sdr_clr_bits(host->base + EMMC_IOCON, 1);
2107 }
2108 
2109 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2110 {
2111         unsigned long flags;
2112         struct msdc_host *host = mmc_priv(mmc);
2113 
2114         spin_lock_irqsave(&host->lock, flags);
2115         __msdc_enable_sdio_irq(host, 1);
2116         spin_unlock_irqrestore(&host->lock, flags);
2117 }
2118 
2119 static int msdc_get_cd(struct mmc_host *mmc)
2120 {
2121         struct msdc_host *host = mmc_priv(mmc);
2122         int val;
2123 
2124         if (mmc->caps & MMC_CAP_NONREMOVABLE)
2125                 return 1;
2126 
2127         if (!host->internal_cd)
2128                 return mmc_gpio_get_cd(mmc);
2129 
2130         val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2131         if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2132                 return !!val;
2133         else
2134                 return !val;
2135 }
2136 
2137 static const struct mmc_host_ops mt_msdc_ops = {
2138         .post_req = msdc_post_req,
2139         .pre_req = msdc_pre_req,
2140         .request = msdc_ops_request,
2141         .set_ios = msdc_ops_set_ios,
2142         .get_ro = mmc_gpio_get_ro,
2143         .get_cd = msdc_get_cd,
2144         .enable_sdio_irq = msdc_enable_sdio_irq,
2145         .ack_sdio_irq = msdc_ack_sdio_irq,
2146         .start_signal_voltage_switch = msdc_ops_switch_volt,
2147         .card_busy = msdc_card_busy,
2148         .execute_tuning = msdc_execute_tuning,
2149         .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2150         .hw_reset = msdc_hw_reset,
2151 };
2152 
2153 static void msdc_of_property_parse(struct platform_device *pdev,
2154                                    struct msdc_host *host)
2155 {
2156         of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2157                              &host->latch_ck);
2158 
2159         of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2160                              &host->hs400_ds_delay);
2161 
2162         of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2163                              &host->hs200_cmd_int_delay);
2164 
2165         of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2166                              &host->hs400_cmd_int_delay);
2167 
2168         if (of_property_read_bool(pdev->dev.of_node,
2169                                   "mediatek,hs400-cmd-resp-sel-rising"))
2170                 host->hs400_cmd_resp_sel_rising = true;
2171         else
2172                 host->hs400_cmd_resp_sel_rising = false;
2173 }
2174 
2175 static int msdc_drv_probe(struct platform_device *pdev)
2176 {
2177         struct mmc_host *mmc;
2178         struct msdc_host *host;
2179         struct resource *res;
2180         int ret;
2181 
2182         if (!pdev->dev.of_node) {
2183                 dev_err(&pdev->dev, "No DT found\n");
2184                 return -EINVAL;
2185         }
2186 
2187         /* Allocate MMC host for this device */
2188         mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2189         if (!mmc)
2190                 return -ENOMEM;
2191 
2192         host = mmc_priv(mmc);
2193         ret = mmc_of_parse(mmc);
2194         if (ret)
2195                 goto host_free;
2196 
2197         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2198         host->base = devm_ioremap_resource(&pdev->dev, res);
2199         if (IS_ERR(host->base)) {
2200                 ret = PTR_ERR(host->base);
2201                 goto host_free;
2202         }
2203 
2204         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2205         if (res) {
2206                 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2207                 if (IS_ERR(host->top_base))
2208                         host->top_base = NULL;
2209         }
2210 
2211         ret = mmc_regulator_get_supply(mmc);
2212         if (ret)
2213                 goto host_free;
2214 
2215         host->src_clk = devm_clk_get(&pdev->dev, "source");
2216         if (IS_ERR(host->src_clk)) {
2217                 ret = PTR_ERR(host->src_clk);
2218                 goto host_free;
2219         }
2220 
2221         host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2222         if (IS_ERR(host->h_clk)) {
2223                 ret = PTR_ERR(host->h_clk);
2224                 goto host_free;
2225         }
2226 
2227         host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
2228         if (IS_ERR(host->bus_clk))
2229                 host->bus_clk = NULL;
2230         /*source clock control gate is optional clock*/
2231         host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
2232         if (IS_ERR(host->src_clk_cg))
2233                 host->src_clk_cg = NULL;
2234 
2235         host->irq = platform_get_irq(pdev, 0);
2236         if (host->irq < 0) {
2237                 ret = -EINVAL;
2238                 goto host_free;
2239         }
2240 
2241         host->pinctrl = devm_pinctrl_get(&pdev->dev);
2242         if (IS_ERR(host->pinctrl)) {
2243                 ret = PTR_ERR(host->pinctrl);
2244                 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2245                 goto host_free;
2246         }
2247 
2248         host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2249         if (IS_ERR(host->pins_default)) {
2250                 ret = PTR_ERR(host->pins_default);
2251                 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2252                 goto host_free;
2253         }
2254 
2255         host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2256         if (IS_ERR(host->pins_uhs)) {
2257                 ret = PTR_ERR(host->pins_uhs);
2258                 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2259                 goto host_free;
2260         }
2261 
2262         msdc_of_property_parse(pdev, host);
2263 
2264         host->dev = &pdev->dev;
2265         host->dev_comp = of_device_get_match_data(&pdev->dev);
2266         host->mmc = mmc;
2267         host->src_clk_freq = clk_get_rate(host->src_clk);
2268         /* Set host parameters to mmc */
2269         mmc->ops = &mt_msdc_ops;
2270         if (host->dev_comp->clk_div_bits == 8)
2271                 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2272         else
2273                 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2274 
2275         if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2276             !mmc_can_gpio_cd(mmc) &&
2277             host->dev_comp->use_internal_cd) {
2278                 /*
2279                  * Is removable but no GPIO declared, so
2280                  * use internal functionality.
2281                  */
2282                 host->internal_cd = true;
2283         }
2284 
2285         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2286                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2287 
2288         mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
2289         /* MMC core transfer sizes tunable parameters */
2290         mmc->max_segs = MAX_BD_NUM;
2291         if (host->dev_comp->support_64g)
2292                 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2293         else
2294                 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2295         mmc->max_blk_size = 2048;
2296         mmc->max_req_size = 512 * 1024;
2297         mmc->max_blk_count = mmc->max_req_size / 512;
2298         if (host->dev_comp->support_64g)
2299                 host->dma_mask = DMA_BIT_MASK(36);
2300         else
2301                 host->dma_mask = DMA_BIT_MASK(32);
2302         mmc_dev(mmc)->dma_mask = &host->dma_mask;
2303 
2304         host->timeout_clks = 3 * 1048576;
2305         host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2306                                 2 * sizeof(struct mt_gpdma_desc),
2307                                 &host->dma.gpd_addr, GFP_KERNEL);
2308         host->dma.bd = dma_alloc_coherent(&pdev->dev,
2309                                 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2310                                 &host->dma.bd_addr, GFP_KERNEL);
2311         if (!host->dma.gpd || !host->dma.bd) {
2312                 ret = -ENOMEM;
2313                 goto release_mem;
2314         }
2315         msdc_init_gpd_bd(host, &host->dma);
2316         INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2317         spin_lock_init(&host->lock);
2318 
2319         platform_set_drvdata(pdev, mmc);
2320         msdc_ungate_clock(host);
2321         msdc_init_hw(host);
2322 
2323         ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2324                                IRQF_TRIGGER_NONE, pdev->name, host);
2325         if (ret)
2326                 goto release;
2327 
2328         pm_runtime_set_active(host->dev);
2329         pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2330         pm_runtime_use_autosuspend(host->dev);
2331         pm_runtime_enable(host->dev);
2332         ret = mmc_add_host(mmc);
2333 
2334         if (ret)
2335                 goto end;
2336 
2337         return 0;
2338 end:
2339         pm_runtime_disable(host->dev);
2340 release:
2341         platform_set_drvdata(pdev, NULL);
2342         msdc_deinit_hw(host);
2343         msdc_gate_clock(host);
2344 release_mem:
2345         if (host->dma.gpd)
2346                 dma_free_coherent(&pdev->dev,
2347                         2 * sizeof(struct mt_gpdma_desc),
2348                         host->dma.gpd, host->dma.gpd_addr);
2349         if (host->dma.bd)
2350                 dma_free_coherent(&pdev->dev,
2351                         MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2352                         host->dma.bd, host->dma.bd_addr);
2353 host_free:
2354         mmc_free_host(mmc);
2355 
2356         return ret;
2357 }
2358 
2359 static int msdc_drv_remove(struct platform_device *pdev)
2360 {
2361         struct mmc_host *mmc;
2362         struct msdc_host *host;
2363 
2364         mmc = platform_get_drvdata(pdev);
2365         host = mmc_priv(mmc);
2366 
2367         pm_runtime_get_sync(host->dev);
2368 
2369         platform_set_drvdata(pdev, NULL);
2370         mmc_remove_host(host->mmc);
2371         msdc_deinit_hw(host);
2372         msdc_gate_clock(host);
2373 
2374         pm_runtime_disable(host->dev);
2375         pm_runtime_put_noidle(host->dev);
2376         dma_free_coherent(&pdev->dev,
2377                         2 * sizeof(struct mt_gpdma_desc),
2378                         host->dma.gpd, host->dma.gpd_addr);
2379         dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2380                         host->dma.bd, host->dma.bd_addr);
2381 
2382         mmc_free_host(host->mmc);
2383 
2384         return 0;
2385 }
2386 
2387 #ifdef CONFIG_PM
2388 static void msdc_save_reg(struct msdc_host *host)
2389 {
2390         u32 tune_reg = host->dev_comp->pad_tune_reg;
2391 
2392         host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2393         host->save_para.iocon = readl(host->base + MSDC_IOCON);
2394         host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2395         host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2396         host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2397         host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2398         host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2399         host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2400         host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2401         host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2402         host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2403         if (host->top_base) {
2404                 host->save_para.emmc_top_control =
2405                         readl(host->top_base + EMMC_TOP_CONTROL);
2406                 host->save_para.emmc_top_cmd =
2407                         readl(host->top_base + EMMC_TOP_CMD);
2408                 host->save_para.emmc50_pad_ds_tune =
2409                         readl(host->top_base + EMMC50_PAD_DS_TUNE);
2410         } else {
2411                 host->save_para.pad_tune = readl(host->base + tune_reg);
2412         }
2413 }
2414 
2415 static void msdc_restore_reg(struct msdc_host *host)
2416 {
2417         u32 tune_reg = host->dev_comp->pad_tune_reg;
2418 
2419         writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2420         writel(host->save_para.iocon, host->base + MSDC_IOCON);
2421         writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2422         writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2423         writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2424         writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2425         writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2426         writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2427         writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2428         writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2429         writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2430         if (host->top_base) {
2431                 writel(host->save_para.emmc_top_control,
2432                        host->top_base + EMMC_TOP_CONTROL);
2433                 writel(host->save_para.emmc_top_cmd,
2434                        host->top_base + EMMC_TOP_CMD);
2435                 writel(host->save_para.emmc50_pad_ds_tune,
2436                        host->top_base + EMMC50_PAD_DS_TUNE);
2437         } else {
2438                 writel(host->save_para.pad_tune, host->base + tune_reg);
2439         }
2440 
2441         if (sdio_irq_claimed(host->mmc))
2442                 __msdc_enable_sdio_irq(host, 1);
2443 }
2444 
2445 static int msdc_runtime_suspend(struct device *dev)
2446 {
2447         struct mmc_host *mmc = dev_get_drvdata(dev);
2448         struct msdc_host *host = mmc_priv(mmc);
2449 
2450         msdc_save_reg(host);
2451         msdc_gate_clock(host);
2452         return 0;
2453 }
2454 
2455 static int msdc_runtime_resume(struct device *dev)
2456 {
2457         struct mmc_host *mmc = dev_get_drvdata(dev);
2458         struct msdc_host *host = mmc_priv(mmc);
2459 
2460         msdc_ungate_clock(host);
2461         msdc_restore_reg(host);
2462         return 0;
2463 }
2464 #endif
2465 
2466 static const struct dev_pm_ops msdc_dev_pm_ops = {
2467         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2468                                 pm_runtime_force_resume)
2469         SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2470 };
2471 
2472 static struct platform_driver mt_msdc_driver = {
2473         .probe = msdc_drv_probe,
2474         .remove = msdc_drv_remove,
2475         .driver = {
2476                 .name = "mtk-msdc",
2477                 .of_match_table = msdc_of_ids,
2478                 .pm = &msdc_dev_pm_ops,
2479         },
2480 };
2481 
2482 module_platform_driver(mt_msdc_driver);
2483 MODULE_LICENSE("GPL v2");
2484 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/mmc/host/mtk-sd.c

DEFINITIONS
