This source file includes following definitions.
- jz4740_mmc_write_irq_mask
- jz4740_mmc_write_irq_reg
- jz4740_mmc_read_irq_reg
- jz4740_mmc_release_dma_channels
- jz4740_mmc_acquire_dma_channels
- jz4740_mmc_get_dma_chan
- jz4740_mmc_dma_unmap
- jz4740_mmc_prepare_dma_data
- jz4740_mmc_start_dma_transfer
- jz4740_mmc_pre_request
- jz4740_mmc_post_request
- jz4740_mmc_set_irq_enabled
- jz4740_mmc_clock_enable
- jz4740_mmc_clock_disable
- jz4740_mmc_reset
- jz4740_mmc_request_done
- jz4740_mmc_poll_irq
- jz4740_mmc_transfer_check_state
- jz4740_mmc_write_data
- jz4740_mmc_read_data
- jz4740_mmc_timeout
- jz4740_mmc_read_response
- jz4740_mmc_send_command
- jz_mmc_prepare_data_transfer
- jz_mmc_irq_worker
- jz_mmc_irq
- jz4740_mmc_set_clock_rate
- jz4740_mmc_request
- jz4740_mmc_set_ios
- jz4740_mmc_enable_sdio_irq
- jz4740_mmc_probe
- jz4740_mmc_remove
- jz4740_mmc_suspend
- jz4740_mmc_resume
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7
8
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/mmc/host.h>
19 #include <linux/mmc/slot-gpio.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
25
26 #include <asm/cacheflush.h>
27
28 #define JZ_REG_MMC_STRPCL 0x00
29 #define JZ_REG_MMC_STATUS 0x04
30 #define JZ_REG_MMC_CLKRT 0x08
31 #define JZ_REG_MMC_CMDAT 0x0C
32 #define JZ_REG_MMC_RESTO 0x10
33 #define JZ_REG_MMC_RDTO 0x14
34 #define JZ_REG_MMC_BLKLEN 0x18
35 #define JZ_REG_MMC_NOB 0x1C
36 #define JZ_REG_MMC_SNOB 0x20
37 #define JZ_REG_MMC_IMASK 0x24
38 #define JZ_REG_MMC_IREG 0x28
39 #define JZ_REG_MMC_CMD 0x2C
40 #define JZ_REG_MMC_ARG 0x30
41 #define JZ_REG_MMC_RESP_FIFO 0x34
42 #define JZ_REG_MMC_RXFIFO 0x38
43 #define JZ_REG_MMC_TXFIFO 0x3C
44 #define JZ_REG_MMC_DMAC 0x44
45
46 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
47 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
48 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
49 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
50 #define JZ_MMC_STRPCL_RESET BIT(3)
51 #define JZ_MMC_STRPCL_START_OP BIT(2)
52 #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
53 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
54 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
55
56
57 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
58 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
59 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
60 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
61 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
62 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
63 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
64 #define JZ_MMC_STATUS_CLK_EN BIT(8)
65 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
66 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
67 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
68 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
69 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
70 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
71 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
72 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
73
74 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
75 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
76
77
78 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
79 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
80 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
81 #define JZ_MMC_CMDAT_INIT BIT(7)
82 #define JZ_MMC_CMDAT_BUSY BIT(6)
83 #define JZ_MMC_CMDAT_STREAM BIT(5)
84 #define JZ_MMC_CMDAT_WRITE BIT(4)
85 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
86 #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
87 #define JZ_MMC_CMDAT_RSP_R1 1
88 #define JZ_MMC_CMDAT_RSP_R2 2
89 #define JZ_MMC_CMDAT_RSP_R3 3
90
91 #define JZ_MMC_IRQ_SDIO BIT(7)
92 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
93 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
94 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
95 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
96 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
97
98 #define JZ_MMC_DMAC_DMA_SEL BIT(1)
99 #define JZ_MMC_DMAC_DMA_EN BIT(0)
100
101 #define JZ_MMC_CLK_RATE 24000000
102
103 enum jz4740_mmc_version {
104 JZ_MMC_JZ4740,
105 JZ_MMC_JZ4725B,
106 JZ_MMC_JZ4780,
107 };
108
109 enum jz4740_mmc_state {
110 JZ4740_MMC_STATE_READ_RESPONSE,
111 JZ4740_MMC_STATE_TRANSFER_DATA,
112 JZ4740_MMC_STATE_SEND_STOP,
113 JZ4740_MMC_STATE_DONE,
114 };
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129 enum jz4780_cookie {
130 COOKIE_UNMAPPED = 0,
131 COOKIE_PREMAPPED,
132 COOKIE_MAPPED,
133 };
134
135 struct jz4740_mmc_host {
136 struct mmc_host *mmc;
137 struct platform_device *pdev;
138 struct clk *clk;
139
140 enum jz4740_mmc_version version;
141
142 int irq;
143 int card_detect_irq;
144
145 void __iomem *base;
146 struct resource *mem_res;
147 struct mmc_request *req;
148 struct mmc_command *cmd;
149
150 unsigned long waiting;
151
152 uint32_t cmdat;
153
154 uint32_t irq_mask;
155
156 spinlock_t lock;
157
158 struct timer_list timeout_timer;
159 struct sg_mapping_iter miter;
160 enum jz4740_mmc_state state;
161
162
163 struct dma_chan *dma_rx;
164 struct dma_chan *dma_tx;
165 bool use_dma;
166
167
168
169
170
171 #define JZ4740_MMC_FIFO_HALF_SIZE 8
172 };
173
174 static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host,
175 uint32_t val)
176 {
177 if (host->version >= JZ_MMC_JZ4725B)
178 return writel(val, host->base + JZ_REG_MMC_IMASK);
179 else
180 return writew(val, host->base + JZ_REG_MMC_IMASK);
181 }
182
183 static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host,
184 uint32_t val)
185 {
186 if (host->version >= JZ_MMC_JZ4780)
187 writel(val, host->base + JZ_REG_MMC_IREG);
188 else
189 writew(val, host->base + JZ_REG_MMC_IREG);
190 }
191
192 static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host)
193 {
194 if (host->version >= JZ_MMC_JZ4780)
195 return readl(host->base + JZ_REG_MMC_IREG);
196 else
197 return readw(host->base + JZ_REG_MMC_IREG);
198 }
199
200
201
202
203 static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
204 {
205 if (!host->use_dma)
206 return;
207
208 dma_release_channel(host->dma_tx);
209 dma_release_channel(host->dma_rx);
210 }
211
212 static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
213 {
214 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
215 if (IS_ERR(host->dma_tx)) {
216 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
217 return PTR_ERR(host->dma_tx);
218 }
219
220 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
221 if (IS_ERR(host->dma_rx)) {
222 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
223 dma_release_channel(host->dma_tx);
224 return PTR_ERR(host->dma_rx);
225 }
226
227 return 0;
228 }
229
230 static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
231 struct mmc_data *data)
232 {
233 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
234 }
235
236 static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
237 struct mmc_data *data)
238 {
239 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
240 enum dma_data_direction dir = mmc_get_dma_dir(data);
241
242 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
243 data->host_cookie = COOKIE_UNMAPPED;
244 }
245
246
247
248
249 static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
250 struct mmc_data *data,
251 int cookie)
252 {
253 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
254 enum dma_data_direction dir = mmc_get_dma_dir(data);
255 int sg_count;
256
257 if (data->host_cookie == COOKIE_PREMAPPED)
258 return data->sg_count;
259
260 sg_count = dma_map_sg(chan->device->dev,
261 data->sg,
262 data->sg_len,
263 dir);
264
265 if (sg_count <= 0) {
266 dev_err(mmc_dev(host->mmc),
267 "Failed to map scatterlist for DMA operation\n");
268 return -EINVAL;
269 }
270
271 data->sg_count = sg_count;
272 data->host_cookie = cookie;
273
274 return data->sg_count;
275 }
276
277 static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
278 struct mmc_data *data)
279 {
280 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
281 struct dma_async_tx_descriptor *desc;
282 struct dma_slave_config conf = {
283 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
284 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
285 .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
286 .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
287 };
288 int sg_count;
289
290 if (data->flags & MMC_DATA_WRITE) {
291 conf.direction = DMA_MEM_TO_DEV;
292 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
293 } else {
294 conf.direction = DMA_DEV_TO_MEM;
295 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
296 }
297
298 sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED);
299 if (sg_count < 0)
300 return sg_count;
301
302 dmaengine_slave_config(chan, &conf);
303 desc = dmaengine_prep_slave_sg(chan, data->sg, sg_count,
304 conf.direction,
305 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
306 if (!desc) {
307 dev_err(mmc_dev(host->mmc),
308 "Failed to allocate DMA %s descriptor",
309 conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX");
310 goto dma_unmap;
311 }
312
313 dmaengine_submit(desc);
314 dma_async_issue_pending(chan);
315
316 return 0;
317
318 dma_unmap:
319 if (data->host_cookie == COOKIE_MAPPED)
320 jz4740_mmc_dma_unmap(host, data);
321 return -ENOMEM;
322 }
323
324 static void jz4740_mmc_pre_request(struct mmc_host *mmc,
325 struct mmc_request *mrq)
326 {
327 struct jz4740_mmc_host *host = mmc_priv(mmc);
328 struct mmc_data *data = mrq->data;
329
330 if (!host->use_dma)
331 return;
332
333 data->host_cookie = COOKIE_UNMAPPED;
334 if (jz4740_mmc_prepare_dma_data(host, data, COOKIE_PREMAPPED) < 0)
335 data->host_cookie = COOKIE_UNMAPPED;
336 }
337
338 static void jz4740_mmc_post_request(struct mmc_host *mmc,
339 struct mmc_request *mrq,
340 int err)
341 {
342 struct jz4740_mmc_host *host = mmc_priv(mmc);
343 struct mmc_data *data = mrq->data;
344
345 if (data && data->host_cookie != COOKIE_UNMAPPED)
346 jz4740_mmc_dma_unmap(host, data);
347
348 if (err) {
349 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
350
351 dmaengine_terminate_all(chan);
352 }
353 }
354
355
356
357 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
358 unsigned int irq, bool enabled)
359 {
360 unsigned long flags;
361
362 spin_lock_irqsave(&host->lock, flags);
363 if (enabled)
364 host->irq_mask &= ~irq;
365 else
366 host->irq_mask |= irq;
367
368 jz4740_mmc_write_irq_mask(host, host->irq_mask);
369 spin_unlock_irqrestore(&host->lock, flags);
370 }
371
372 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
373 bool start_transfer)
374 {
375 uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
376
377 if (start_transfer)
378 val |= JZ_MMC_STRPCL_START_OP;
379
380 writew(val, host->base + JZ_REG_MMC_STRPCL);
381 }
382
383 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
384 {
385 uint32_t status;
386 unsigned int timeout = 1000;
387
388 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
389 do {
390 status = readl(host->base + JZ_REG_MMC_STATUS);
391 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
392 }
393
394 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
395 {
396 uint32_t status;
397 unsigned int timeout = 1000;
398
399 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
400 udelay(10);
401 do {
402 status = readl(host->base + JZ_REG_MMC_STATUS);
403 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
404 }
405
406 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
407 {
408 struct mmc_request *req;
409 struct mmc_data *data;
410
411 req = host->req;
412 data = req->data;
413 host->req = NULL;
414
415 if (data && data->host_cookie == COOKIE_MAPPED)
416 jz4740_mmc_dma_unmap(host, data);
417 mmc_request_done(host->mmc, req);
418 }
419
420 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
421 unsigned int irq)
422 {
423 unsigned int timeout = 0x800;
424 uint32_t status;
425
426 do {
427 status = jz4740_mmc_read_irq_reg(host);
428 } while (!(status & irq) && --timeout);
429
430 if (timeout == 0) {
431 set_bit(0, &host->waiting);
432 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
433 jz4740_mmc_set_irq_enabled(host, irq, true);
434 return true;
435 }
436
437 return false;
438 }
439
440 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
441 struct mmc_data *data)
442 {
443 int status;
444
445 status = readl(host->base + JZ_REG_MMC_STATUS);
446 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
447 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
448 host->req->cmd->error = -ETIMEDOUT;
449 data->error = -ETIMEDOUT;
450 } else {
451 host->req->cmd->error = -EIO;
452 data->error = -EIO;
453 }
454 } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
455 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
456 host->req->cmd->error = -ETIMEDOUT;
457 data->error = -ETIMEDOUT;
458 } else {
459 host->req->cmd->error = -EIO;
460 data->error = -EIO;
461 }
462 }
463 }
464
465 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
466 struct mmc_data *data)
467 {
468 struct sg_mapping_iter *miter = &host->miter;
469 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
470 uint32_t *buf;
471 bool timeout;
472 size_t i, j;
473
474 while (sg_miter_next(miter)) {
475 buf = miter->addr;
476 i = miter->length / 4;
477 j = i / 8;
478 i = i & 0x7;
479 while (j) {
480 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
481 if (unlikely(timeout))
482 goto poll_timeout;
483
484 writel(buf[0], fifo_addr);
485 writel(buf[1], fifo_addr);
486 writel(buf[2], fifo_addr);
487 writel(buf[3], fifo_addr);
488 writel(buf[4], fifo_addr);
489 writel(buf[5], fifo_addr);
490 writel(buf[6], fifo_addr);
491 writel(buf[7], fifo_addr);
492 buf += 8;
493 --j;
494 }
495 if (unlikely(i)) {
496 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
497 if (unlikely(timeout))
498 goto poll_timeout;
499
500 while (i) {
501 writel(*buf, fifo_addr);
502 ++buf;
503 --i;
504 }
505 }
506 data->bytes_xfered += miter->length;
507 }
508 sg_miter_stop(miter);
509
510 return false;
511
512 poll_timeout:
513 miter->consumed = (void *)buf - miter->addr;
514 data->bytes_xfered += miter->consumed;
515 sg_miter_stop(miter);
516
517 return true;
518 }
519
520 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
521 struct mmc_data *data)
522 {
523 struct sg_mapping_iter *miter = &host->miter;
524 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
525 uint32_t *buf;
526 uint32_t d;
527 uint32_t status;
528 size_t i, j;
529 unsigned int timeout;
530
531 while (sg_miter_next(miter)) {
532 buf = miter->addr;
533 i = miter->length;
534 j = i / 32;
535 i = i & 0x1f;
536 while (j) {
537 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
538 if (unlikely(timeout))
539 goto poll_timeout;
540
541 buf[0] = readl(fifo_addr);
542 buf[1] = readl(fifo_addr);
543 buf[2] = readl(fifo_addr);
544 buf[3] = readl(fifo_addr);
545 buf[4] = readl(fifo_addr);
546 buf[5] = readl(fifo_addr);
547 buf[6] = readl(fifo_addr);
548 buf[7] = readl(fifo_addr);
549
550 buf += 8;
551 --j;
552 }
553
554 if (unlikely(i)) {
555 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
556 if (unlikely(timeout))
557 goto poll_timeout;
558
559 while (i >= 4) {
560 *buf++ = readl(fifo_addr);
561 i -= 4;
562 }
563 if (unlikely(i > 0)) {
564 d = readl(fifo_addr);
565 memcpy(buf, &d, i);
566 }
567 }
568 data->bytes_xfered += miter->length;
569
570
571
572 flush_dcache_page(miter->page);
573 }
574 sg_miter_stop(miter);
575
576
577
578 timeout = 1000;
579 status = readl(host->base + JZ_REG_MMC_STATUS);
580 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
581 d = readl(fifo_addr);
582 status = readl(host->base + JZ_REG_MMC_STATUS);
583 }
584
585 return false;
586
587 poll_timeout:
588 miter->consumed = (void *)buf - miter->addr;
589 data->bytes_xfered += miter->consumed;
590 sg_miter_stop(miter);
591
592 return true;
593 }
594
595 static void jz4740_mmc_timeout(struct timer_list *t)
596 {
597 struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer);
598
599 if (!test_and_clear_bit(0, &host->waiting))
600 return;
601
602 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
603
604 host->req->cmd->error = -ETIMEDOUT;
605 jz4740_mmc_request_done(host);
606 }
607
608 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
609 struct mmc_command *cmd)
610 {
611 int i;
612 uint16_t tmp;
613 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
614
615 if (cmd->flags & MMC_RSP_136) {
616 tmp = readw(fifo_addr);
617 for (i = 0; i < 4; ++i) {
618 cmd->resp[i] = tmp << 24;
619 tmp = readw(fifo_addr);
620 cmd->resp[i] |= tmp << 8;
621 tmp = readw(fifo_addr);
622 cmd->resp[i] |= tmp >> 8;
623 }
624 } else {
625 cmd->resp[0] = readw(fifo_addr) << 24;
626 cmd->resp[0] |= readw(fifo_addr) << 8;
627 cmd->resp[0] |= readw(fifo_addr) & 0xff;
628 }
629 }
630
631 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
632 struct mmc_command *cmd)
633 {
634 uint32_t cmdat = host->cmdat;
635
636 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
637 jz4740_mmc_clock_disable(host);
638
639 host->cmd = cmd;
640
641 if (cmd->flags & MMC_RSP_BUSY)
642 cmdat |= JZ_MMC_CMDAT_BUSY;
643
644 switch (mmc_resp_type(cmd)) {
645 case MMC_RSP_R1B:
646 case MMC_RSP_R1:
647 cmdat |= JZ_MMC_CMDAT_RSP_R1;
648 break;
649 case MMC_RSP_R2:
650 cmdat |= JZ_MMC_CMDAT_RSP_R2;
651 break;
652 case MMC_RSP_R3:
653 cmdat |= JZ_MMC_CMDAT_RSP_R3;
654 break;
655 default:
656 break;
657 }
658
659 if (cmd->data) {
660 cmdat |= JZ_MMC_CMDAT_DATA_EN;
661 if (cmd->data->flags & MMC_DATA_WRITE)
662 cmdat |= JZ_MMC_CMDAT_WRITE;
663 if (host->use_dma) {
664
665
666
667
668
669
670
671
672
673 if (host->version >= JZ_MMC_JZ4780) {
674 writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL,
675 host->base + JZ_REG_MMC_DMAC);
676 } else {
677 cmdat |= JZ_MMC_CMDAT_DMA_EN;
678 }
679 } else if (host->version >= JZ_MMC_JZ4780) {
680 writel(0, host->base + JZ_REG_MMC_DMAC);
681 }
682
683 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
684 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
685 }
686
687 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
688 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
689 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
690
691 jz4740_mmc_clock_enable(host, 1);
692 }
693
694 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
695 {
696 struct mmc_command *cmd = host->req->cmd;
697 struct mmc_data *data = cmd->data;
698 int direction;
699
700 if (data->flags & MMC_DATA_READ)
701 direction = SG_MITER_TO_SG;
702 else
703 direction = SG_MITER_FROM_SG;
704
705 sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
706 }
707
708
709 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
710 {
711 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
712 struct mmc_command *cmd = host->req->cmd;
713 struct mmc_request *req = host->req;
714 struct mmc_data *data = cmd->data;
715 bool timeout = false;
716
717 if (cmd->error)
718 host->state = JZ4740_MMC_STATE_DONE;
719
720 switch (host->state) {
721 case JZ4740_MMC_STATE_READ_RESPONSE:
722 if (cmd->flags & MMC_RSP_PRESENT)
723 jz4740_mmc_read_response(host, cmd);
724
725 if (!data)
726 break;
727
728 jz_mmc_prepare_data_transfer(host);
729
730
731 case JZ4740_MMC_STATE_TRANSFER_DATA:
732 if (host->use_dma) {
733
734
735
736
737
738
739 timeout = jz4740_mmc_start_dma_transfer(host, data);
740 data->bytes_xfered = data->blocks * data->blksz;
741 } else if (data->flags & MMC_DATA_READ)
742
743
744
745
746
747 timeout = jz4740_mmc_read_data(host, data);
748 else
749 timeout = jz4740_mmc_write_data(host, data);
750
751 if (unlikely(timeout)) {
752 host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
753 break;
754 }
755
756 jz4740_mmc_transfer_check_state(host, data);
757
758 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
759 if (unlikely(timeout)) {
760 host->state = JZ4740_MMC_STATE_SEND_STOP;
761 break;
762 }
763 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
764
765
766 case JZ4740_MMC_STATE_SEND_STOP:
767 if (!req->stop)
768 break;
769
770 jz4740_mmc_send_command(host, req->stop);
771
772 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
773 timeout = jz4740_mmc_poll_irq(host,
774 JZ_MMC_IRQ_PRG_DONE);
775 if (timeout) {
776 host->state = JZ4740_MMC_STATE_DONE;
777 break;
778 }
779 }
780 case JZ4740_MMC_STATE_DONE:
781 break;
782 }
783
784 if (!timeout)
785 jz4740_mmc_request_done(host);
786
787 return IRQ_HANDLED;
788 }
789
790 static irqreturn_t jz_mmc_irq(int irq, void *devid)
791 {
792 struct jz4740_mmc_host *host = devid;
793 struct mmc_command *cmd = host->cmd;
794 uint32_t irq_reg, status, tmp;
795
796 status = readl(host->base + JZ_REG_MMC_STATUS);
797 irq_reg = jz4740_mmc_read_irq_reg(host);
798
799 tmp = irq_reg;
800 irq_reg &= ~host->irq_mask;
801
802 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
803 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
804
805 if (tmp != irq_reg)
806 jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg);
807
808 if (irq_reg & JZ_MMC_IRQ_SDIO) {
809 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO);
810 mmc_signal_sdio_irq(host->mmc);
811 irq_reg &= ~JZ_MMC_IRQ_SDIO;
812 }
813
814 if (host->req && cmd && irq_reg) {
815 if (test_and_clear_bit(0, &host->waiting)) {
816 del_timer(&host->timeout_timer);
817
818 if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
819 cmd->error = -ETIMEDOUT;
820 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
821 cmd->error = -EIO;
822 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
823 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
824 if (cmd->data)
825 cmd->data->error = -EIO;
826 cmd->error = -EIO;
827 }
828
829 jz4740_mmc_set_irq_enabled(host, irq_reg, false);
830 jz4740_mmc_write_irq_reg(host, irq_reg);
831
832 return IRQ_WAKE_THREAD;
833 }
834 }
835
836 return IRQ_HANDLED;
837 }
838
839 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
840 {
841 int div = 0;
842 int real_rate;
843
844 jz4740_mmc_clock_disable(host);
845 clk_set_rate(host->clk, host->mmc->f_max);
846
847 real_rate = clk_get_rate(host->clk);
848
849 while (real_rate > rate && div < 7) {
850 ++div;
851 real_rate >>= 1;
852 }
853
854 writew(div, host->base + JZ_REG_MMC_CLKRT);
855 return real_rate;
856 }
857
858 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
859 {
860 struct jz4740_mmc_host *host = mmc_priv(mmc);
861
862 host->req = req;
863
864 jz4740_mmc_write_irq_reg(host, ~0);
865 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
866
867 host->state = JZ4740_MMC_STATE_READ_RESPONSE;
868 set_bit(0, &host->waiting);
869 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
870 jz4740_mmc_send_command(host, req->cmd);
871 }
872
873 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
874 {
875 struct jz4740_mmc_host *host = mmc_priv(mmc);
876 if (ios->clock)
877 jz4740_mmc_set_clock_rate(host, ios->clock);
878
879 switch (ios->power_mode) {
880 case MMC_POWER_UP:
881 jz4740_mmc_reset(host);
882 if (!IS_ERR(mmc->supply.vmmc))
883 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
884 host->cmdat |= JZ_MMC_CMDAT_INIT;
885 clk_prepare_enable(host->clk);
886 break;
887 case MMC_POWER_ON:
888 break;
889 default:
890 if (!IS_ERR(mmc->supply.vmmc))
891 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
892 clk_disable_unprepare(host->clk);
893 break;
894 }
895
896 switch (ios->bus_width) {
897 case MMC_BUS_WIDTH_1:
898 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
899 break;
900 case MMC_BUS_WIDTH_4:
901 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
902 break;
903 default:
904 break;
905 }
906 }
907
908 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
909 {
910 struct jz4740_mmc_host *host = mmc_priv(mmc);
911 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
912 }
913
914 static const struct mmc_host_ops jz4740_mmc_ops = {
915 .request = jz4740_mmc_request,
916 .pre_req = jz4740_mmc_pre_request,
917 .post_req = jz4740_mmc_post_request,
918 .set_ios = jz4740_mmc_set_ios,
919 .get_ro = mmc_gpio_get_ro,
920 .get_cd = mmc_gpio_get_cd,
921 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
922 };
923
924 static const struct of_device_id jz4740_mmc_of_match[] = {
925 { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 },
926 { .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B },
927 { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 },
928 {},
929 };
930 MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match);
931
932 static int jz4740_mmc_probe(struct platform_device* pdev)
933 {
934 int ret;
935 struct mmc_host *mmc;
936 struct jz4740_mmc_host *host;
937 const struct of_device_id *match;
938
939 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
940 if (!mmc) {
941 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
942 return -ENOMEM;
943 }
944
945 host = mmc_priv(mmc);
946
947 match = of_match_device(jz4740_mmc_of_match, &pdev->dev);
948 if (match) {
949 host->version = (enum jz4740_mmc_version)match->data;
950 } else {
951
952 host->version = JZ_MMC_JZ4740;
953 }
954
955 ret = mmc_of_parse(mmc);
956 if (ret) {
957 if (ret != -EPROBE_DEFER)
958 dev_err(&pdev->dev,
959 "could not parse device properties: %d\n", ret);
960 goto err_free_host;
961 }
962
963 mmc_regulator_get_supply(mmc);
964
965 host->irq = platform_get_irq(pdev, 0);
966 if (host->irq < 0) {
967 ret = host->irq;
968 goto err_free_host;
969 }
970
971 host->clk = devm_clk_get(&pdev->dev, "mmc");
972 if (IS_ERR(host->clk)) {
973 ret = PTR_ERR(host->clk);
974 dev_err(&pdev->dev, "Failed to get mmc clock\n");
975 goto err_free_host;
976 }
977
978 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
979 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
980 if (IS_ERR(host->base)) {
981 ret = PTR_ERR(host->base);
982 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
983 goto err_free_host;
984 }
985
986 mmc->ops = &jz4740_mmc_ops;
987 if (!mmc->f_max)
988 mmc->f_max = JZ_MMC_CLK_RATE;
989 mmc->f_min = mmc->f_max / 128;
990 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
991
992 mmc->max_blk_size = (1 << 10) - 1;
993 mmc->max_blk_count = (1 << 15) - 1;
994 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
995
996 mmc->max_segs = 128;
997 mmc->max_seg_size = mmc->max_req_size;
998
999 host->mmc = mmc;
1000 host->pdev = pdev;
1001 spin_lock_init(&host->lock);
1002 host->irq_mask = ~0;
1003
1004 jz4740_mmc_reset(host);
1005
1006 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
1007 dev_name(&pdev->dev), host);
1008 if (ret) {
1009 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1010 goto err_free_host;
1011 }
1012
1013 jz4740_mmc_clock_disable(host);
1014 timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0);
1015
1016 ret = jz4740_mmc_acquire_dma_channels(host);
1017 if (ret == -EPROBE_DEFER)
1018 goto err_free_irq;
1019 host->use_dma = !ret;
1020
1021 platform_set_drvdata(pdev, host);
1022 ret = mmc_add_host(mmc);
1023
1024 if (ret) {
1025 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
1026 goto err_release_dma;
1027 }
1028 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
1029
1030 dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
1031 host->use_dma ? "DMA" : "PIO",
1032 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1033
1034 return 0;
1035
1036 err_release_dma:
1037 if (host->use_dma)
1038 jz4740_mmc_release_dma_channels(host);
1039 err_free_irq:
1040 free_irq(host->irq, host);
1041 err_free_host:
1042 mmc_free_host(mmc);
1043
1044 return ret;
1045 }
1046
1047 static int jz4740_mmc_remove(struct platform_device *pdev)
1048 {
1049 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1050
1051 del_timer_sync(&host->timeout_timer);
1052 jz4740_mmc_set_irq_enabled(host, 0xff, false);
1053 jz4740_mmc_reset(host);
1054
1055 mmc_remove_host(host->mmc);
1056
1057 free_irq(host->irq, host);
1058
1059 if (host->use_dma)
1060 jz4740_mmc_release_dma_channels(host);
1061
1062 mmc_free_host(host->mmc);
1063
1064 return 0;
1065 }
1066
1067 #ifdef CONFIG_PM_SLEEP
1068
1069 static int jz4740_mmc_suspend(struct device *dev)
1070 {
1071 return pinctrl_pm_select_sleep_state(dev);
1072 }
1073
1074 static int jz4740_mmc_resume(struct device *dev)
1075 {
1076 return pinctrl_pm_select_default_state(dev);
1077 }
1078
1079 static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
1080 jz4740_mmc_resume);
1081 #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
1082 #else
1083 #define JZ4740_MMC_PM_OPS NULL
1084 #endif
1085
1086 static struct platform_driver jz4740_mmc_driver = {
1087 .probe = jz4740_mmc_probe,
1088 .remove = jz4740_mmc_remove,
1089 .driver = {
1090 .name = "jz4740-mmc",
1091 .of_match_table = of_match_ptr(jz4740_mmc_of_match),
1092 .pm = JZ4740_MMC_PM_OPS,
1093 },
1094 };
1095
1096 module_platform_driver(jz4740_mmc_driver);
1097
1098 MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
1099 MODULE_LICENSE("GPL");
1100 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");