This source file includes following definitions.
- sdhci_am654_set_clock
- sdhci_j721e_4bit_set_clock
- sdhci_am654_set_power
- sdhci_am654_write_b
- sdhci_am654_execute_tuning
- sdhci_am654_init
- sdhci_am654_get_of_property
- sdhci_am654_probe
- sdhci_am654_remove
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7
8 #include <linux/clk.h>
9 #include <linux/of.h>
10 #include <linux/module.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/property.h>
13 #include <linux/regmap.h>
14
15 #include "sdhci-pltfm.h"
16
17
18 #define CTL_CFG_2 0x14
19
20 #define SLOTTYPE_MASK GENMASK(31, 30)
21 #define SLOTTYPE_EMBEDDED BIT(30)
22
23
24 #define PHY_CTRL1 0x100
25 #define PHY_CTRL2 0x104
26 #define PHY_CTRL3 0x108
27 #define PHY_CTRL4 0x10C
28 #define PHY_CTRL5 0x110
29 #define PHY_CTRL6 0x114
30 #define PHY_STAT1 0x130
31 #define PHY_STAT2 0x134
32
33 #define IOMUX_ENABLE_SHIFT 31
34 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
35 #define OTAPDLYENA_SHIFT 20
36 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
37 #define OTAPDLYSEL_SHIFT 12
38 #define OTAPDLYSEL_MASK GENMASK(15, 12)
39 #define STRBSEL_SHIFT 24
40 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
41 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
42 #define SEL50_SHIFT 8
43 #define SEL50_MASK BIT(SEL50_SHIFT)
44 #define SEL100_SHIFT 9
45 #define SEL100_MASK BIT(SEL100_SHIFT)
46 #define FREQSEL_SHIFT 8
47 #define FREQSEL_MASK GENMASK(10, 8)
48 #define DLL_TRIM_ICP_SHIFT 4
49 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
50 #define DR_TY_SHIFT 20
51 #define DR_TY_MASK GENMASK(22, 20)
52 #define ENDLL_SHIFT 1
53 #define ENDLL_MASK BIT(ENDLL_SHIFT)
54 #define DLLRDY_SHIFT 0
55 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
56 #define PDB_SHIFT 0
57 #define PDB_MASK BIT(PDB_SHIFT)
58 #define CALDONE_SHIFT 1
59 #define CALDONE_MASK BIT(CALDONE_SHIFT)
60 #define RETRIM_SHIFT 17
61 #define RETRIM_MASK BIT(RETRIM_SHIFT)
62
63 #define DRIVER_STRENGTH_50_OHM 0x0
64 #define DRIVER_STRENGTH_33_OHM 0x1
65 #define DRIVER_STRENGTH_66_OHM 0x2
66 #define DRIVER_STRENGTH_100_OHM 0x3
67 #define DRIVER_STRENGTH_40_OHM 0x4
68
69 #define CLOCK_TOO_SLOW_HZ 400000
70
71 static struct regmap_config sdhci_am654_regmap_config = {
72 .reg_bits = 32,
73 .val_bits = 32,
74 .reg_stride = 4,
75 .fast_io = true,
76 };
77
78 struct sdhci_am654_data {
79 struct regmap *base;
80 int otap_del_sel;
81 int trm_icp;
82 int drv_strength;
83 bool dll_on;
84 int strb_sel;
85 u32 flags;
86 };
87
88 struct sdhci_am654_driver_data {
89 const struct sdhci_pltfm_data *pdata;
90 u32 flags;
91 #define IOMUX_PRESENT (1 << 0)
92 #define FREQSEL_2_BIT (1 << 1)
93 #define STRBSEL_4_BIT (1 << 2)
94 #define DLL_PRESENT (1 << 3)
95 };
96
97 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
98 {
99 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
100 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
101 int sel50, sel100, freqsel;
102 u32 mask, val;
103 int ret;
104
105 if (sdhci_am654->dll_on) {
106 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
107
108 sdhci_am654->dll_on = false;
109 }
110
111 sdhci_set_clock(host, clock);
112
113 if (clock > CLOCK_TOO_SLOW_HZ) {
114
115 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
116 val = (1 << OTAPDLYENA_SHIFT) |
117 (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
118 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
119
120 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
121 if (sdhci_am654->flags & STRBSEL_4_BIT)
122 mask = STRBSEL_4BIT_MASK;
123 else
124 mask = STRBSEL_8BIT_MASK;
125
126 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask,
127 sdhci_am654->strb_sel <<
128 STRBSEL_SHIFT);
129 }
130
131 if (sdhci_am654->flags & FREQSEL_2_BIT) {
132 switch (clock) {
133 case 200000000:
134 sel50 = 0;
135 sel100 = 0;
136 break;
137 case 100000000:
138 sel50 = 0;
139 sel100 = 1;
140 break;
141 default:
142 sel50 = 1;
143 sel100 = 0;
144 }
145
146
147 mask = SEL50_MASK | SEL100_MASK;
148 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
149 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask,
150 val);
151 } else {
152 switch (clock) {
153 case 200000000:
154 freqsel = 0x0;
155 break;
156 default:
157 freqsel = 0x4;
158 }
159
160 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
161 FREQSEL_MASK,
162 freqsel << FREQSEL_SHIFT);
163 }
164
165
166 mask = DLL_TRIM_ICP_MASK;
167 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
168
169
170 mask |= DR_TY_MASK;
171 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
172 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
173
174 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
175 0x1 << ENDLL_SHIFT);
176
177
178
179
180 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
181 val, val & DLLRDY_MASK, 1000,
182 1000000);
183 if (ret) {
184 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
185 return;
186 }
187
188 sdhci_am654->dll_on = true;
189 }
190 }
191
192 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
193 unsigned int clock)
194 {
195 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
196 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
197 int val, mask;
198
199 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
200 val = (1 << OTAPDLYENA_SHIFT) |
201 (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
202 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
203
204 sdhci_set_clock(host, clock);
205 }
206
207 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode,
208 unsigned short vdd)
209 {
210 if (!IS_ERR(host->mmc->supply.vmmc)) {
211 struct mmc_host *mmc = host->mmc;
212
213 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
214 }
215 sdhci_set_power_noreg(host, mode, vdd);
216 }
217
218 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
219 {
220 unsigned char timing = host->mmc->ios.timing;
221
222 if (reg == SDHCI_HOST_CONTROL) {
223 switch (timing) {
224
225
226
227
228 case MMC_TIMING_SD_HS:
229 case MMC_TIMING_MMC_HS:
230 case MMC_TIMING_UHS_SDR12:
231 case MMC_TIMING_UHS_SDR25:
232 val &= ~SDHCI_CTRL_HISPD;
233 }
234 }
235
236 writeb(val, host->ioaddr + reg);
237 }
238
239 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
240 {
241 struct sdhci_host *host = mmc_priv(mmc);
242 int err = sdhci_execute_tuning(mmc, opcode);
243
244 if (err)
245 return err;
246
247
248
249
250 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
251
252 return 0;
253 }
254
255 static struct sdhci_ops sdhci_am654_ops = {
256 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
257 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
258 .set_uhs_signaling = sdhci_set_uhs_signaling,
259 .set_bus_width = sdhci_set_bus_width,
260 .set_power = sdhci_am654_set_power,
261 .set_clock = sdhci_am654_set_clock,
262 .write_b = sdhci_am654_write_b,
263 .reset = sdhci_reset,
264 };
265
266 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
267 .ops = &sdhci_am654_ops,
268 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
269 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
270 };
271
272 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
273 .pdata = &sdhci_am654_pdata,
274 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
275 };
276
277 static struct sdhci_ops sdhci_j721e_8bit_ops = {
278 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
279 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
280 .set_uhs_signaling = sdhci_set_uhs_signaling,
281 .set_bus_width = sdhci_set_bus_width,
282 .set_power = sdhci_am654_set_power,
283 .set_clock = sdhci_am654_set_clock,
284 .write_b = sdhci_am654_write_b,
285 .reset = sdhci_reset,
286 };
287
288 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
289 .ops = &sdhci_j721e_8bit_ops,
290 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
291 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
292 };
293
294 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
295 .pdata = &sdhci_j721e_8bit_pdata,
296 .flags = DLL_PRESENT,
297 };
298
299 static struct sdhci_ops sdhci_j721e_4bit_ops = {
300 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
301 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
302 .set_uhs_signaling = sdhci_set_uhs_signaling,
303 .set_bus_width = sdhci_set_bus_width,
304 .set_power = sdhci_am654_set_power,
305 .set_clock = sdhci_j721e_4bit_set_clock,
306 .write_b = sdhci_am654_write_b,
307 .reset = sdhci_reset,
308 };
309
310 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
311 .ops = &sdhci_j721e_4bit_ops,
312 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
313 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
314 };
315
316 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
317 .pdata = &sdhci_j721e_4bit_pdata,
318 .flags = IOMUX_PRESENT,
319 };
320 static int sdhci_am654_init(struct sdhci_host *host)
321 {
322 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
323 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
324 u32 ctl_cfg_2 = 0;
325 u32 mask;
326 u32 val;
327 int ret;
328
329
330 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
331 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
332
333 if (sdhci_am654->flags & DLL_PRESENT) {
334 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
335 if (~val & CALDONE_MASK) {
336
337 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
338 PDB_MASK, PDB_MASK);
339 ret = regmap_read_poll_timeout(sdhci_am654->base,
340 PHY_STAT1, val,
341 val & CALDONE_MASK,
342 1, 20);
343 if (ret)
344 return ret;
345 }
346 }
347
348
349 if (sdhci_am654->flags & IOMUX_PRESENT)
350 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
351 IOMUX_ENABLE_MASK, 0);
352
353
354 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
355 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
356
357 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
358 ctl_cfg_2);
359
360 return sdhci_add_host(host);
361 }
362
363 static int sdhci_am654_get_of_property(struct platform_device *pdev,
364 struct sdhci_am654_data *sdhci_am654)
365 {
366 struct device *dev = &pdev->dev;
367 int drv_strength;
368 int ret;
369
370 ret = device_property_read_u32(dev, "ti,otap-del-sel",
371 &sdhci_am654->otap_del_sel);
372 if (ret)
373 return ret;
374
375 if (sdhci_am654->flags & DLL_PRESENT) {
376 ret = device_property_read_u32(dev, "ti,trm-icp",
377 &sdhci_am654->trm_icp);
378 if (ret)
379 return ret;
380
381 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
382 &drv_strength);
383 if (ret)
384 return ret;
385
386 switch (drv_strength) {
387 case 50:
388 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
389 break;
390 case 33:
391 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
392 break;
393 case 66:
394 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
395 break;
396 case 100:
397 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
398 break;
399 case 40:
400 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
401 break;
402 default:
403 dev_err(dev, "Invalid driver strength\n");
404 return -EINVAL;
405 }
406 }
407
408 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
409
410 sdhci_get_of_property(pdev);
411
412 return 0;
413 }
414
415 static const struct of_device_id sdhci_am654_of_match[] = {
416 {
417 .compatible = "ti,am654-sdhci-5.1",
418 .data = &sdhci_am654_drvdata,
419 },
420 {
421 .compatible = "ti,j721e-sdhci-8bit",
422 .data = &sdhci_j721e_8bit_drvdata,
423 },
424 {
425 .compatible = "ti,j721e-sdhci-4bit",
426 .data = &sdhci_j721e_4bit_drvdata,
427 },
428 { }
429 };
430
431 static int sdhci_am654_probe(struct platform_device *pdev)
432 {
433 const struct sdhci_am654_driver_data *drvdata;
434 struct sdhci_pltfm_host *pltfm_host;
435 struct sdhci_am654_data *sdhci_am654;
436 const struct of_device_id *match;
437 struct sdhci_host *host;
438 struct resource *res;
439 struct clk *clk_xin;
440 struct device *dev = &pdev->dev;
441 void __iomem *base;
442 int ret;
443
444 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
445 drvdata = match->data;
446 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
447 if (IS_ERR(host))
448 return PTR_ERR(host);
449
450 pltfm_host = sdhci_priv(host);
451 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
452 sdhci_am654->flags = drvdata->flags;
453
454 clk_xin = devm_clk_get(dev, "clk_xin");
455 if (IS_ERR(clk_xin)) {
456 dev_err(dev, "clk_xin clock not found.\n");
457 ret = PTR_ERR(clk_xin);
458 goto err_pltfm_free;
459 }
460
461 pltfm_host->clk = clk_xin;
462
463
464 pm_runtime_enable(dev);
465 ret = pm_runtime_get_sync(dev);
466 if (ret < 0) {
467 pm_runtime_put_noidle(dev);
468 goto pm_runtime_disable;
469 }
470
471 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
472 base = devm_ioremap_resource(dev, res);
473 if (IS_ERR(base)) {
474 ret = PTR_ERR(base);
475 goto pm_runtime_put;
476 }
477
478 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
479 &sdhci_am654_regmap_config);
480 if (IS_ERR(sdhci_am654->base)) {
481 dev_err(dev, "Failed to initialize regmap\n");
482 ret = PTR_ERR(sdhci_am654->base);
483 goto pm_runtime_put;
484 }
485
486 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
487 if (ret)
488 goto pm_runtime_put;
489
490 ret = mmc_of_parse(host->mmc);
491 if (ret) {
492 dev_err(dev, "parsing dt failed (%d)\n", ret);
493 goto pm_runtime_put;
494 }
495
496 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
497
498 ret = sdhci_am654_init(host);
499 if (ret)
500 goto pm_runtime_put;
501
502 return 0;
503
504 pm_runtime_put:
505 pm_runtime_put_sync(dev);
506 pm_runtime_disable:
507 pm_runtime_disable(dev);
508 err_pltfm_free:
509 sdhci_pltfm_free(pdev);
510 return ret;
511 }
512
513 static int sdhci_am654_remove(struct platform_device *pdev)
514 {
515 struct sdhci_host *host = platform_get_drvdata(pdev);
516 int ret;
517
518 sdhci_remove_host(host, true);
519 ret = pm_runtime_put_sync(&pdev->dev);
520 if (ret < 0)
521 return ret;
522
523 pm_runtime_disable(&pdev->dev);
524 sdhci_pltfm_free(pdev);
525
526 return 0;
527 }
528
529 static struct platform_driver sdhci_am654_driver = {
530 .driver = {
531 .name = "sdhci-am654",
532 .of_match_table = sdhci_am654_of_match,
533 },
534 .probe = sdhci_am654_probe,
535 .remove = sdhci_am654_remove,
536 };
537
538 module_platform_driver(sdhci_am654_driver);
539
540 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
541 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
542 MODULE_LICENSE("GPL");