drivers/mmc/host/renesas_sdhi

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This source file includes following definitions.
renesas_sdhi_sdbuf_width
renesas_sdhi_clk_enable
renesas_sdhi_clk_update
renesas_sdhi_set_clock
renesas_sdhi_clk_disable
renesas_sdhi_card_busy
renesas_sdhi_start_signal_voltage_switch
sd_scc_read32
sd_scc_write32
renesas_sdhi_init_tuning
renesas_sdhi_prepare_tuning
renesas_sdhi_hs400_complete
renesas_sdhi_reset_scc
renesas_sdhi_disable_scc
renesas_sdhi_reset_hs400_mode
renesas_sdhi_prepare_hs400_tuning
renesas_sdhi_select_tuning
renesas_sdhi_check_scc_error
renesas_sdhi_hw_reset
renesas_sdhi_wait_idle
renesas_sdhi_write16_hook
renesas_sdhi_multi_io_quirk
renesas_sdhi_enable_dma
renesas_sdhi_probe
renesas_sdhi_remove
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas SDHI
   4  *
   5  * Copyright (C) 2015-19 Renesas Electronics Corporation
   6  * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
   7  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   8  * Copyright (C) 2009 Magnus Damm
   9  *
  10  * Based on "Compaq ASIC3 support":
  11  *
  12  * Copyright 2001 Compaq Computer Corporation.
  13  * Copyright 2004-2005 Phil Blundell
  14  * Copyright 2007-2008 OpenedHand Ltd.
  15  *
  16  * Authors: Phil Blundell <pb@handhelds.org>,
  17  *          Samuel Ortiz <sameo@openedhand.com>
  18  *
  19  */
  20 
  21 #include <linux/kernel.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/mmc/slot-gpio.h>
  29 #include <linux/mfd/tmio.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/delay.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #include <linux/pinctrl/pinctrl-state.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/sys_soc.h>
  36 
  37 #include "renesas_sdhi.h"
  38 #include "tmio_mmc.h"
  39 
  40 #define HOST_MODE               0xe4
  41 
  42 #define SDHI_VER_GEN2_SDR50     0x490c
  43 #define SDHI_VER_RZ_A1          0x820b
  44 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  45 #define SDHI_VER_GEN2_SDR104    0xcb0d
  46 #define SDHI_VER_GEN3_SD        0xcc10
  47 #define SDHI_VER_GEN3_SDMMC     0xcd10
  48 
  49 struct renesas_sdhi_quirks {
  50         bool hs400_disabled;
  51         bool hs400_4taps;
  52 };
  53 
  54 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  55 {
  56         u32 val;
  57 
  58         /*
  59          * see also
  60          *      renesas_sdhi_of_data :: dma_buswidth
  61          */
  62         switch (sd_ctrl_read16(host, CTL_VERSION)) {
  63         case SDHI_VER_GEN2_SDR50:
  64                 val = (width == 32) ? 0x0001 : 0x0000;
  65                 break;
  66         case SDHI_VER_GEN2_SDR104:
  67                 val = (width == 32) ? 0x0000 : 0x0001;
  68                 break;
  69         case SDHI_VER_GEN3_SD:
  70         case SDHI_VER_GEN3_SDMMC:
  71                 if (width == 64)
  72                         val = 0x0000;
  73                 else if (width == 32)
  74                         val = 0x0101;
  75                 else
  76                         val = 0x0001;
  77                 break;
  78         default:
  79                 /* nothing to do */
  80                 return;
  81         }
  82 
  83         sd_ctrl_write16(host, HOST_MODE, val);
  84 }
  85 
  86 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  87 {
  88         struct mmc_host *mmc = host->mmc;
  89         struct renesas_sdhi *priv = host_to_priv(host);
  90         int ret = clk_prepare_enable(priv->clk);
  91 
  92         if (ret < 0)
  93                 return ret;
  94 
  95         ret = clk_prepare_enable(priv->clk_cd);
  96         if (ret < 0) {
  97                 clk_disable_unprepare(priv->clk);
  98                 return ret;
  99         }
 100 
 101         /*
 102          * The clock driver may not know what maximum frequency
 103          * actually works, so it should be set with the max-frequency
 104          * property which will already have been read to f_max.  If it
 105          * was missing, assume the current frequency is the maximum.
 106          */
 107         if (!mmc->f_max)
 108                 mmc->f_max = clk_get_rate(priv->clk);
 109 
 110         /*
 111          * Minimum frequency is the minimum input clock frequency
 112          * divided by our maximum divider.
 113          */
 114         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 115 
 116         /* enable 16bit data access on SDBUF as default */
 117         renesas_sdhi_sdbuf_width(host, 16);
 118 
 119         return 0;
 120 }
 121 
 122 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 123                                             unsigned int new_clock)
 124 {
 125         struct renesas_sdhi *priv = host_to_priv(host);
 126         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 127         int i;
 128 
 129         /* tested only on R-Car Gen2+ currently; may work for others */
 130         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 131                 return clk_get_rate(priv->clk);
 132 
 133         /*
 134          * We want the bus clock to be as close as possible to, but no
 135          * greater than, new_clock.  As we can divide by 1 << i for
 136          * any i in [0, 9] we want the input clock to be as close as
 137          * possible, but no greater than, new_clock << i.
 138          */
 139         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 140                 freq = clk_round_rate(priv->clk, new_clock << i);
 141                 if (freq > (new_clock << i)) {
 142                         /* Too fast; look for a slightly slower option */
 143                         freq = clk_round_rate(priv->clk,
 144                                               (new_clock << i) / 4 * 3);
 145                         if (freq > (new_clock << i))
 146                                 continue;
 147                 }
 148 
 149                 diff = new_clock - (freq >> i);
 150                 if (diff <= diff_min) {
 151                         best_freq = freq;
 152                         diff_min = diff;
 153                 }
 154         }
 155 
 156         clk_set_rate(priv->clk, best_freq);
 157 
 158         return clk_get_rate(priv->clk);
 159 }
 160 
 161 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 162                                    unsigned int new_clock)
 163 {
 164         u32 clk = 0, clock;
 165 
 166         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 167                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 168 
 169         if (new_clock == 0) {
 170                 host->mmc->actual_clock = 0;
 171                 goto out;
 172         }
 173 
 174         host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
 175         clock = host->mmc->actual_clock / 512;
 176 
 177         for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
 178                 clock <<= 1;
 179 
 180         /* 1/1 clock is option */
 181         if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
 182                 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
 183                         clk |= 0xff;
 184                 else
 185                         clk &= ~0xff;
 186         }
 187 
 188         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
 189         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 190                 usleep_range(10000, 11000);
 191 
 192         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 193                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 194 
 195 out:
 196         /* HW engineers overrode docs: no sleep needed on R-Car2+ */
 197         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 198                 usleep_range(10000, 11000);
 199 }
 200 
 201 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 202 {
 203         struct renesas_sdhi *priv = host_to_priv(host);
 204 
 205         clk_disable_unprepare(priv->clk);
 206         clk_disable_unprepare(priv->clk_cd);
 207 }
 208 
 209 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 210 {
 211         struct tmio_mmc_host *host = mmc_priv(mmc);
 212 
 213         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 214                  TMIO_STAT_DAT0);
 215 }
 216 
 217 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 218                                                     struct mmc_ios *ios)
 219 {
 220         struct tmio_mmc_host *host = mmc_priv(mmc);
 221         struct renesas_sdhi *priv = host_to_priv(host);
 222         struct pinctrl_state *pin_state;
 223         int ret;
 224 
 225         switch (ios->signal_voltage) {
 226         case MMC_SIGNAL_VOLTAGE_330:
 227                 pin_state = priv->pins_default;
 228                 break;
 229         case MMC_SIGNAL_VOLTAGE_180:
 230                 pin_state = priv->pins_uhs;
 231                 break;
 232         default:
 233                 return -EINVAL;
 234         }
 235 
 236         /*
 237          * If anything is missing, assume signal voltage is fixed at
 238          * 3.3V and succeed/fail accordingly.
 239          */
 240         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 241                 return ios->signal_voltage ==
 242                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 243 
 244         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 245         if (ret)
 246                 return ret;
 247 
 248         return pinctrl_select_state(priv->pinctrl, pin_state);
 249 }
 250 
 251 /* SCC registers */
 252 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 253 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 254 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 255 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 256 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 257 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 258 #define SH_MOBILE_SDHI_SCC_TMPPORT2     0x00E
 259 
 260 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
 261 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 262 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 263 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 264 
 265 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
 266 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 267 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
 268 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 269 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
 270 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 271 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
 272 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL   BIT(4)
 273 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN     BIT(31)
 274 
 275 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 276                                 struct renesas_sdhi *priv, int addr)
 277 {
 278         return readl(priv->scc_ctl + (addr << host->bus_shift));
 279 }
 280 
 281 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 282                                   struct renesas_sdhi *priv,
 283                                   int addr, u32 val)
 284 {
 285         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 286 }
 287 
 288 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 289 {
 290         struct renesas_sdhi *priv;
 291 
 292         priv = host_to_priv(host);
 293 
 294         /* Initialize SCC */
 295         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 296 
 297         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 298                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 299 
 300         /* set sampling clock selection range */
 301         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 302                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 303                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 304 
 305         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 306                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 307                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 308 
 309         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 310                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 311                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 312 
 313         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 314 
 315         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 316                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 317 
 318         /* Read TAPNUM */
 319         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 320                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 321                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 322 }
 323 
 324 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
 325                                         unsigned long tap)
 326 {
 327         struct renesas_sdhi *priv = host_to_priv(host);
 328 
 329         /* Set sampling clock position */
 330         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
 331 }
 332 
 333 static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
 334 {
 335         struct renesas_sdhi *priv = host_to_priv(host);
 336 
 337         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 338                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 339 
 340         /* Set HS400 mode */
 341         sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
 342                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 343 
 344         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
 345                        priv->scc_tappos_hs400);
 346 
 347         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 348                        (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 349                         SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
 350                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 351 
 352         /* Set the sampling clock selection range of HS400 mode */
 353         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 354                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 355                        0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 356 
 357 
 358         if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400)
 359                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 360                                host->tap_set / 2);
 361 
 362         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 363                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 364                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 365 
 366         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 367                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 368 }
 369 
 370 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
 371                                    struct renesas_sdhi *priv)
 372 {
 373         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 374                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 375 
 376         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 377                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 378                        sd_scc_read32(host, priv,
 379                                      SH_MOBILE_SDHI_SCC_CKSEL));
 380 }
 381 
 382 static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host)
 383 {
 384         struct renesas_sdhi *priv = host_to_priv(host);
 385 
 386         renesas_sdhi_reset_scc(host, priv);
 387 
 388         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 389                        ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
 390                        sd_scc_read32(host, priv,
 391                                      SH_MOBILE_SDHI_SCC_DTCNTL));
 392 
 393         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 394                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 395 }
 396 
 397 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
 398                                           struct renesas_sdhi *priv)
 399 {
 400         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 401                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 402 
 403         /* Reset HS400 mode */
 404         sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
 405                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 406 
 407         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 408 
 409         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 410                        ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 411                          SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
 412                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 413 
 414         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 415                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 416 }
 417 
 418 static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host)
 419 {
 420         renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
 421 }
 422 
 423 #define SH_MOBILE_SDHI_MAX_TAP 3
 424 
 425 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 426 {
 427         struct renesas_sdhi *priv = host_to_priv(host);
 428         unsigned long tap_cnt;  /* counter of tuning success */
 429         unsigned long tap_start;/* start position of tuning success */
 430         unsigned long tap_end;  /* end position of tuning success */
 431         unsigned long ntap;     /* temporary counter of tuning success */
 432         unsigned long i;
 433 
 434         /* Clear SCC_RVSREQ */
 435         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 436 
 437         /*
 438          * When tuning CMD19 is issued twice for each tap, merge the
 439          * result requiring the tap to be good in both runs before
 440          * considering it for tuning selection.
 441          */
 442         for (i = 0; i < host->tap_num * 2; i++) {
 443                 int offset = host->tap_num * (i < host->tap_num ? 1 : -1);
 444 
 445                 if (!test_bit(i, host->taps))
 446                         clear_bit(i + offset, host->taps);
 447         }
 448 
 449         /*
 450          * Find the longest consecutive run of successful probes.  If that
 451          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
 452          * center index as the tap.
 453          */
 454         tap_cnt = 0;
 455         ntap = 0;
 456         tap_start = 0;
 457         tap_end = 0;
 458         for (i = 0; i < host->tap_num * 2; i++) {
 459                 if (test_bit(i, host->taps)) {
 460                         ntap++;
 461                 } else {
 462                         if (ntap > tap_cnt) {
 463                                 tap_start = i - ntap;
 464                                 tap_end = i - 1;
 465                                 tap_cnt = ntap;
 466                         }
 467                         ntap = 0;
 468                 }
 469         }
 470 
 471         if (ntap > tap_cnt) {
 472                 tap_start = i - ntap;
 473                 tap_end = i - 1;
 474                 tap_cnt = ntap;
 475         }
 476 
 477         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
 478                 host->tap_set = (tap_start + tap_end) / 2 % host->tap_num;
 479         else
 480                 return -EIO;
 481 
 482         /* Set SCC */
 483         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set);
 484 
 485         /* Enable auto re-tuning */
 486         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 487                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 488                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 489 
 490         return 0;
 491 }
 492 
 493 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
 494 {
 495         struct renesas_sdhi *priv = host_to_priv(host);
 496         bool use_4tap = host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400;
 497 
 498         /*
 499          * Skip checking SCC errors when running on 4 taps in HS400 mode as
 500          * any retuning would still result in the same 4 taps being used.
 501          */
 502         if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
 503             !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
 504             !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
 505                 return false;
 506 
 507         if (mmc_doing_retune(host->mmc))
 508                 return false;
 509 
 510         /* Check SCC error */
 511         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 512             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
 513             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 514             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 515                 /* Clear SCC error */
 516                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 517                 return true;
 518         }
 519 
 520         return false;
 521 }
 522 
 523 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
 524 {
 525         struct renesas_sdhi *priv;
 526 
 527         priv = host_to_priv(host);
 528 
 529         renesas_sdhi_reset_scc(host, priv);
 530         renesas_sdhi_reset_hs400_mode(host, priv);
 531 
 532         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 533                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 534 
 535         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 536                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 537                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 538 
 539         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 540                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 541                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 542 
 543         if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
 544                 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
 545                                              TMIO_MASK_INIT_RCAR2);
 546 }
 547 
 548 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 549 {
 550         int timeout = 1000;
 551         /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 552         u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 553 
 554         while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 555                               & bit) == wait_state)
 556                 udelay(1);
 557 
 558         if (!timeout) {
 559                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 560                 return -EBUSY;
 561         }
 562 
 563         return 0;
 564 }
 565 
 566 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 567 {
 568         u32 bit = TMIO_STAT_SCLKDIVEN;
 569 
 570         switch (addr) {
 571         case CTL_SD_CMD:
 572         case CTL_STOP_INTERNAL_ACTION:
 573         case CTL_XFER_BLK_COUNT:
 574         case CTL_SD_XFER_LEN:
 575         case CTL_SD_MEM_CARD_OPT:
 576         case CTL_TRANSACTION_CTL:
 577         case CTL_DMA_ENABLE:
 578         case HOST_MODE:
 579                 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 580                         bit = TMIO_STAT_CMD_BUSY;
 581                 /* fallthrough */
 582         case CTL_SD_CARD_CLK_CTL:
 583                 return renesas_sdhi_wait_idle(host, bit);
 584         }
 585 
 586         return 0;
 587 }
 588 
 589 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 590                                        unsigned int direction, int blk_size)
 591 {
 592         /*
 593          * In Renesas controllers, when performing a
 594          * multiple block read of one or two blocks,
 595          * depending on the timing with which the
 596          * response register is read, the response
 597          * value may not be read properly.
 598          * Use single block read for this HW bug
 599          */
 600         if ((direction == MMC_DATA_READ) &&
 601             blk_size == 2)
 602                 return 1;
 603 
 604         return blk_size;
 605 }
 606 
 607 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 608 {
 609         /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 610         int width = (host->bus_shift == 2) ? 64 : 32;
 611 
 612         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 613         renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 614 }
 615 
 616 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
 617         .hs400_disabled = true,
 618         .hs400_4taps = true,
 619 };
 620 
 621 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
 622         .hs400_4taps = true,
 623 };
 624 
 625 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
 626         .hs400_disabled = true,
 627 };
 628 
 629 static const struct soc_device_attribute sdhi_quirks_match[]  = {
 630         { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
 631         { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
 632         { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
 633         { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
 634         { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
 635         { /* Sentinel. */ },
 636 };
 637 
 638 int renesas_sdhi_probe(struct platform_device *pdev,
 639                        const struct tmio_mmc_dma_ops *dma_ops)
 640 {
 641         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 642         const struct renesas_sdhi_quirks *quirks = NULL;
 643         const struct renesas_sdhi_of_data *of_data;
 644         const struct soc_device_attribute *attr;
 645         struct tmio_mmc_data *mmc_data;
 646         struct tmio_mmc_dma *dma_priv;
 647         struct tmio_mmc_host *host;
 648         struct renesas_sdhi *priv;
 649         int num_irqs, irq, ret, i;
 650         struct resource *res;
 651         u16 ver;
 652 
 653         of_data = of_device_get_match_data(&pdev->dev);
 654 
 655         attr = soc_device_match(sdhi_quirks_match);
 656         if (attr)
 657                 quirks = attr->data;
 658 
 659         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 660         if (!res)
 661                 return -EINVAL;
 662 
 663         priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 664                             GFP_KERNEL);
 665         if (!priv)
 666                 return -ENOMEM;
 667 
 668         mmc_data = &priv->mmc_data;
 669         dma_priv = &priv->dma_priv;
 670 
 671         priv->clk = devm_clk_get(&pdev->dev, NULL);
 672         if (IS_ERR(priv->clk)) {
 673                 ret = PTR_ERR(priv->clk);
 674                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 675                 return ret;
 676         }
 677 
 678         /*
 679          * Some controllers provide a 2nd clock just to run the internal card
 680          * detection logic. Unfortunately, the existing driver architecture does
 681          * not support a separation of clocks for runtime PM usage. When
 682          * native hotplug is used, the tmio driver assumes that the core
 683          * must continue to run for card detect to stay active, so we cannot
 684          * disable it.
 685          * Additionally, it is prohibited to supply a clock to the core but not
 686          * to the card detect circuit. That leaves us with if separate clocks
 687          * are presented, we must treat them both as virtually 1 clock.
 688          */
 689         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 690         if (IS_ERR(priv->clk_cd))
 691                 priv->clk_cd = NULL;
 692 
 693         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 694         if (!IS_ERR(priv->pinctrl)) {
 695                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 696                                                 PINCTRL_STATE_DEFAULT);
 697                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 698                                                 "state_uhs");
 699         }
 700 
 701         host = tmio_mmc_host_alloc(pdev, mmc_data);
 702         if (IS_ERR(host))
 703                 return PTR_ERR(host);
 704 
 705         if (of_data) {
 706                 mmc_data->flags |= of_data->tmio_flags;
 707                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 708                 mmc_data->capabilities |= of_data->capabilities;
 709                 mmc_data->capabilities2 |= of_data->capabilities2;
 710                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 711                 mmc_data->max_blk_count = of_data->max_blk_count;
 712                 mmc_data->max_segs = of_data->max_segs;
 713                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 714                 host->bus_shift = of_data->bus_shift;
 715         }
 716 
 717         host->write16_hook      = renesas_sdhi_write16_hook;
 718         host->clk_enable        = renesas_sdhi_clk_enable;
 719         host->clk_disable       = renesas_sdhi_clk_disable;
 720         host->set_clock         = renesas_sdhi_set_clock;
 721         host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
 722         host->dma_ops           = dma_ops;
 723 
 724         if (quirks && quirks->hs400_disabled)
 725                 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
 726 
 727         if (quirks && quirks->hs400_4taps)
 728                 mmc_data->flags |= TMIO_MMC_HAVE_4TAP_HS400;
 729 
 730         /* For some SoC, we disable internal WP. GPIO may override this */
 731         if (mmc_can_gpio_ro(host->mmc))
 732                 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
 733 
 734         /* SDR speeds are only available on Gen2+ */
 735         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
 736                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
 737                 host->ops.card_busy = renesas_sdhi_card_busy;
 738                 host->ops.start_signal_voltage_switch =
 739                         renesas_sdhi_start_signal_voltage_switch;
 740                 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
 741 
 742                 /* SDR and HS200/400 registers requires HW reset */
 743                 if (of_data && of_data->scc_offset) {
 744                         priv->scc_ctl = host->ctl + of_data->scc_offset;
 745                         host->mmc->caps |= MMC_CAP_HW_RESET;
 746                         host->hw_reset = renesas_sdhi_hw_reset;
 747                 }
 748         }
 749 
 750         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
 751         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
 752                 host->bus_shift = 1;
 753 
 754         if (mmd)
 755                 *mmc_data = *mmd;
 756 
 757         dma_priv->filter = shdma_chan_filter;
 758         dma_priv->enable = renesas_sdhi_enable_dma;
 759 
 760         mmc_data->alignment_shift = 1; /* 2-byte alignment */
 761         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
 762 
 763         /*
 764          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
 765          * bus width mode.
 766          */
 767         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 768 
 769         /*
 770          * All SDHI blocks support SDIO IRQ signalling.
 771          */
 772         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
 773 
 774         /* All SDHI have CMD12 control bit */
 775         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
 776 
 777         /* All SDHI have SDIO status bits which must be 1 */
 778         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
 779 
 780         ret = renesas_sdhi_clk_enable(host);
 781         if (ret)
 782                 goto efree;
 783 
 784         ver = sd_ctrl_read16(host, CTL_VERSION);
 785         /* GEN2_SDR104 is first known SDHI to use 32bit block count */
 786         if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
 787                 mmc_data->max_blk_count = U16_MAX;
 788 
 789         /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
 790         if (ver == SDHI_VER_GEN2_SDR50)
 791                 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
 792 
 793         ret = tmio_mmc_host_probe(host);
 794         if (ret < 0)
 795                 goto edisclk;
 796 
 797         /* Enable tuning iff we have an SCC and a supported mode */
 798         if (of_data && of_data->scc_offset &&
 799             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
 800              host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
 801                                  MMC_CAP2_HS400_1_8V))) {
 802                 const struct renesas_sdhi_scc *taps = of_data->taps;
 803                 bool hit = false;
 804 
 805                 for (i = 0; i < of_data->taps_num; i++) {
 806                         if (taps[i].clk_rate == 0 ||
 807                             taps[i].clk_rate == host->mmc->f_max) {
 808                                 priv->scc_tappos = taps->tap;
 809                                 priv->scc_tappos_hs400 = taps->tap_hs400;
 810                                 hit = true;
 811                                 break;
 812                         }
 813                 }
 814 
 815                 if (!hit)
 816                         dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
 817 
 818                 host->init_tuning = renesas_sdhi_init_tuning;
 819                 host->prepare_tuning = renesas_sdhi_prepare_tuning;
 820                 host->select_tuning = renesas_sdhi_select_tuning;
 821                 host->check_scc_error = renesas_sdhi_check_scc_error;
 822                 host->prepare_hs400_tuning =
 823                         renesas_sdhi_prepare_hs400_tuning;
 824                 host->hs400_downgrade = renesas_sdhi_disable_scc;
 825                 host->hs400_complete = renesas_sdhi_hs400_complete;
 826         }
 827 
 828         num_irqs = platform_irq_count(pdev);
 829         if (num_irqs < 0) {
 830                 ret = num_irqs;
 831                 goto eirq;
 832         }
 833 
 834         /* There must be at least one IRQ source */
 835         if (!num_irqs) {
 836                 ret = -ENXIO;
 837                 goto eirq;
 838         }
 839 
 840         for (i = 0; i < num_irqs; i++) {
 841                 irq = platform_get_irq(pdev, i);
 842                 if (irq < 0) {
 843                         ret = irq;
 844                         goto eirq;
 845                 }
 846 
 847                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
 848                                        dev_name(&pdev->dev), host);
 849                 if (ret)
 850                         goto eirq;
 851         }
 852 
 853         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
 854                  mmc_hostname(host->mmc), (unsigned long)
 855                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
 856                  host->mmc->f_max / 1000000);
 857 
 858         return ret;
 859 
 860 eirq:
 861         tmio_mmc_host_remove(host);
 862 edisclk:
 863         renesas_sdhi_clk_disable(host);
 864 efree:
 865         tmio_mmc_host_free(host);
 866 
 867         return ret;
 868 }
 869 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
 870 
 871 int renesas_sdhi_remove(struct platform_device *pdev)
 872 {
 873         struct tmio_mmc_host *host = platform_get_drvdata(pdev);
 874 
 875         tmio_mmc_host_remove(host);
 876         renesas_sdhi_clk_disable(host);
 877 
 878         return 0;
 879 }
 880 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
 881 
 882 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/mmc/host/renesas_sdhi_core.c

DEFINITIONS
