This source file includes following definitions.
- sunxi_mmc_reset_host
- sunxi_mmc_init_host
- sunxi_mmc_init_idma_des
- sunxi_mmc_map_dma
- sunxi_mmc_start_dma
- sunxi_mmc_send_manual_stop
- sunxi_mmc_dump_errinfo
- sunxi_mmc_finalize_request
- sunxi_mmc_irq
- sunxi_mmc_handle_manual_stop
- sunxi_mmc_oclk_onoff
- sunxi_mmc_calibrate
- sunxi_mmc_clk_set_phase
- sunxi_mmc_clk_set_rate
- sunxi_mmc_set_bus_width
- sunxi_mmc_set_clk
- sunxi_mmc_card_power
- sunxi_mmc_set_ios
- sunxi_mmc_volt_switch
- sunxi_mmc_enable_sdio_irq
- sunxi_mmc_hw_reset
- sunxi_mmc_request
- sunxi_mmc_card_busy
- sunxi_mmc_enable
- sunxi_mmc_disable
- sunxi_mmc_resource_request
- sunxi_mmc_probe
- sunxi_mmc_remove
- sunxi_mmc_runtime_resume
- sunxi_mmc_runtime_suspend
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12 #include <linux/clk.h>
13 #include <linux/clk/sunxi-ng.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/mmc/card.h>
22 #include <linux/mmc/core.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/sd.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_platform.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/reset.h>
35 #include <linux/scatterlist.h>
36 #include <linux/slab.h>
37 #include <linux/spinlock.h>
38
39
40 #define SDXC_REG_GCTRL (0x00)
41 #define SDXC_REG_CLKCR (0x04)
42 #define SDXC_REG_TMOUT (0x08)
43 #define SDXC_REG_WIDTH (0x0C)
44 #define SDXC_REG_BLKSZ (0x10)
45 #define SDXC_REG_BCNTR (0x14)
46 #define SDXC_REG_CMDR (0x18)
47 #define SDXC_REG_CARG (0x1C)
48 #define SDXC_REG_RESP0 (0x20)
49 #define SDXC_REG_RESP1 (0x24)
50 #define SDXC_REG_RESP2 (0x28)
51 #define SDXC_REG_RESP3 (0x2C)
52 #define SDXC_REG_IMASK (0x30)
53 #define SDXC_REG_MISTA (0x34)
54 #define SDXC_REG_RINTR (0x38)
55 #define SDXC_REG_STAS (0x3C)
56 #define SDXC_REG_FTRGL (0x40)
57 #define SDXC_REG_FUNS (0x44)
58 #define SDXC_REG_CBCR (0x48)
59 #define SDXC_REG_BBCR (0x4C)
60 #define SDXC_REG_DBGC (0x50)
61 #define SDXC_REG_HWRST (0x78)
62 #define SDXC_REG_DMAC (0x80)
63 #define SDXC_REG_DLBA (0x84)
64 #define SDXC_REG_IDST (0x88)
65 #define SDXC_REG_IDIE (0x8C)
66 #define SDXC_REG_CHDA (0x90)
67 #define SDXC_REG_CBDA (0x94)
68
69
70 #define SDXC_REG_A12A 0x058
71 #define SDXC_REG_SD_NTSR 0x05C
72 #define SDXC_REG_DRV_DL 0x140
73 #define SDXC_REG_SAMP_DL_REG 0x144
74 #define SDXC_REG_DS_DL_REG 0x148
75
76 #define mmc_readl(host, reg) \
77 readl((host)->reg_base + SDXC_##reg)
78 #define mmc_writel(host, reg, value) \
79 writel((value), (host)->reg_base + SDXC_##reg)
80
81
82 #define SDXC_SOFT_RESET BIT(0)
83 #define SDXC_FIFO_RESET BIT(1)
84 #define SDXC_DMA_RESET BIT(2)
85 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
86 #define SDXC_DMA_ENABLE_BIT BIT(5)
87 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
88 #define SDXC_POSEDGE_LATCH_DATA BIT(9)
89 #define SDXC_DDR_MODE BIT(10)
90 #define SDXC_MEMORY_ACCESS_DONE BIT(29)
91 #define SDXC_ACCESS_DONE_DIRECT BIT(30)
92 #define SDXC_ACCESS_BY_AHB BIT(31)
93 #define SDXC_ACCESS_BY_DMA (0 << 31)
94 #define SDXC_HARDWARE_RESET \
95 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
96
97
98 #define SDXC_MASK_DATA0 BIT(31)
99 #define SDXC_CARD_CLOCK_ON BIT(16)
100 #define SDXC_LOW_POWER_ON BIT(17)
101
102
103 #define SDXC_WIDTH1 0
104 #define SDXC_WIDTH4 1
105 #define SDXC_WIDTH8 2
106
107
108 #define SDXC_RESP_EXPIRE BIT(6)
109 #define SDXC_LONG_RESPONSE BIT(7)
110 #define SDXC_CHECK_RESPONSE_CRC BIT(8)
111 #define SDXC_DATA_EXPIRE BIT(9)
112 #define SDXC_WRITE BIT(10)
113 #define SDXC_SEQUENCE_MODE BIT(11)
114 #define SDXC_SEND_AUTO_STOP BIT(12)
115 #define SDXC_WAIT_PRE_OVER BIT(13)
116 #define SDXC_STOP_ABORT_CMD BIT(14)
117 #define SDXC_SEND_INIT_SEQUENCE BIT(15)
118 #define SDXC_UPCLK_ONLY BIT(21)
119 #define SDXC_READ_CEATA_DEV BIT(22)
120 #define SDXC_CCS_EXPIRE BIT(23)
121 #define SDXC_ENABLE_BIT_BOOT BIT(24)
122 #define SDXC_ALT_BOOT_OPTIONS BIT(25)
123 #define SDXC_BOOT_ACK_EXPIRE BIT(26)
124 #define SDXC_BOOT_ABORT BIT(27)
125 #define SDXC_VOLTAGE_SWITCH BIT(28)
126 #define SDXC_USE_HOLD_REGISTER BIT(29)
127 #define SDXC_START BIT(31)
128
129
130 #define SDXC_RESP_ERROR BIT(1)
131 #define SDXC_COMMAND_DONE BIT(2)
132 #define SDXC_DATA_OVER BIT(3)
133 #define SDXC_TX_DATA_REQUEST BIT(4)
134 #define SDXC_RX_DATA_REQUEST BIT(5)
135 #define SDXC_RESP_CRC_ERROR BIT(6)
136 #define SDXC_DATA_CRC_ERROR BIT(7)
137 #define SDXC_RESP_TIMEOUT BIT(8)
138 #define SDXC_DATA_TIMEOUT BIT(9)
139 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
140 #define SDXC_FIFO_RUN_ERROR BIT(11)
141 #define SDXC_HARD_WARE_LOCKED BIT(12)
142 #define SDXC_START_BIT_ERROR BIT(13)
143 #define SDXC_AUTO_COMMAND_DONE BIT(14)
144 #define SDXC_END_BIT_ERROR BIT(15)
145 #define SDXC_SDIO_INTERRUPT BIT(16)
146 #define SDXC_CARD_INSERT BIT(30)
147 #define SDXC_CARD_REMOVE BIT(31)
148 #define SDXC_INTERRUPT_ERROR_BIT \
149 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
150 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
151 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
152 #define SDXC_INTERRUPT_DONE_BIT \
153 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
154 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
155
156
157 #define SDXC_RXWL_FLAG BIT(0)
158 #define SDXC_TXWL_FLAG BIT(1)
159 #define SDXC_FIFO_EMPTY BIT(2)
160 #define SDXC_FIFO_FULL BIT(3)
161 #define SDXC_CARD_PRESENT BIT(8)
162 #define SDXC_CARD_DATA_BUSY BIT(9)
163 #define SDXC_DATA_FSM_BUSY BIT(10)
164 #define SDXC_DMA_REQUEST BIT(31)
165 #define SDXC_FIFO_SIZE 16
166
167
168 #define SDXC_CEATA_ON (0xceaa << 16)
169 #define SDXC_SEND_IRQ_RESPONSE BIT(0)
170 #define SDXC_SDIO_READ_WAIT BIT(1)
171 #define SDXC_ABORT_READ_DATA BIT(2)
172 #define SDXC_SEND_CCSD BIT(8)
173 #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
174 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
175
176
177 #define SDXC_IDMAC_SOFT_RESET BIT(0)
178 #define SDXC_IDMAC_FIX_BURST BIT(1)
179 #define SDXC_IDMAC_IDMA_ON BIT(7)
180 #define SDXC_IDMAC_REFETCH_DES BIT(31)
181
182
183 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
184 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
185 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
186 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
187 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
188 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
189 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
190 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
191 #define SDXC_IDMAC_IDLE (0 << 13)
192 #define SDXC_IDMAC_SUSPEND (1 << 13)
193 #define SDXC_IDMAC_DESC_READ (2 << 13)
194 #define SDXC_IDMAC_DESC_CHECK (3 << 13)
195 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
196 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
197 #define SDXC_IDMAC_READ (6 << 13)
198 #define SDXC_IDMAC_WRITE (7 << 13)
199 #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
200
201
202
203
204
205
206
207
208 #define SDXC_IDMAC_DES0_DIC BIT(1)
209 #define SDXC_IDMAC_DES0_LD BIT(2)
210 #define SDXC_IDMAC_DES0_FD BIT(3)
211 #define SDXC_IDMAC_DES0_CH BIT(4)
212 #define SDXC_IDMAC_DES0_ER BIT(5)
213 #define SDXC_IDMAC_DES0_CES BIT(30)
214 #define SDXC_IDMAC_DES0_OWN BIT(31)
215
216 #define SDXC_CLK_400K 0
217 #define SDXC_CLK_25M 1
218 #define SDXC_CLK_50M 2
219 #define SDXC_CLK_50M_DDR 3
220 #define SDXC_CLK_50M_DDR_8BIT 4
221
222 #define SDXC_2X_TIMING_MODE BIT(31)
223
224 #define SDXC_CAL_START BIT(15)
225 #define SDXC_CAL_DONE BIT(14)
226 #define SDXC_CAL_DL_SHIFT 8
227 #define SDXC_CAL_DL_SW_EN BIT(7)
228 #define SDXC_CAL_DL_SW_SHIFT 0
229 #define SDXC_CAL_DL_MASK 0x3f
230
231 #define SDXC_CAL_TIMEOUT 3
232
233 struct sunxi_mmc_clk_delay {
234 u32 output;
235 u32 sample;
236 };
237
238 struct sunxi_idma_des {
239 __le32 config;
240 __le32 buf_size;
241 __le32 buf_addr_ptr1;
242 __le32 buf_addr_ptr2;
243 };
244
245 struct sunxi_mmc_cfg {
246 u32 idma_des_size_bits;
247 const struct sunxi_mmc_clk_delay *clk_delays;
248
249
250 bool can_calibrate;
251
252
253 bool mask_data0;
254
255
256
257
258
259
260
261 bool needs_new_timings;
262
263
264 bool ccu_has_timings_switch;
265 };
266
267 struct sunxi_mmc_host {
268 struct device *dev;
269 struct mmc_host *mmc;
270 struct reset_control *reset;
271 const struct sunxi_mmc_cfg *cfg;
272
273
274 void __iomem *reg_base;
275
276
277 struct clk *clk_ahb;
278 struct clk *clk_mmc;
279 struct clk *clk_sample;
280 struct clk *clk_output;
281
282
283 spinlock_t lock;
284 int irq;
285 u32 int_sum;
286 u32 sdio_imask;
287
288
289 dma_addr_t sg_dma;
290 void *sg_cpu;
291 bool wait_dma;
292
293 struct mmc_request *mrq;
294 struct mmc_request *manual_stop_mrq;
295 int ferror;
296
297
298 bool vqmmc_enabled;
299
300
301 bool use_new_timings;
302 };
303
304 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
305 {
306 unsigned long expire = jiffies + msecs_to_jiffies(250);
307 u32 rval;
308
309 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
310 do {
311 rval = mmc_readl(host, REG_GCTRL);
312 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
313
314 if (rval & SDXC_HARDWARE_RESET) {
315 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
316 return -EIO;
317 }
318
319 return 0;
320 }
321
322 static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
323 {
324 u32 rval;
325
326 if (sunxi_mmc_reset_host(host))
327 return -EIO;
328
329
330
331
332
333
334 mmc_writel(host, REG_FTRGL, 0x20070008);
335
336 mmc_writel(host, REG_TMOUT, 0xffffffff);
337
338 mmc_writel(host, REG_IMASK, host->sdio_imask);
339
340 mmc_writel(host, REG_RINTR, 0xffffffff);
341
342 mmc_writel(host, REG_DBGC, 0xdeb);
343
344 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
345
346 mmc_writel(host, REG_DLBA, host->sg_dma);
347
348 rval = mmc_readl(host, REG_GCTRL);
349 rval |= SDXC_INTERRUPT_ENABLE_BIT;
350
351 rval &= ~SDXC_ACCESS_DONE_DIRECT;
352 mmc_writel(host, REG_GCTRL, rval);
353
354 return 0;
355 }
356
357 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
358 struct mmc_data *data)
359 {
360 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
361 dma_addr_t next_desc = host->sg_dma;
362 int i, max_len = (1 << host->cfg->idma_des_size_bits);
363
364 for (i = 0; i < data->sg_len; i++) {
365 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
366 SDXC_IDMAC_DES0_OWN |
367 SDXC_IDMAC_DES0_DIC);
368
369 if (data->sg[i].length == max_len)
370 pdes[i].buf_size = 0;
371 else
372 pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
373
374 next_desc += sizeof(struct sunxi_idma_des);
375 pdes[i].buf_addr_ptr1 =
376 cpu_to_le32(sg_dma_address(&data->sg[i]));
377 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
378 }
379
380 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
381 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
382 SDXC_IDMAC_DES0_ER);
383 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
384 pdes[i - 1].buf_addr_ptr2 = 0;
385
386
387
388
389
390 wmb();
391 }
392
393 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
394 struct mmc_data *data)
395 {
396 u32 i, dma_len;
397 struct scatterlist *sg;
398
399 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
400 mmc_get_dma_dir(data));
401 if (dma_len == 0) {
402 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
403 return -ENOMEM;
404 }
405
406 for_each_sg(data->sg, sg, data->sg_len, i) {
407 if (sg->offset & 3 || sg->length & 3) {
408 dev_err(mmc_dev(host->mmc),
409 "unaligned scatterlist: os %x length %d\n",
410 sg->offset, sg->length);
411 return -EINVAL;
412 }
413 }
414
415 return 0;
416 }
417
418 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
419 struct mmc_data *data)
420 {
421 u32 rval;
422
423 sunxi_mmc_init_idma_des(host, data);
424
425 rval = mmc_readl(host, REG_GCTRL);
426 rval |= SDXC_DMA_ENABLE_BIT;
427 mmc_writel(host, REG_GCTRL, rval);
428 rval |= SDXC_DMA_RESET;
429 mmc_writel(host, REG_GCTRL, rval);
430
431 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
432
433 if (!(data->flags & MMC_DATA_WRITE))
434 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
435
436 mmc_writel(host, REG_DMAC,
437 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
438 }
439
440 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
441 struct mmc_request *req)
442 {
443 u32 arg, cmd_val, ri;
444 unsigned long expire = jiffies + msecs_to_jiffies(1000);
445
446 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
447 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
448
449 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
450 cmd_val |= SD_IO_RW_DIRECT;
451 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
452 ((req->cmd->arg >> 28) & 0x7);
453 } else {
454 cmd_val |= MMC_STOP_TRANSMISSION;
455 arg = 0;
456 }
457
458 mmc_writel(host, REG_CARG, arg);
459 mmc_writel(host, REG_CMDR, cmd_val);
460
461 do {
462 ri = mmc_readl(host, REG_RINTR);
463 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
464 time_before(jiffies, expire));
465
466 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
467 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
468 if (req->stop)
469 req->stop->resp[0] = -ETIMEDOUT;
470 } else {
471 if (req->stop)
472 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
473 }
474
475 mmc_writel(host, REG_RINTR, 0xffff);
476 }
477
478 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
479 {
480 struct mmc_command *cmd = host->mrq->cmd;
481 struct mmc_data *data = host->mrq->data;
482
483
484 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
485 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
486 cmd->opcode == SD_IO_RW_DIRECT))
487 return;
488
489 dev_dbg(mmc_dev(host->mmc),
490 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
491 host->mmc->index, cmd->opcode,
492 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
493 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
494 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
495 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
496 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
497 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
498 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
499 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
500 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
501 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
502 );
503 }
504
505
506 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
507 {
508 struct mmc_request *mrq = host->mrq;
509 struct mmc_data *data = mrq->data;
510 u32 rval;
511
512 mmc_writel(host, REG_IMASK, host->sdio_imask);
513 mmc_writel(host, REG_IDIE, 0);
514
515 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
516 sunxi_mmc_dump_errinfo(host);
517 mrq->cmd->error = -ETIMEDOUT;
518
519 if (data) {
520 data->error = -ETIMEDOUT;
521 host->manual_stop_mrq = mrq;
522 }
523
524 if (mrq->stop)
525 mrq->stop->error = -ETIMEDOUT;
526 } else {
527 if (mrq->cmd->flags & MMC_RSP_136) {
528 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
529 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
530 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
531 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
532 } else {
533 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
534 }
535
536 if (data)
537 data->bytes_xfered = data->blocks * data->blksz;
538 }
539
540 if (data) {
541 mmc_writel(host, REG_IDST, 0x337);
542 mmc_writel(host, REG_DMAC, 0);
543 rval = mmc_readl(host, REG_GCTRL);
544 rval |= SDXC_DMA_RESET;
545 mmc_writel(host, REG_GCTRL, rval);
546 rval &= ~SDXC_DMA_ENABLE_BIT;
547 mmc_writel(host, REG_GCTRL, rval);
548 rval |= SDXC_FIFO_RESET;
549 mmc_writel(host, REG_GCTRL, rval);
550 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
551 mmc_get_dma_dir(data));
552 }
553
554 mmc_writel(host, REG_RINTR, 0xffff);
555
556 host->mrq = NULL;
557 host->int_sum = 0;
558 host->wait_dma = false;
559
560 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
561 }
562
563 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
564 {
565 struct sunxi_mmc_host *host = dev_id;
566 struct mmc_request *mrq;
567 u32 msk_int, idma_int;
568 bool finalize = false;
569 bool sdio_int = false;
570 irqreturn_t ret = IRQ_HANDLED;
571
572 spin_lock(&host->lock);
573
574 idma_int = mmc_readl(host, REG_IDST);
575 msk_int = mmc_readl(host, REG_MISTA);
576
577 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
578 host->mrq, msk_int, idma_int);
579
580 mrq = host->mrq;
581 if (mrq) {
582 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
583 host->wait_dma = false;
584
585 host->int_sum |= msk_int;
586
587
588 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
589 !(host->int_sum & SDXC_COMMAND_DONE))
590 mmc_writel(host, REG_IMASK,
591 host->sdio_imask | SDXC_COMMAND_DONE);
592
593 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
594 finalize = true;
595 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
596 !host->wait_dma)
597 finalize = true;
598 }
599
600 if (msk_int & SDXC_SDIO_INTERRUPT)
601 sdio_int = true;
602
603 mmc_writel(host, REG_RINTR, msk_int);
604 mmc_writel(host, REG_IDST, idma_int);
605
606 if (finalize)
607 ret = sunxi_mmc_finalize_request(host);
608
609 spin_unlock(&host->lock);
610
611 if (finalize && ret == IRQ_HANDLED)
612 mmc_request_done(host->mmc, mrq);
613
614 if (sdio_int)
615 mmc_signal_sdio_irq(host->mmc);
616
617 return ret;
618 }
619
620 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
621 {
622 struct sunxi_mmc_host *host = dev_id;
623 struct mmc_request *mrq;
624 unsigned long iflags;
625
626 spin_lock_irqsave(&host->lock, iflags);
627 mrq = host->manual_stop_mrq;
628 spin_unlock_irqrestore(&host->lock, iflags);
629
630 if (!mrq) {
631 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
632 return IRQ_HANDLED;
633 }
634
635 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
636
637
638
639
640
641
642
643
644
645 sunxi_mmc_send_manual_stop(host, mrq);
646
647 spin_lock_irqsave(&host->lock, iflags);
648 host->manual_stop_mrq = NULL;
649 spin_unlock_irqrestore(&host->lock, iflags);
650
651 mmc_request_done(host->mmc, mrq);
652
653 return IRQ_HANDLED;
654 }
655
656 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
657 {
658 unsigned long expire = jiffies + msecs_to_jiffies(750);
659 u32 rval;
660
661 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
662 oclk_en ? "en" : "dis");
663
664 rval = mmc_readl(host, REG_CLKCR);
665 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
666
667 if (oclk_en)
668 rval |= SDXC_CARD_CLOCK_ON;
669 if (host->cfg->mask_data0)
670 rval |= SDXC_MASK_DATA0;
671
672 mmc_writel(host, REG_CLKCR, rval);
673
674 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
675 mmc_writel(host, REG_CMDR, rval);
676
677 do {
678 rval = mmc_readl(host, REG_CMDR);
679 } while (time_before(jiffies, expire) && (rval & SDXC_START));
680
681
682 mmc_writel(host, REG_RINTR,
683 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
684
685 if (rval & SDXC_START) {
686 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
687 return -EIO;
688 }
689
690 if (host->cfg->mask_data0) {
691 rval = mmc_readl(host, REG_CLKCR);
692 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
693 }
694
695 return 0;
696 }
697
698 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
699 {
700 if (!host->cfg->can_calibrate)
701 return 0;
702
703
704
705
706
707
708
709
710
711
712 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
713
714 return 0;
715 }
716
717 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
718 struct mmc_ios *ios, u32 rate)
719 {
720 int index;
721
722
723 if (host->use_new_timings)
724 return 0;
725
726
727 if (!host->cfg->clk_delays)
728 return 0;
729
730
731 if (rate <= 400000) {
732 index = SDXC_CLK_400K;
733 } else if (rate <= 25000000) {
734 index = SDXC_CLK_25M;
735 } else if (rate <= 52000000) {
736 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
737 ios->timing != MMC_TIMING_MMC_DDR52) {
738 index = SDXC_CLK_50M;
739 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
740 index = SDXC_CLK_50M_DDR_8BIT;
741 } else {
742 index = SDXC_CLK_50M_DDR;
743 }
744 } else {
745 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
746 return -EINVAL;
747 }
748
749 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
750 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
751
752 return 0;
753 }
754
755 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
756 struct mmc_ios *ios)
757 {
758 struct mmc_host *mmc = host->mmc;
759 long rate;
760 u32 rval, clock = ios->clock, div = 1;
761 int ret;
762
763 ret = sunxi_mmc_oclk_onoff(host, 0);
764 if (ret)
765 return ret;
766
767
768 mmc->actual_clock = 0;
769
770 if (!ios->clock)
771 return 0;
772
773
774
775
776
777
778
779
780
781
782 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
783 (host->use_new_timings ||
784 ios->bus_width == MMC_BUS_WIDTH_8)) {
785 div = 2;
786 clock <<= 1;
787 }
788
789 if (host->use_new_timings && host->cfg->ccu_has_timings_switch) {
790 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
791 if (ret) {
792 dev_err(mmc_dev(mmc),
793 "error setting new timing mode\n");
794 return ret;
795 }
796 }
797
798 rate = clk_round_rate(host->clk_mmc, clock);
799 if (rate < 0) {
800 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
801 clock, rate);
802 return rate;
803 }
804 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
805 clock, rate);
806
807
808 ret = clk_set_rate(host->clk_mmc, rate);
809 if (ret) {
810 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
811 rate, ret);
812 return ret;
813 }
814
815
816 rval = mmc_readl(host, REG_CLKCR);
817 rval &= ~0xff;
818 rval |= div - 1;
819 mmc_writel(host, REG_CLKCR, rval);
820
821
822 rate /= div;
823
824
825
826
827
828
829
830 if (host->use_new_timings) {
831
832 rval = mmc_readl(host, REG_SD_NTSR);
833 rval |= SDXC_2X_TIMING_MODE;
834 mmc_writel(host, REG_SD_NTSR, rval);
835 }
836
837
838 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
839 if (ret)
840 return ret;
841
842 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
843 if (ret)
844 return ret;
845
846
847
848
849
850
851
852
853
854 ret = sunxi_mmc_oclk_onoff(host, 1);
855 if (ret)
856 return ret;
857
858
859 mmc->actual_clock = rate;
860
861 return 0;
862 }
863
864 static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,
865 unsigned char width)
866 {
867 switch (width) {
868 case MMC_BUS_WIDTH_1:
869 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
870 break;
871 case MMC_BUS_WIDTH_4:
872 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
873 break;
874 case MMC_BUS_WIDTH_8:
875 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
876 break;
877 }
878 }
879
880 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
881 {
882 u32 rval;
883
884
885 rval = mmc_readl(host, REG_GCTRL);
886 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
887 ios->timing == MMC_TIMING_MMC_DDR52)
888 rval |= SDXC_DDR_MODE;
889 else
890 rval &= ~SDXC_DDR_MODE;
891 mmc_writel(host, REG_GCTRL, rval);
892
893 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
894
895 }
896
897 static void sunxi_mmc_card_power(struct sunxi_mmc_host *host,
898 struct mmc_ios *ios)
899 {
900 struct mmc_host *mmc = host->mmc;
901
902 switch (ios->power_mode) {
903 case MMC_POWER_UP:
904 dev_dbg(mmc_dev(mmc), "Powering card up\n");
905
906 if (!IS_ERR(mmc->supply.vmmc)) {
907 host->ferror = mmc_regulator_set_ocr(mmc,
908 mmc->supply.vmmc,
909 ios->vdd);
910 if (host->ferror)
911 return;
912 }
913
914 if (!IS_ERR(mmc->supply.vqmmc)) {
915 host->ferror = regulator_enable(mmc->supply.vqmmc);
916 if (host->ferror) {
917 dev_err(mmc_dev(mmc),
918 "failed to enable vqmmc\n");
919 return;
920 }
921 host->vqmmc_enabled = true;
922 }
923 break;
924
925 case MMC_POWER_OFF:
926 dev_dbg(mmc_dev(mmc), "Powering card off\n");
927
928 if (!IS_ERR(mmc->supply.vmmc))
929 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
930
931 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
932 regulator_disable(mmc->supply.vqmmc);
933
934 host->vqmmc_enabled = false;
935 break;
936
937 default:
938 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n");
939 break;
940 }
941 }
942
943 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
944 {
945 struct sunxi_mmc_host *host = mmc_priv(mmc);
946
947 sunxi_mmc_card_power(host, ios);
948 sunxi_mmc_set_bus_width(host, ios->bus_width);
949 sunxi_mmc_set_clk(host, ios);
950 }
951
952 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
953 {
954
955 if (!IS_ERR(mmc->supply.vqmmc))
956 return mmc_regulator_set_vqmmc(mmc, ios);
957
958
959 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
960 return 0;
961
962 return -EINVAL;
963 }
964
965 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
966 {
967 struct sunxi_mmc_host *host = mmc_priv(mmc);
968 unsigned long flags;
969 u32 imask;
970
971 if (enable)
972 pm_runtime_get_noresume(host->dev);
973
974 spin_lock_irqsave(&host->lock, flags);
975
976 imask = mmc_readl(host, REG_IMASK);
977 if (enable) {
978 host->sdio_imask = SDXC_SDIO_INTERRUPT;
979 imask |= SDXC_SDIO_INTERRUPT;
980 } else {
981 host->sdio_imask = 0;
982 imask &= ~SDXC_SDIO_INTERRUPT;
983 }
984 mmc_writel(host, REG_IMASK, imask);
985 spin_unlock_irqrestore(&host->lock, flags);
986
987 if (!enable)
988 pm_runtime_put_noidle(host->mmc->parent);
989 }
990
991 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
992 {
993 struct sunxi_mmc_host *host = mmc_priv(mmc);
994 mmc_writel(host, REG_HWRST, 0);
995 udelay(10);
996 mmc_writel(host, REG_HWRST, 1);
997 udelay(300);
998 }
999
1000 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1001 {
1002 struct sunxi_mmc_host *host = mmc_priv(mmc);
1003 struct mmc_command *cmd = mrq->cmd;
1004 struct mmc_data *data = mrq->data;
1005 unsigned long iflags;
1006 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
1007 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
1008 bool wait_dma = host->wait_dma;
1009 int ret;
1010
1011
1012 if (host->ferror) {
1013 mrq->cmd->error = host->ferror;
1014 mmc_request_done(mmc, mrq);
1015 return;
1016 }
1017
1018 if (data) {
1019 ret = sunxi_mmc_map_dma(host, data);
1020 if (ret < 0) {
1021 dev_err(mmc_dev(mmc), "map DMA failed\n");
1022 cmd->error = ret;
1023 data->error = ret;
1024 mmc_request_done(mmc, mrq);
1025 return;
1026 }
1027 }
1028
1029 if (cmd->opcode == MMC_GO_IDLE_STATE) {
1030 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
1031 imask |= SDXC_COMMAND_DONE;
1032 }
1033
1034 if (cmd->flags & MMC_RSP_PRESENT) {
1035 cmd_val |= SDXC_RESP_EXPIRE;
1036 if (cmd->flags & MMC_RSP_136)
1037 cmd_val |= SDXC_LONG_RESPONSE;
1038 if (cmd->flags & MMC_RSP_CRC)
1039 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
1040
1041 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
1042 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
1043
1044 if (cmd->data->stop) {
1045 imask |= SDXC_AUTO_COMMAND_DONE;
1046 cmd_val |= SDXC_SEND_AUTO_STOP;
1047 } else {
1048 imask |= SDXC_DATA_OVER;
1049 }
1050
1051 if (cmd->data->flags & MMC_DATA_WRITE)
1052 cmd_val |= SDXC_WRITE;
1053 else
1054 wait_dma = true;
1055 } else {
1056 imask |= SDXC_COMMAND_DONE;
1057 }
1058 } else {
1059 imask |= SDXC_COMMAND_DONE;
1060 }
1061
1062 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1063 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1064 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1065
1066 spin_lock_irqsave(&host->lock, iflags);
1067
1068 if (host->mrq || host->manual_stop_mrq) {
1069 spin_unlock_irqrestore(&host->lock, iflags);
1070
1071 if (data)
1072 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1073 mmc_get_dma_dir(data));
1074
1075 dev_err(mmc_dev(mmc), "request already pending\n");
1076 mrq->cmd->error = -EBUSY;
1077 mmc_request_done(mmc, mrq);
1078 return;
1079 }
1080
1081 if (data) {
1082 mmc_writel(host, REG_BLKSZ, data->blksz);
1083 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1084 sunxi_mmc_start_dma(host, data);
1085 }
1086
1087 host->mrq = mrq;
1088 host->wait_dma = wait_dma;
1089 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1090 mmc_writel(host, REG_CARG, cmd->arg);
1091 mmc_writel(host, REG_CMDR, cmd_val);
1092
1093 spin_unlock_irqrestore(&host->lock, iflags);
1094 }
1095
1096 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1097 {
1098 struct sunxi_mmc_host *host = mmc_priv(mmc);
1099
1100 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1101 }
1102
1103 static const struct mmc_host_ops sunxi_mmc_ops = {
1104 .request = sunxi_mmc_request,
1105 .set_ios = sunxi_mmc_set_ios,
1106 .get_ro = mmc_gpio_get_ro,
1107 .get_cd = mmc_gpio_get_cd,
1108 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1109 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1110 .hw_reset = sunxi_mmc_hw_reset,
1111 .card_busy = sunxi_mmc_card_busy,
1112 };
1113
1114 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1115 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1116 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1117 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1118 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
1119
1120 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
1121 };
1122
1123 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1124 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1125 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1126 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
1127 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1128 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
1129 };
1130
1131 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1132 .idma_des_size_bits = 13,
1133 .clk_delays = NULL,
1134 .can_calibrate = false,
1135 };
1136
1137 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1138 .idma_des_size_bits = 16,
1139 .clk_delays = NULL,
1140 .can_calibrate = false,
1141 };
1142
1143 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1144 .idma_des_size_bits = 16,
1145 .clk_delays = sunxi_mmc_clk_delays,
1146 .can_calibrate = false,
1147 };
1148
1149 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
1150 .idma_des_size_bits = 16,
1151 .clk_delays = sunxi_mmc_clk_delays,
1152 .can_calibrate = false,
1153 .ccu_has_timings_switch = true,
1154 };
1155
1156 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1157 .idma_des_size_bits = 16,
1158 .clk_delays = sun9i_mmc_clk_delays,
1159 .can_calibrate = false,
1160 };
1161
1162 static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1163 .idma_des_size_bits = 16,
1164 .clk_delays = NULL,
1165 .can_calibrate = true,
1166 .mask_data0 = true,
1167 .needs_new_timings = true,
1168 };
1169
1170 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1171 .idma_des_size_bits = 13,
1172 .clk_delays = NULL,
1173 .can_calibrate = true,
1174 .needs_new_timings = true,
1175 };
1176
1177 static const struct of_device_id sunxi_mmc_of_match[] = {
1178 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1179 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1180 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1181 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
1182 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1183 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1184 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1185 { }
1186 };
1187 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1188
1189 static int sunxi_mmc_enable(struct sunxi_mmc_host *host)
1190 {
1191 int ret;
1192
1193 if (!IS_ERR(host->reset)) {
1194 ret = reset_control_reset(host->reset);
1195 if (ret) {
1196 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",
1197 ret);
1198 return ret;
1199 }
1200 }
1201
1202 ret = clk_prepare_enable(host->clk_ahb);
1203 if (ret) {
1204 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);
1205 goto error_assert_reset;
1206 }
1207
1208 ret = clk_prepare_enable(host->clk_mmc);
1209 if (ret) {
1210 dev_err(host->dev, "Enable mmc clk err %d\n", ret);
1211 goto error_disable_clk_ahb;
1212 }
1213
1214 ret = clk_prepare_enable(host->clk_output);
1215 if (ret) {
1216 dev_err(host->dev, "Enable output clk err %d\n", ret);
1217 goto error_disable_clk_mmc;
1218 }
1219
1220 ret = clk_prepare_enable(host->clk_sample);
1221 if (ret) {
1222 dev_err(host->dev, "Enable sample clk err %d\n", ret);
1223 goto error_disable_clk_output;
1224 }
1225
1226
1227
1228
1229
1230 ret = sunxi_mmc_reset_host(host);
1231 if (ret)
1232 goto error_disable_clk_sample;
1233
1234 return 0;
1235
1236 error_disable_clk_sample:
1237 clk_disable_unprepare(host->clk_sample);
1238 error_disable_clk_output:
1239 clk_disable_unprepare(host->clk_output);
1240 error_disable_clk_mmc:
1241 clk_disable_unprepare(host->clk_mmc);
1242 error_disable_clk_ahb:
1243 clk_disable_unprepare(host->clk_ahb);
1244 error_assert_reset:
1245 if (!IS_ERR(host->reset))
1246 reset_control_assert(host->reset);
1247 return ret;
1248 }
1249
1250 static void sunxi_mmc_disable(struct sunxi_mmc_host *host)
1251 {
1252 sunxi_mmc_reset_host(host);
1253
1254 clk_disable_unprepare(host->clk_sample);
1255 clk_disable_unprepare(host->clk_output);
1256 clk_disable_unprepare(host->clk_mmc);
1257 clk_disable_unprepare(host->clk_ahb);
1258
1259 if (!IS_ERR(host->reset))
1260 reset_control_assert(host->reset);
1261 }
1262
1263 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1264 struct platform_device *pdev)
1265 {
1266 int ret;
1267
1268 host->cfg = of_device_get_match_data(&pdev->dev);
1269 if (!host->cfg)
1270 return -EINVAL;
1271
1272 ret = mmc_regulator_get_supply(host->mmc);
1273 if (ret)
1274 return ret;
1275
1276 host->reg_base = devm_ioremap_resource(&pdev->dev,
1277 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1278 if (IS_ERR(host->reg_base))
1279 return PTR_ERR(host->reg_base);
1280
1281 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1282 if (IS_ERR(host->clk_ahb)) {
1283 dev_err(&pdev->dev, "Could not get ahb clock\n");
1284 return PTR_ERR(host->clk_ahb);
1285 }
1286
1287 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1288 if (IS_ERR(host->clk_mmc)) {
1289 dev_err(&pdev->dev, "Could not get mmc clock\n");
1290 return PTR_ERR(host->clk_mmc);
1291 }
1292
1293 if (host->cfg->clk_delays) {
1294 host->clk_output = devm_clk_get(&pdev->dev, "output");
1295 if (IS_ERR(host->clk_output)) {
1296 dev_err(&pdev->dev, "Could not get output clock\n");
1297 return PTR_ERR(host->clk_output);
1298 }
1299
1300 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1301 if (IS_ERR(host->clk_sample)) {
1302 dev_err(&pdev->dev, "Could not get sample clock\n");
1303 return PTR_ERR(host->clk_sample);
1304 }
1305 }
1306
1307 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1308 "ahb");
1309 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1310 return PTR_ERR(host->reset);
1311
1312 ret = sunxi_mmc_enable(host);
1313 if (ret)
1314 return ret;
1315
1316 host->irq = platform_get_irq(pdev, 0);
1317 if (host->irq <= 0) {
1318 ret = -EINVAL;
1319 goto error_disable_mmc;
1320 }
1321
1322 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1323 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1324
1325 error_disable_mmc:
1326 sunxi_mmc_disable(host);
1327 return ret;
1328 }
1329
1330 static int sunxi_mmc_probe(struct platform_device *pdev)
1331 {
1332 struct sunxi_mmc_host *host;
1333 struct mmc_host *mmc;
1334 int ret;
1335
1336 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1337 if (!mmc) {
1338 dev_err(&pdev->dev, "mmc alloc host failed\n");
1339 return -ENOMEM;
1340 }
1341 platform_set_drvdata(pdev, mmc);
1342
1343 host = mmc_priv(mmc);
1344 host->dev = &pdev->dev;
1345 host->mmc = mmc;
1346 spin_lock_init(&host->lock);
1347
1348 ret = sunxi_mmc_resource_request(host, pdev);
1349 if (ret)
1350 goto error_free_host;
1351
1352 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1353 &host->sg_dma, GFP_KERNEL);
1354 if (!host->sg_cpu) {
1355 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1356 ret = -ENOMEM;
1357 goto error_free_host;
1358 }
1359
1360 if (host->cfg->ccu_has_timings_switch) {
1361
1362
1363
1364
1365 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
1366
1367
1368 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
1369 if (ret < 0) {
1370
1371
1372
1373
1374 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
1375 host->use_new_timings = false;
1376 } else {
1377 host->use_new_timings = !!ret;
1378 }
1379 } else if (host->cfg->needs_new_timings) {
1380
1381 host->use_new_timings = true;
1382 }
1383
1384 mmc->ops = &sunxi_mmc_ops;
1385 mmc->max_blk_count = 8192;
1386 mmc->max_blk_size = 4096;
1387 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1388 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
1389 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
1390
1391 mmc->f_min = 400000;
1392 mmc->f_max = 52000000;
1393 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1394 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1395
1396
1397
1398
1399
1400
1401
1402
1403 if ((host->cfg->clk_delays || host->use_new_timings) &&
1404 !of_device_is_compatible(pdev->dev.of_node,
1405 "allwinner,sun50i-h5-emmc"))
1406 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1407
1408 ret = mmc_of_parse(mmc);
1409 if (ret)
1410 goto error_free_dma;
1411
1412
1413
1414
1415
1416
1417
1418 if (!(host->cfg->clk_delays || host->use_new_timings)) {
1419 mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR |
1420 MMC_CAP_1_2V_DDR | MMC_CAP_UHS);
1421 mmc->caps2 &= ~MMC_CAP2_HS200;
1422 }
1423
1424
1425 mmc->caps2 &= ~MMC_CAP2_HS400;
1426
1427 ret = sunxi_mmc_init_host(host);
1428 if (ret)
1429 goto error_free_dma;
1430
1431 pm_runtime_set_active(&pdev->dev);
1432 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1433 pm_runtime_use_autosuspend(&pdev->dev);
1434 pm_runtime_enable(&pdev->dev);
1435
1436 ret = mmc_add_host(mmc);
1437 if (ret)
1438 goto error_free_dma;
1439
1440 dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n",
1441 mmc->max_req_size >> 10,
1442 host->use_new_timings ? ", uses new timings mode" : "");
1443
1444 return 0;
1445
1446 error_free_dma:
1447 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1448 error_free_host:
1449 mmc_free_host(mmc);
1450 return ret;
1451 }
1452
1453 static int sunxi_mmc_remove(struct platform_device *pdev)
1454 {
1455 struct mmc_host *mmc = platform_get_drvdata(pdev);
1456 struct sunxi_mmc_host *host = mmc_priv(mmc);
1457
1458 mmc_remove_host(mmc);
1459 pm_runtime_force_suspend(&pdev->dev);
1460 disable_irq(host->irq);
1461 sunxi_mmc_disable(host);
1462 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1463 mmc_free_host(mmc);
1464
1465 return 0;
1466 }
1467
1468 #ifdef CONFIG_PM
1469 static int sunxi_mmc_runtime_resume(struct device *dev)
1470 {
1471 struct mmc_host *mmc = dev_get_drvdata(dev);
1472 struct sunxi_mmc_host *host = mmc_priv(mmc);
1473 int ret;
1474
1475 ret = sunxi_mmc_enable(host);
1476 if (ret)
1477 return ret;
1478
1479 sunxi_mmc_init_host(host);
1480 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
1481 sunxi_mmc_set_clk(host, &mmc->ios);
1482 enable_irq(host->irq);
1483
1484 return 0;
1485 }
1486
1487 static int sunxi_mmc_runtime_suspend(struct device *dev)
1488 {
1489 struct mmc_host *mmc = dev_get_drvdata(dev);
1490 struct sunxi_mmc_host *host = mmc_priv(mmc);
1491
1492
1493
1494
1495
1496
1497 disable_irq(host->irq);
1498 sunxi_mmc_reset_host(host);
1499 sunxi_mmc_disable(host);
1500
1501 return 0;
1502 }
1503 #endif
1504
1505 static const struct dev_pm_ops sunxi_mmc_pm_ops = {
1506 SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
1507 sunxi_mmc_runtime_resume,
1508 NULL)
1509 };
1510
1511 static struct platform_driver sunxi_mmc_driver = {
1512 .driver = {
1513 .name = "sunxi-mmc",
1514 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1515 .pm = &sunxi_mmc_pm_ops,
1516 },
1517 .probe = sunxi_mmc_probe,
1518 .remove = sunxi_mmc_remove,
1519 };
1520 module_platform_driver(sunxi_mmc_driver);
1521
1522 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1523 MODULE_LICENSE("GPL v2");
1524 MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
1525 MODULE_ALIAS("platform:sunxi-mmc");