root/drivers/mmc/host/sdhci-of-at91.c

DEFINITIONS

1. sdhci_at91_set_force_card_detect
2. sdhci_at91_set_clock
3. sdhci_at91_set_power
4. sdhci_at91_set_uhs_signaling
5. sdhci_at91_reset
6. sdhci_at91_set_clks_presets
7. sdhci_at91_suspend
8. sdhci_at91_runtime_suspend
9. sdhci_at91_runtime_resume
10. sdhci_at91_probe
11. sdhci_at91_remove

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Atmel SDMMC controller driver.
   4  *
   5  * Copyright (C) 2015 Atmel,
   6  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   7  */
   8 
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mmc/host.h>
  15 #include <linux/mmc/slot-gpio.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pm.h>
  20 #include <linux/pm_runtime.h>
  21 
  22 #include "sdhci-pltfm.h"
  23 
  24 #define SDMMC_MC1R      0x204
  25 #define         SDMMC_MC1R_DDR          BIT(3)
  26 #define         SDMMC_MC1R_FCD          BIT(7)
  27 #define SDMMC_CACR      0x230
  28 #define         SDMMC_CACR_CAPWREN      BIT(0)
  29 #define         SDMMC_CACR_KEY          (0x46 << 8)
  30 
  31 #define SDHCI_AT91_PRESET_COMMON_CONF   0x400 /* drv type B, programmable clock mode */
  32 
  33 struct sdhci_at91_priv {
  34         struct clk *hclock;
  35         struct clk *gck;
  36         struct clk *mainck;
  37         bool restore_needed;
  38 };
  39 
  40 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
  41 {
  42         u8 mc1r;
  43 
  44         mc1r = readb(host->ioaddr + SDMMC_MC1R);
  45         mc1r |= SDMMC_MC1R_FCD;
  46         writeb(mc1r, host->ioaddr + SDMMC_MC1R);
  47 }
  48 
  49 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
  50 {
  51         u16 clk;
  52         unsigned long timeout;
  53 
  54         host->mmc->actual_clock = 0;
  55 
  56         /*
  57          * There is no requirement to disable the internal clock before
  58          * changing the SD clock configuration. Moreover, disabling the
  59          * internal clock, changing the configuration and re-enabling the
  60          * internal clock causes some bugs. It can prevent to get the internal
  61          * clock stable flag ready and an unexpected switch to the base clock
  62          * when using presets.
  63          */
  64         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  65         clk &= SDHCI_CLOCK_INT_EN;
  66         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  67 
  68         if (clock == 0)
  69                 return;
  70 
  71         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
  72 
  73         clk |= SDHCI_CLOCK_INT_EN;
  74         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  75 
  76         /* Wait max 20 ms */
  77         timeout = 20;
  78         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  79                 & SDHCI_CLOCK_INT_STABLE)) {
  80                 if (timeout == 0) {
  81                         pr_err("%s: Internal clock never stabilised.\n",
  82                                mmc_hostname(host->mmc));
  83                         return;
  84                 }
  85                 timeout--;
  86                 mdelay(1);
  87         }
  88 
  89         clk |= SDHCI_CLOCK_CARD_EN;
  90         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  91 }
  92 
  93 /*
  94  * In this specific implementation of the SDHCI controller, the power register
  95  * needs to have a valid voltage set even when the power supply is managed by
  96  * an external regulator.
  97  */
  98 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
  99                      unsigned short vdd)
 100 {
 101         if (!IS_ERR(host->mmc->supply.vmmc)) {
 102                 struct mmc_host *mmc = host->mmc;
 103 
 104                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 105         }
 106         sdhci_set_power_noreg(host, mode, vdd);
 107 }
 108 
 109 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
 110                                          unsigned int timing)
 111 {
 112         if (timing == MMC_TIMING_MMC_DDR52)
 113                 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
 114         sdhci_set_uhs_signaling(host, timing);
 115 }
 116 
 117 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
 118 {
 119         sdhci_reset(host, mask);
 120 
 121         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
 122             || mmc_gpio_get_cd(host->mmc) >= 0)
 123                 sdhci_at91_set_force_card_detect(host);
 124 }
 125 
 126 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
 127         .set_clock              = sdhci_at91_set_clock,
 128         .set_bus_width          = sdhci_set_bus_width,
 129         .reset                  = sdhci_at91_reset,
 130         .set_uhs_signaling      = sdhci_at91_set_uhs_signaling,
 131         .set_power              = sdhci_at91_set_power,
 132 };
 133 
 134 static const struct sdhci_pltfm_data soc_data_sama5d2 = {
 135         .ops = &sdhci_at91_sama5d2_ops,
 136 };
 137 
 138 static const struct of_device_id sdhci_at91_dt_match[] = {
 139         { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
 140         {}
 141 };
 142 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
 143 
 144 static int sdhci_at91_set_clks_presets(struct device *dev)
 145 {
 146         struct sdhci_host *host = dev_get_drvdata(dev);
 147         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 148         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 149         int ret;
 150         unsigned int                    caps0, caps1;
 151         unsigned int                    clk_base, clk_mul;
 152         unsigned int                    gck_rate, real_gck_rate;
 153         unsigned int                    preset_div;
 154 
 155         /*
 156          * The mult clock is provided by as a generated clock by the PMC
 157          * controller. In order to set the rate of gck, we have to get the
 158          * base clock rate and the clock mult from capabilities.
 159          */
 160         clk_prepare_enable(priv->hclock);
 161         caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
 162         caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
 163         clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
 164         clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
 165         gck_rate = clk_base * 1000000 * (clk_mul + 1);
 166         ret = clk_set_rate(priv->gck, gck_rate);
 167         if (ret < 0) {
 168                 dev_err(dev, "failed to set gck");
 169                 clk_disable_unprepare(priv->hclock);
 170                 return ret;
 171         }
 172         /*
 173          * We need to check if we have the requested rate for gck because in
 174          * some cases this rate could be not supported. If it happens, the rate
 175          * is the closest one gck can provide. We have to update the value
 176          * of clk mul.
 177          */
 178         real_gck_rate = clk_get_rate(priv->gck);
 179         if (real_gck_rate != gck_rate) {
 180                 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
 181                 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
 182                 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) &
 183                           SDHCI_CLOCK_MUL_MASK);
 184                 /* Set capabilities in r/w mode. */
 185                 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN,
 186                        host->ioaddr + SDMMC_CACR);
 187                 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
 188                 /* Set capabilities in ro mode. */
 189                 writel(0, host->ioaddr + SDMMC_CACR);
 190                 dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n",
 191                          clk_mul, real_gck_rate);
 192         }
 193 
 194         /*
 195          * We have to set preset values because it depends on the clk_mul
 196          * value. Moreover, SDR104 is supported in a degraded mode since the
 197          * maximum sd clock value is 120 MHz instead of 208 MHz. For that
 198          * reason, we need to use presets to support SDR104.
 199          */
 200         preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
 201         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 202                host->ioaddr + SDHCI_PRESET_FOR_SDR12);
 203         preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
 204         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 205                host->ioaddr + SDHCI_PRESET_FOR_SDR25);
 206         preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
 207         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 208                host->ioaddr + SDHCI_PRESET_FOR_SDR50);
 209         preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
 210         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 211                host->ioaddr + SDHCI_PRESET_FOR_SDR104);
 212         preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
 213         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 214                host->ioaddr + SDHCI_PRESET_FOR_DDR50);
 215 
 216         clk_prepare_enable(priv->mainck);
 217         clk_prepare_enable(priv->gck);
 218 
 219         return 0;
 220 }
 221 
 222 #ifdef CONFIG_PM_SLEEP
 223 static int sdhci_at91_suspend(struct device *dev)
 224 {
 225         struct sdhci_host *host = dev_get_drvdata(dev);
 226         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 227         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 228         int ret;
 229 
 230         ret = pm_runtime_force_suspend(dev);
 231 
 232         priv->restore_needed = true;
 233 
 234         return ret;
 235 }
 236 #endif /* CONFIG_PM_SLEEP */
 237 
 238 #ifdef CONFIG_PM
 239 static int sdhci_at91_runtime_suspend(struct device *dev)
 240 {
 241         struct sdhci_host *host = dev_get_drvdata(dev);
 242         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 243         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 244         int ret;
 245 
 246         ret = sdhci_runtime_suspend_host(host);
 247 
 248         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 249                 mmc_retune_needed(host->mmc);
 250 
 251         clk_disable_unprepare(priv->gck);
 252         clk_disable_unprepare(priv->hclock);
 253         clk_disable_unprepare(priv->mainck);
 254 
 255         return ret;
 256 }
 257 
 258 static int sdhci_at91_runtime_resume(struct device *dev)
 259 {
 260         struct sdhci_host *host = dev_get_drvdata(dev);
 261         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 262         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 263         int ret;
 264 
 265         if (priv->restore_needed) {
 266                 ret = sdhci_at91_set_clks_presets(dev);
 267                 if (ret)
 268                         return ret;
 269 
 270                 priv->restore_needed = false;
 271                 goto out;
 272         }
 273 
 274         ret = clk_prepare_enable(priv->mainck);
 275         if (ret) {
 276                 dev_err(dev, "can't enable mainck\n");
 277                 return ret;
 278         }
 279 
 280         ret = clk_prepare_enable(priv->hclock);
 281         if (ret) {
 282                 dev_err(dev, "can't enable hclock\n");
 283                 return ret;
 284         }
 285 
 286         ret = clk_prepare_enable(priv->gck);
 287         if (ret) {
 288                 dev_err(dev, "can't enable gck\n");
 289                 return ret;
 290         }
 291 
 292 out:
 293         return sdhci_runtime_resume_host(host, 0);
 294 }
 295 #endif /* CONFIG_PM */
 296 
 297 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
 298         SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
 299         SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
 300                            sdhci_at91_runtime_resume,
 301                            NULL)
 302 };
 303 
 304 static int sdhci_at91_probe(struct platform_device *pdev)
 305 {
 306         const struct of_device_id       *match;
 307         const struct sdhci_pltfm_data   *soc_data;
 308         struct sdhci_host               *host;
 309         struct sdhci_pltfm_host         *pltfm_host;
 310         struct sdhci_at91_priv          *priv;
 311         int                             ret;
 312 
 313         match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
 314         if (!match)
 315                 return -EINVAL;
 316         soc_data = match->data;
 317 
 318         host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
 319         if (IS_ERR(host))
 320                 return PTR_ERR(host);
 321 
 322         pltfm_host = sdhci_priv(host);
 323         priv = sdhci_pltfm_priv(pltfm_host);
 324 
 325         priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
 326         if (IS_ERR(priv->mainck)) {
 327                 dev_err(&pdev->dev, "failed to get baseclk\n");
 328                 ret = PTR_ERR(priv->mainck);
 329                 goto sdhci_pltfm_free;
 330         }
 331 
 332         priv->hclock = devm_clk_get(&pdev->dev, "hclock");
 333         if (IS_ERR(priv->hclock)) {
 334                 dev_err(&pdev->dev, "failed to get hclock\n");
 335                 ret = PTR_ERR(priv->hclock);
 336                 goto sdhci_pltfm_free;
 337         }
 338 
 339         priv->gck = devm_clk_get(&pdev->dev, "multclk");
 340         if (IS_ERR(priv->gck)) {
 341                 dev_err(&pdev->dev, "failed to get multclk\n");
 342                 ret = PTR_ERR(priv->gck);
 343                 goto sdhci_pltfm_free;
 344         }
 345 
 346         ret = sdhci_at91_set_clks_presets(&pdev->dev);
 347         if (ret)
 348                 goto sdhci_pltfm_free;
 349 
 350         priv->restore_needed = false;
 351 
 352         ret = mmc_of_parse(host->mmc);
 353         if (ret)
 354                 goto clocks_disable_unprepare;
 355 
 356         sdhci_get_of_property(pdev);
 357 
 358         pm_runtime_get_noresume(&pdev->dev);
 359         pm_runtime_set_active(&pdev->dev);
 360         pm_runtime_enable(&pdev->dev);
 361         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 362         pm_runtime_use_autosuspend(&pdev->dev);
 363 
 364         /* HS200 is broken at this moment */
 365         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
 366 
 367         ret = sdhci_add_host(host);
 368         if (ret)
 369                 goto pm_runtime_disable;
 370 
 371         /*
 372          * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
 373          * the assumption that all the clocks of the controller are disabled.
 374          * It means we can't get irq from it when it is runtime suspended.
 375          * For that reason, it is not planned to wake-up on a card detect irq
 376          * from the controller.
 377          * If we want to use runtime PM and to be able to wake-up on card
 378          * insertion, we have to use a GPIO for the card detection or we can
 379          * use polling. Be aware that using polling will resume/suspend the
 380          * controller between each attempt.
 381          * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
 382          * to enable polling via device tree with broken-cd property.
 383          */
 384         if (mmc_card_is_removable(host->mmc) &&
 385             mmc_gpio_get_cd(host->mmc) < 0) {
 386                 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
 387                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 388         }
 389 
 390         /*
 391          * If the device attached to the MMC bus is not removable, it is safer
 392          * to set the Force Card Detect bit. People often don't connect the
 393          * card detect signal and use this pin for another purpose. If the card
 394          * detect pin is not muxed to SDHCI controller, a default value is
 395          * used. This value can be different from a SoC revision to another
 396          * one. Problems come when this default value is not card present. To
 397          * avoid this case, if the device is non removable then the card
 398          * detection procedure using the SDMCC_CD signal is bypassed.
 399          * This bit is reset when a software reset for all command is performed
 400          * so we need to implement our own reset function to set back this bit.
 401          *
 402          * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
 403          */
 404         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
 405             || mmc_gpio_get_cd(host->mmc) >= 0)
 406                 sdhci_at91_set_force_card_detect(host);
 407 
 408         pm_runtime_put_autosuspend(&pdev->dev);
 409 
 410         return 0;
 411 
 412 pm_runtime_disable:
 413         pm_runtime_disable(&pdev->dev);
 414         pm_runtime_set_suspended(&pdev->dev);
 415         pm_runtime_put_noidle(&pdev->dev);
 416 clocks_disable_unprepare:
 417         clk_disable_unprepare(priv->gck);
 418         clk_disable_unprepare(priv->mainck);
 419         clk_disable_unprepare(priv->hclock);
 420 sdhci_pltfm_free:
 421         sdhci_pltfm_free(pdev);
 422         return ret;
 423 }
 424 
 425 static int sdhci_at91_remove(struct platform_device *pdev)
 426 {
 427         struct sdhci_host       *host = platform_get_drvdata(pdev);
 428         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 429         struct sdhci_at91_priv  *priv = sdhci_pltfm_priv(pltfm_host);
 430         struct clk *gck = priv->gck;
 431         struct clk *hclock = priv->hclock;
 432         struct clk *mainck = priv->mainck;
 433 
 434         pm_runtime_get_sync(&pdev->dev);
 435         pm_runtime_disable(&pdev->dev);
 436         pm_runtime_put_noidle(&pdev->dev);
 437 
 438         sdhci_pltfm_unregister(pdev);
 439 
 440         clk_disable_unprepare(gck);
 441         clk_disable_unprepare(hclock);
 442         clk_disable_unprepare(mainck);
 443 
 444         return 0;
 445 }
 446 
 447 static struct platform_driver sdhci_at91_driver = {
 448         .driver         = {
 449                 .name   = "sdhci-at91",
 450                 .of_match_table = sdhci_at91_dt_match,
 451                 .pm     = &sdhci_at91_dev_pm_ops,
 452         },
 453         .probe          = sdhci_at91_probe,
 454         .remove         = sdhci_at91_remove,
 455 };
 456 
 457 module_platform_driver(sdhci_at91_driver);
 458 
 459 MODULE_DESCRIPTION("SDHCI driver for at91");
 460 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
 461 MODULE_LICENSE("GPL v2");