root/arch/mips/include/asm/kvm_host.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. kvm_is_error_hva
  2. _kvm_atomic_set_c0_guest_reg
  3. _kvm_atomic_clear_c0_guest_reg
  4. _kvm_atomic_change_c0_guest_reg
  5. __BUILD_KVM_RW_HW
  6. kvm_mips_guest_has_fpu
  7. kvm_mips_guest_can_have_msa
  8. kvm_mips_guest_has_msa
  9. kvm_is_ifetch_fault
  10. kvm_vz_acquire_htimer
  11. kvm_vz_lose_htimer
  12. kvm_arch_hardware_unsetup
  13. kvm_arch_sync_events
  14. kvm_arch_free_memslot
  15. kvm_arch_memslots_updated
  16. kvm_arch_sched_in
  17. kvm_arch_vcpu_blocking
  18. kvm_arch_vcpu_unblocking
  19. kvm_arch_vcpu_block_finish
   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9 
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12 
  13 #include <linux/cpumask.h>
  14 #include <linux/mutex.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/types.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_types.h>
  20 #include <linux/threads.h>
  21 #include <linux/spinlock.h>
  22 
  23 #include <asm/inst.h>
  24 #include <asm/mipsregs.h>
  25 
  26 /* MIPS KVM register ids */
  27 #define MIPS_CP0_32(_R, _S)                                     \
  28         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
  29 
  30 #define MIPS_CP0_64(_R, _S)                                     \
  31         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
  32 
  33 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  34 #define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  35 #define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  36 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  37 #define KVM_REG_MIPS_CP0_CONTEXTCONFIG  MIPS_CP0_32(4, 1)
  38 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  39 #define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3)
  40 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  41 #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  42 #define KVM_REG_MIPS_CP0_SEGCTL0        MIPS_CP0_64(5, 2)
  43 #define KVM_REG_MIPS_CP0_SEGCTL1        MIPS_CP0_64(5, 3)
  44 #define KVM_REG_MIPS_CP0_SEGCTL2        MIPS_CP0_64(5, 4)
  45 #define KVM_REG_MIPS_CP0_PWBASE         MIPS_CP0_64(5, 5)
  46 #define KVM_REG_MIPS_CP0_PWFIELD        MIPS_CP0_64(5, 6)
  47 #define KVM_REG_MIPS_CP0_PWSIZE         MIPS_CP0_64(5, 7)
  48 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  49 #define KVM_REG_MIPS_CP0_PWCTL          MIPS_CP0_32(6, 6)
  50 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  51 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  52 #define KVM_REG_MIPS_CP0_BADINSTR       MIPS_CP0_32(8, 1)
  53 #define KVM_REG_MIPS_CP0_BADINSTRP      MIPS_CP0_32(8, 2)
  54 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  55 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  56 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  57 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  58 #define KVM_REG_MIPS_CP0_INTCTL         MIPS_CP0_32(12, 1)
  59 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  60 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  61 #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
  62 #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  63 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  64 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  65 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  66 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  67 #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
  68 #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
  69 #define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  70 #define KVM_REG_MIPS_CP0_MAARI          MIPS_CP0_64(17, 2)
  71 #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  72 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  73 #define KVM_REG_MIPS_CP0_KSCRATCH1      MIPS_CP0_64(31, 2)
  74 #define KVM_REG_MIPS_CP0_KSCRATCH2      MIPS_CP0_64(31, 3)
  75 #define KVM_REG_MIPS_CP0_KSCRATCH3      MIPS_CP0_64(31, 4)
  76 #define KVM_REG_MIPS_CP0_KSCRATCH4      MIPS_CP0_64(31, 5)
  77 #define KVM_REG_MIPS_CP0_KSCRATCH5      MIPS_CP0_64(31, 6)
  78 #define KVM_REG_MIPS_CP0_KSCRATCH6      MIPS_CP0_64(31, 7)
  79 
  80 
  81 #define KVM_MAX_VCPUS           8
  82 #define KVM_USER_MEM_SLOTS      8
  83 /* memory slots that does not exposed to userspace */
  84 #define KVM_PRIVATE_MEM_SLOTS   0
  85 
  86 #define KVM_HALT_POLL_NS_DEFAULT 500000
  87 
  88 #ifdef CONFIG_KVM_MIPS_VZ
  89 extern unsigned long GUESTID_MASK;
  90 extern unsigned long GUESTID_FIRST_VERSION;
  91 extern unsigned long GUESTID_VERSION_MASK;
  92 #endif
  93 
  94 
  95 /*
  96  * Special address that contains the comm page, used for reducing # of traps
  97  * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
  98  * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
  99  * caught.
 100  */
 101 #define KVM_GUEST_COMMPAGE_ADDR         ((PAGE_SIZE > 0x8000) ? 0 : \
 102                                          (0x8000 - PAGE_SIZE))
 103 
 104 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
 105                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
 106 
 107 #define KVM_GUEST_KUSEG                 0x00000000UL
 108 #define KVM_GUEST_KSEG0                 0x40000000UL
 109 #define KVM_GUEST_KSEG1                 0x40000000UL
 110 #define KVM_GUEST_KSEG23                0x60000000UL
 111 #define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0xe0000000)
 112 #define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
 113 
 114 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 115 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 116 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 117 
 118 /*
 119  * Map an address to a certain kernel segment
 120  */
 121 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 122 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 123 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 124 
 125 #define KVM_INVALID_PAGE                0xdeadbeef
 126 #define KVM_INVALID_ADDR                0xdeadbeef
 127 
 128 /*
 129  * EVA has overlapping user & kernel address spaces, so user VAs may be >
 130  * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
 131  * PAGE_OFFSET.
 132  */
 133 
 134 #define KVM_HVA_ERR_BAD                 (-1UL)
 135 #define KVM_HVA_ERR_RO_BAD              (-2UL)
 136 
 137 static inline bool kvm_is_error_hva(unsigned long addr)
 138 {
 139         return IS_ERR_VALUE(addr);
 140 }
 141 
 142 struct kvm_vm_stat {
 143         ulong remote_tlb_flush;
 144 };
 145 
 146 struct kvm_vcpu_stat {
 147         u64 wait_exits;
 148         u64 cache_exits;
 149         u64 signal_exits;
 150         u64 int_exits;
 151         u64 cop_unusable_exits;
 152         u64 tlbmod_exits;
 153         u64 tlbmiss_ld_exits;
 154         u64 tlbmiss_st_exits;
 155         u64 addrerr_st_exits;
 156         u64 addrerr_ld_exits;
 157         u64 syscall_exits;
 158         u64 resvd_inst_exits;
 159         u64 break_inst_exits;
 160         u64 trap_inst_exits;
 161         u64 msa_fpe_exits;
 162         u64 fpe_exits;
 163         u64 msa_disabled_exits;
 164         u64 flush_dcache_exits;
 165 #ifdef CONFIG_KVM_MIPS_VZ
 166         u64 vz_gpsi_exits;
 167         u64 vz_gsfc_exits;
 168         u64 vz_hc_exits;
 169         u64 vz_grr_exits;
 170         u64 vz_gva_exits;
 171         u64 vz_ghfc_exits;
 172         u64 vz_gpa_exits;
 173         u64 vz_resvd_exits;
 174 #endif
 175         u64 halt_successful_poll;
 176         u64 halt_attempted_poll;
 177         u64 halt_poll_invalid;
 178         u64 halt_wakeup;
 179 };
 180 
 181 struct kvm_arch_memory_slot {
 182 };
 183 
 184 struct kvm_arch {
 185         /* Guest physical mm */
 186         struct mm_struct gpa_mm;
 187         /* Mask of CPUs needing GPA ASID flush */
 188         cpumask_t asid_flush_mask;
 189 };
 190 
 191 #define N_MIPS_COPROC_REGS      32
 192 #define N_MIPS_COPROC_SEL       8
 193 
 194 struct mips_coproc {
 195         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 196 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 197         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 198 #endif
 199 };
 200 
 201 /*
 202  * Coprocessor 0 register names
 203  */
 204 #define MIPS_CP0_TLB_INDEX      0
 205 #define MIPS_CP0_TLB_RANDOM     1
 206 #define MIPS_CP0_TLB_LOW        2
 207 #define MIPS_CP0_TLB_LO0        2
 208 #define MIPS_CP0_TLB_LO1        3
 209 #define MIPS_CP0_TLB_CONTEXT    4
 210 #define MIPS_CP0_TLB_PG_MASK    5
 211 #define MIPS_CP0_TLB_WIRED      6
 212 #define MIPS_CP0_HWRENA         7
 213 #define MIPS_CP0_BAD_VADDR      8
 214 #define MIPS_CP0_COUNT          9
 215 #define MIPS_CP0_TLB_HI         10
 216 #define MIPS_CP0_COMPARE        11
 217 #define MIPS_CP0_STATUS         12
 218 #define MIPS_CP0_CAUSE          13
 219 #define MIPS_CP0_EXC_PC         14
 220 #define MIPS_CP0_PRID           15
 221 #define MIPS_CP0_CONFIG         16
 222 #define MIPS_CP0_LLADDR         17
 223 #define MIPS_CP0_WATCH_LO       18
 224 #define MIPS_CP0_WATCH_HI       19
 225 #define MIPS_CP0_TLB_XCONTEXT   20
 226 #define MIPS_CP0_ECC            26
 227 #define MIPS_CP0_CACHE_ERR      27
 228 #define MIPS_CP0_TAG_LO         28
 229 #define MIPS_CP0_TAG_HI         29
 230 #define MIPS_CP0_ERROR_PC       30
 231 #define MIPS_CP0_DEBUG          23
 232 #define MIPS_CP0_DEPC           24
 233 #define MIPS_CP0_PERFCNT        25
 234 #define MIPS_CP0_ERRCTL         26
 235 #define MIPS_CP0_DATA_LO        28
 236 #define MIPS_CP0_DATA_HI        29
 237 #define MIPS_CP0_DESAVE         31
 238 
 239 #define MIPS_CP0_CONFIG_SEL     0
 240 #define MIPS_CP0_CONFIG1_SEL    1
 241 #define MIPS_CP0_CONFIG2_SEL    2
 242 #define MIPS_CP0_CONFIG3_SEL    3
 243 #define MIPS_CP0_CONFIG4_SEL    4
 244 #define MIPS_CP0_CONFIG5_SEL    5
 245 
 246 #define MIPS_CP0_GUESTCTL2      10
 247 #define MIPS_CP0_GUESTCTL2_SEL  5
 248 #define MIPS_CP0_GTOFFSET       12
 249 #define MIPS_CP0_GTOFFSET_SEL   7
 250 
 251 /* Resume Flags */
 252 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 253 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 254 
 255 #define RESUME_GUEST            0
 256 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 257 #define RESUME_HOST             RESUME_FLAG_HOST
 258 
 259 enum emulation_result {
 260         EMULATE_DONE,           /* no further processing */
 261         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 262         EMULATE_FAIL,           /* can't emulate this instruction */
 263         EMULATE_WAIT,           /* WAIT instruction */
 264         EMULATE_PRIV_FAIL,
 265         EMULATE_EXCEPT,         /* A guest exception has been generated */
 266         EMULATE_HYPERCALL,      /* HYPCALL instruction */
 267 };
 268 
 269 #define mips3_paddr_to_tlbpfn(x) \
 270         (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 271 #define mips3_tlbpfn_to_paddr(x) \
 272         ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 273 
 274 #define MIPS3_PG_SHIFT          6
 275 #define MIPS3_PG_FRAME          0x3fffffc0
 276 
 277 #if defined(CONFIG_64BIT)
 278 #define VPN2_MASK               GENMASK(cpu_vmbits - 1, 13)
 279 #else
 280 #define VPN2_MASK               0xffffe000
 281 #endif
 282 #define KVM_ENTRYHI_ASID        cpu_asid_mask(&boot_cpu_data)
 283 #define TLB_IS_GLOBAL(x)        ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
 284 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 285 #define TLB_ASID(x)             ((x).tlb_hi & KVM_ENTRYHI_ASID)
 286 #define TLB_LO_IDX(x, va)       (((va) >> PAGE_SHIFT) & 1)
 287 #define TLB_IS_VALID(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
 288 #define TLB_IS_DIRTY(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D)
 289 #define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
 290                                  ((y) & VPN2_MASK & ~(x).tlb_mask))
 291 #define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
 292                                  TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
 293 
 294 struct kvm_mips_tlb {
 295         long tlb_mask;
 296         long tlb_hi;
 297         long tlb_lo[2];
 298 };
 299 
 300 #define KVM_NR_MEM_OBJS     4
 301 
 302 /*
 303  * We don't want allocation failures within the mmu code, so we preallocate
 304  * enough memory for a single page fault in a cache.
 305  */
 306 struct kvm_mmu_memory_cache {
 307         int nobjs;
 308         void *objects[KVM_NR_MEM_OBJS];
 309 };
 310 
 311 #define KVM_MIPS_AUX_FPU        0x1
 312 #define KVM_MIPS_AUX_MSA        0x2
 313 
 314 #define KVM_MIPS_GUEST_TLB_SIZE 64
 315 struct kvm_vcpu_arch {
 316         void *guest_ebase;
 317         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 318 
 319         /* Host registers preserved across guest mode execution */
 320         unsigned long host_stack;
 321         unsigned long host_gp;
 322         unsigned long host_pgd;
 323         unsigned long host_entryhi;
 324 
 325         /* Host CP0 registers used when handling exits from guest */
 326         unsigned long host_cp0_badvaddr;
 327         unsigned long host_cp0_epc;
 328         u32 host_cp0_cause;
 329         u32 host_cp0_guestctl0;
 330         u32 host_cp0_badinstr;
 331         u32 host_cp0_badinstrp;
 332 
 333         /* GPRS */
 334         unsigned long gprs[32];
 335         unsigned long hi;
 336         unsigned long lo;
 337         unsigned long pc;
 338 
 339         /* FPU State */
 340         struct mips_fpu_struct fpu;
 341         /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
 342         unsigned int aux_inuse;
 343 
 344         /* COP0 State */
 345         struct mips_coproc *cop0;
 346 
 347         /* Host KSEG0 address of the EI/DI offset */
 348         void *kseg0_commpage;
 349 
 350         /* Resume PC after MMIO completion */
 351         unsigned long io_pc;
 352         /* GPR used as IO source/target */
 353         u32 io_gpr;
 354 
 355         struct hrtimer comparecount_timer;
 356         /* Count timer control KVM register */
 357         u32 count_ctl;
 358         /* Count bias from the raw time */
 359         u32 count_bias;
 360         /* Frequency of timer in Hz */
 361         u32 count_hz;
 362         /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
 363         s64 count_dyn_bias;
 364         /* Resume time */
 365         ktime_t count_resume;
 366         /* Period of timer tick in ns */
 367         u64 count_period;
 368 
 369         /* Bitmask of exceptions that are pending */
 370         unsigned long pending_exceptions;
 371 
 372         /* Bitmask of pending exceptions to be cleared */
 373         unsigned long pending_exceptions_clr;
 374 
 375         /* S/W Based TLB for guest */
 376         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 377 
 378         /* Guest kernel/user [partial] mm */
 379         struct mm_struct guest_kernel_mm, guest_user_mm;
 380 
 381         /* Guest ASID of last user mode execution */
 382         unsigned int last_user_gasid;
 383 
 384         /* Cache some mmu pages needed inside spinlock regions */
 385         struct kvm_mmu_memory_cache mmu_page_cache;
 386 
 387 #ifdef CONFIG_KVM_MIPS_VZ
 388         /* vcpu's vzguestid is different on each host cpu in an smp system */
 389         u32 vzguestid[NR_CPUS];
 390 
 391         /* wired guest TLB entries */
 392         struct kvm_mips_tlb *wired_tlb;
 393         unsigned int wired_tlb_limit;
 394         unsigned int wired_tlb_used;
 395 
 396         /* emulated guest MAAR registers */
 397         unsigned long maar[6];
 398 #endif
 399 
 400         /* Last CPU the VCPU state was loaded on */
 401         int last_sched_cpu;
 402         /* Last CPU the VCPU actually executed guest code on */
 403         int last_exec_cpu;
 404 
 405         /* WAIT executed */
 406         int wait;
 407 
 408         u8 fpu_enabled;
 409         u8 msa_enabled;
 410 };
 411 
 412 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 413                                                 unsigned long val)
 414 {
 415         unsigned long temp;
 416         do {
 417                 __asm__ __volatile__(
 418                 "       .set    push                            \n"
 419                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 420                 "       " __LL "%0, %1                          \n"
 421                 "       or      %0, %2                          \n"
 422                 "       " __SC  "%0, %1                         \n"
 423                 "       .set    pop                             \n"
 424                 : "=&r" (temp), "+m" (*reg)
 425                 : "r" (val));
 426         } while (unlikely(!temp));
 427 }
 428 
 429 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 430                                                   unsigned long val)
 431 {
 432         unsigned long temp;
 433         do {
 434                 __asm__ __volatile__(
 435                 "       .set    push                            \n"
 436                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 437                 "       " __LL "%0, %1                          \n"
 438                 "       and     %0, %2                          \n"
 439                 "       " __SC  "%0, %1                         \n"
 440                 "       .set    pop                             \n"
 441                 : "=&r" (temp), "+m" (*reg)
 442                 : "r" (~val));
 443         } while (unlikely(!temp));
 444 }
 445 
 446 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 447                                                    unsigned long change,
 448                                                    unsigned long val)
 449 {
 450         unsigned long temp;
 451         do {
 452                 __asm__ __volatile__(
 453                 "       .set    push                            \n"
 454                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 455                 "       " __LL "%0, %1                          \n"
 456                 "       and     %0, %2                          \n"
 457                 "       or      %0, %3                          \n"
 458                 "       " __SC  "%0, %1                         \n"
 459                 "       .set    pop                             \n"
 460                 : "=&r" (temp), "+m" (*reg)
 461                 : "r" (~change), "r" (val & change));
 462         } while (unlikely(!temp));
 463 }
 464 
 465 /* Guest register types, used in accessor build below */
 466 #define __KVMT32        u32
 467 #define __KVMTl unsigned long
 468 
 469 /*
 470  * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg()
 471  * These operate on the saved guest C0 state in RAM.
 472  */
 473 
 474 /* Generate saved context simple accessors */
 475 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 476 static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \
 477 {                                                                       \
 478         return cop0->reg[(_reg)][(sel)];                                \
 479 }                                                                       \
 480 static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0,    \
 481                                            __KVMT##type val)            \
 482 {                                                                       \
 483         cop0->reg[(_reg)][(sel)] = val;                                 \
 484 }
 485 
 486 /* Generate saved context bitwise modifiers */
 487 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 488 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
 489                                          __KVMT##type val)              \
 490 {                                                                       \
 491         cop0->reg[(_reg)][(sel)] |= val;                                \
 492 }                                                                       \
 493 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
 494                                            __KVMT##type val)            \
 495 {                                                                       \
 496         cop0->reg[(_reg)][(sel)] &= ~val;                               \
 497 }                                                                       \
 498 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
 499                                             __KVMT##type mask,          \
 500                                             __KVMT##type val)           \
 501 {                                                                       \
 502         unsigned long _mask = mask;                                     \
 503         cop0->reg[(_reg)][(sel)] &= ~_mask;                             \
 504         cop0->reg[(_reg)][(sel)] |= val & _mask;                        \
 505 }
 506 
 507 /* Generate saved context atomic bitwise modifiers */
 508 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
 509 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
 510                                          __KVMT##type val)              \
 511 {                                                                       \
 512         _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val);   \
 513 }                                                                       \
 514 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
 515                                            __KVMT##type val)            \
 516 {                                                                       \
 517         _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
 518 }                                                                       \
 519 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
 520                                             __KVMT##type mask,          \
 521                                             __KVMT##type val)           \
 522 {                                                                       \
 523         _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \
 524                                         val);                           \
 525 }
 526 
 527 /*
 528  * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg()
 529  * These operate on the VZ guest C0 context in hardware.
 530  */
 531 
 532 /* Generate VZ guest context simple accessors */
 533 #define __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
 534 static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \
 535 {                                                                       \
 536         return read_gc0_##name();                                       \
 537 }                                                                       \
 538 static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0,    \
 539                                            __KVMT##type val)            \
 540 {                                                                       \
 541         write_gc0_##name(val);                                          \
 542 }
 543 
 544 /* Generate VZ guest context bitwise modifiers */
 545 #define __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
 546 static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0,      \
 547                                          __KVMT##type val)              \
 548 {                                                                       \
 549         set_gc0_##name(val);                                            \
 550 }                                                                       \
 551 static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0,    \
 552                                            __KVMT##type val)            \
 553 {                                                                       \
 554         clear_gc0_##name(val);                                          \
 555 }                                                                       \
 556 static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0,   \
 557                                             __KVMT##type mask,          \
 558                                             __KVMT##type val)           \
 559 {                                                                       \
 560         change_gc0_##name(mask, val);                                   \
 561 }
 562 
 563 /* Generate VZ guest context save/restore to/from saved context */
 564 #define __BUILD_KVM_SAVE_VZ(name, _reg, sel)                    \
 565 static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0)     \
 566 {                                                                       \
 567         write_gc0_##name(cop0->reg[(_reg)][(sel)]);                     \
 568 }                                                                       \
 569 static inline void kvm_save_gc0_##name(struct mips_coproc *cop0)        \
 570 {                                                                       \
 571         cop0->reg[(_reg)][(sel)] = read_gc0_##name();                   \
 572 }
 573 
 574 /*
 575  * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2()
 576  * These wrap a set of operations to provide them with a different name.
 577  */
 578 
 579 /* Generate simple accessor wrapper */
 580 #define __BUILD_KVM_RW_WRAP(name1, name2, type)                         \
 581 static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0)   \
 582 {                                                                       \
 583         return kvm_read_##name2(cop0);                                  \
 584 }                                                                       \
 585 static inline void kvm_write_##name1(struct mips_coproc *cop0,          \
 586                                      __KVMT##type val)                  \
 587 {                                                                       \
 588         kvm_write_##name2(cop0, val);                                   \
 589 }
 590 
 591 /* Generate bitwise modifier wrapper */
 592 #define __BUILD_KVM_SET_WRAP(name1, name2, type)                        \
 593 static inline void kvm_set_##name1(struct mips_coproc *cop0,            \
 594                                    __KVMT##type val)                    \
 595 {                                                                       \
 596         kvm_set_##name2(cop0, val);                                     \
 597 }                                                                       \
 598 static inline void kvm_clear_##name1(struct mips_coproc *cop0,          \
 599                                      __KVMT##type val)                  \
 600 {                                                                       \
 601         kvm_clear_##name2(cop0, val);                                   \
 602 }                                                                       \
 603 static inline void kvm_change_##name1(struct mips_coproc *cop0,         \
 604                                       __KVMT##type mask,                \
 605                                       __KVMT##type val)                 \
 606 {                                                                       \
 607         kvm_change_##name2(cop0, mask, val);                            \
 608 }
 609 
 610 /*
 611  * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg()
 612  * These generate accessors operating on the saved context in RAM, and wrap them
 613  * with the common guest C0 accessors (for use by common emulation code).
 614  */
 615 
 616 #define __BUILD_KVM_RW_SW(name, type, _reg, sel)                        \
 617         __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 618         __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type)
 619 
 620 #define __BUILD_KVM_SET_SW(name, type, _reg, sel)                       \
 621         __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 622         __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
 623 
 624 #define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel)                    \
 625         __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
 626         __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
 627 
 628 #ifndef CONFIG_KVM_MIPS_VZ
 629 
 630 /*
 631  * T&E (trap & emulate software based virtualisation)
 632  * We generate the common accessors operating exclusively on the saved context
 633  * in RAM.
 634  */
 635 
 636 #define __BUILD_KVM_RW_HW       __BUILD_KVM_RW_SW
 637 #define __BUILD_KVM_SET_HW      __BUILD_KVM_SET_SW
 638 #define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_ATOMIC_SW
 639 
 640 #else
 641 
 642 /*
 643  * VZ (hardware assisted virtualisation)
 644  * These macros use the active guest state in VZ mode (hardware registers),
 645  */
 646 
 647 /*
 648  * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg()
 649  * These generate accessors operating on the VZ guest context in hardware, and
 650  * wrap them with the common guest C0 accessors (for use by common emulation
 651  * code).
 652  *
 653  * Accessors operating on the saved context in RAM are also generated to allow
 654  * convenient explicit saving and restoring of the state.
 655  */
 656 
 657 #define __BUILD_KVM_RW_HW(name, type, _reg, sel)                        \
 658         __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 659         __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
 660         __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type)       \
 661         __BUILD_KVM_SAVE_VZ(name, _reg, sel)
 662 
 663 #define __BUILD_KVM_SET_HW(name, type, _reg, sel)                       \
 664         __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 665         __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
 666         __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type)
 667 
 668 /*
 669  * We can't do atomic modifications of COP0 state if hardware can modify it.
 670  * Races must be handled explicitly.
 671  */
 672 #define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_SET_HW
 673 
 674 #endif
 675 
 676 /*
 677  * Define accessors for CP0 registers that are accessible to the guest. These
 678  * are primarily used by common emulation code, which may need to access the
 679  * registers differently depending on the implementation.
 680  *
 681  *    fns_hw/sw    name     type    reg num         select
 682  */
 683 __BUILD_KVM_RW_HW(index,          32, MIPS_CP0_TLB_INDEX,    0)
 684 __BUILD_KVM_RW_HW(entrylo0,       l,  MIPS_CP0_TLB_LO0,      0)
 685 __BUILD_KVM_RW_HW(entrylo1,       l,  MIPS_CP0_TLB_LO1,      0)
 686 __BUILD_KVM_RW_HW(context,        l,  MIPS_CP0_TLB_CONTEXT,  0)
 687 __BUILD_KVM_RW_HW(contextconfig,  32, MIPS_CP0_TLB_CONTEXT,  1)
 688 __BUILD_KVM_RW_HW(userlocal,      l,  MIPS_CP0_TLB_CONTEXT,  2)
 689 __BUILD_KVM_RW_HW(xcontextconfig, l,  MIPS_CP0_TLB_CONTEXT,  3)
 690 __BUILD_KVM_RW_HW(pagemask,       l,  MIPS_CP0_TLB_PG_MASK,  0)
 691 __BUILD_KVM_RW_HW(pagegrain,      32, MIPS_CP0_TLB_PG_MASK,  1)
 692 __BUILD_KVM_RW_HW(segctl0,        l,  MIPS_CP0_TLB_PG_MASK,  2)
 693 __BUILD_KVM_RW_HW(segctl1,        l,  MIPS_CP0_TLB_PG_MASK,  3)
 694 __BUILD_KVM_RW_HW(segctl2,        l,  MIPS_CP0_TLB_PG_MASK,  4)
 695 __BUILD_KVM_RW_HW(pwbase,         l,  MIPS_CP0_TLB_PG_MASK,  5)
 696 __BUILD_KVM_RW_HW(pwfield,        l,  MIPS_CP0_TLB_PG_MASK,  6)
 697 __BUILD_KVM_RW_HW(pwsize,         l,  MIPS_CP0_TLB_PG_MASK,  7)
 698 __BUILD_KVM_RW_HW(wired,          32, MIPS_CP0_TLB_WIRED,    0)
 699 __BUILD_KVM_RW_HW(pwctl,          32, MIPS_CP0_TLB_WIRED,    6)
 700 __BUILD_KVM_RW_HW(hwrena,         32, MIPS_CP0_HWRENA,       0)
 701 __BUILD_KVM_RW_HW(badvaddr,       l,  MIPS_CP0_BAD_VADDR,    0)
 702 __BUILD_KVM_RW_HW(badinstr,       32, MIPS_CP0_BAD_VADDR,    1)
 703 __BUILD_KVM_RW_HW(badinstrp,      32, MIPS_CP0_BAD_VADDR,    2)
 704 __BUILD_KVM_RW_SW(count,          32, MIPS_CP0_COUNT,        0)
 705 __BUILD_KVM_RW_HW(entryhi,        l,  MIPS_CP0_TLB_HI,       0)
 706 __BUILD_KVM_RW_HW(compare,        32, MIPS_CP0_COMPARE,      0)
 707 __BUILD_KVM_RW_HW(status,         32, MIPS_CP0_STATUS,       0)
 708 __BUILD_KVM_RW_HW(intctl,         32, MIPS_CP0_STATUS,       1)
 709 __BUILD_KVM_RW_HW(cause,          32, MIPS_CP0_CAUSE,        0)
 710 __BUILD_KVM_RW_HW(epc,            l,  MIPS_CP0_EXC_PC,       0)
 711 __BUILD_KVM_RW_SW(prid,           32, MIPS_CP0_PRID,         0)
 712 __BUILD_KVM_RW_HW(ebase,          l,  MIPS_CP0_PRID,         1)
 713 __BUILD_KVM_RW_HW(config,         32, MIPS_CP0_CONFIG,       0)
 714 __BUILD_KVM_RW_HW(config1,        32, MIPS_CP0_CONFIG,       1)
 715 __BUILD_KVM_RW_HW(config2,        32, MIPS_CP0_CONFIG,       2)
 716 __BUILD_KVM_RW_HW(config3,        32, MIPS_CP0_CONFIG,       3)
 717 __BUILD_KVM_RW_HW(config4,        32, MIPS_CP0_CONFIG,       4)
 718 __BUILD_KVM_RW_HW(config5,        32, MIPS_CP0_CONFIG,       5)
 719 __BUILD_KVM_RW_HW(config6,        32, MIPS_CP0_CONFIG,       6)
 720 __BUILD_KVM_RW_HW(config7,        32, MIPS_CP0_CONFIG,       7)
 721 __BUILD_KVM_RW_SW(maari,          l,  MIPS_CP0_LLADDR,       2)
 722 __BUILD_KVM_RW_HW(xcontext,       l,  MIPS_CP0_TLB_XCONTEXT, 0)
 723 __BUILD_KVM_RW_HW(errorepc,       l,  MIPS_CP0_ERROR_PC,     0)
 724 __BUILD_KVM_RW_HW(kscratch1,      l,  MIPS_CP0_DESAVE,       2)
 725 __BUILD_KVM_RW_HW(kscratch2,      l,  MIPS_CP0_DESAVE,       3)
 726 __BUILD_KVM_RW_HW(kscratch3,      l,  MIPS_CP0_DESAVE,       4)
 727 __BUILD_KVM_RW_HW(kscratch4,      l,  MIPS_CP0_DESAVE,       5)
 728 __BUILD_KVM_RW_HW(kscratch5,      l,  MIPS_CP0_DESAVE,       6)
 729 __BUILD_KVM_RW_HW(kscratch6,      l,  MIPS_CP0_DESAVE,       7)
 730 
 731 /* Bitwise operations (on HW state) */
 732 __BUILD_KVM_SET_HW(status,        32, MIPS_CP0_STATUS,       0)
 733 /* Cause can be modified asynchronously from hardirq hrtimer callback */
 734 __BUILD_KVM_ATOMIC_HW(cause,      32, MIPS_CP0_CAUSE,        0)
 735 __BUILD_KVM_SET_HW(ebase,         l,  MIPS_CP0_PRID,         1)
 736 
 737 /* Bitwise operations (on saved state) */
 738 __BUILD_KVM_SET_SAVED(config,     32, MIPS_CP0_CONFIG,       0)
 739 __BUILD_KVM_SET_SAVED(config1,    32, MIPS_CP0_CONFIG,       1)
 740 __BUILD_KVM_SET_SAVED(config2,    32, MIPS_CP0_CONFIG,       2)
 741 __BUILD_KVM_SET_SAVED(config3,    32, MIPS_CP0_CONFIG,       3)
 742 __BUILD_KVM_SET_SAVED(config4,    32, MIPS_CP0_CONFIG,       4)
 743 __BUILD_KVM_SET_SAVED(config5,    32, MIPS_CP0_CONFIG,       5)
 744 
 745 /* Helpers */
 746 
 747 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
 748 {
 749         return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
 750                 vcpu->fpu_enabled;
 751 }
 752 
 753 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
 754 {
 755         return kvm_mips_guest_can_have_fpu(vcpu) &&
 756                 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
 757 }
 758 
 759 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
 760 {
 761         return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
 762                 vcpu->msa_enabled;
 763 }
 764 
 765 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
 766 {
 767         return kvm_mips_guest_can_have_msa(vcpu) &&
 768                 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
 769 }
 770 
 771 struct kvm_mips_callbacks {
 772         int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
 773         int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
 774         int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
 775         int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
 776         int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
 777         int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
 778         int (*handle_syscall)(struct kvm_vcpu *vcpu);
 779         int (*handle_res_inst)(struct kvm_vcpu *vcpu);
 780         int (*handle_break)(struct kvm_vcpu *vcpu);
 781         int (*handle_trap)(struct kvm_vcpu *vcpu);
 782         int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
 783         int (*handle_fpe)(struct kvm_vcpu *vcpu);
 784         int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
 785         int (*handle_guest_exit)(struct kvm_vcpu *vcpu);
 786         int (*hardware_enable)(void);
 787         void (*hardware_disable)(void);
 788         int (*check_extension)(struct kvm *kvm, long ext);
 789         int (*vcpu_init)(struct kvm_vcpu *vcpu);
 790         void (*vcpu_uninit)(struct kvm_vcpu *vcpu);
 791         int (*vcpu_setup)(struct kvm_vcpu *vcpu);
 792         void (*flush_shadow_all)(struct kvm *kvm);
 793         /*
 794          * Must take care of flushing any cached GPA PTEs (e.g. guest entries in
 795          * VZ root TLB, or T&E GVA page tables and corresponding root TLB
 796          * mappings).
 797          */
 798         void (*flush_shadow_memslot)(struct kvm *kvm,
 799                                      const struct kvm_memory_slot *slot);
 800         gpa_t (*gva_to_gpa)(gva_t gva);
 801         void (*queue_timer_int)(struct kvm_vcpu *vcpu);
 802         void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
 803         void (*queue_io_int)(struct kvm_vcpu *vcpu,
 804                              struct kvm_mips_interrupt *irq);
 805         void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
 806                                struct kvm_mips_interrupt *irq);
 807         int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
 808                            u32 cause);
 809         int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
 810                          u32 cause);
 811         unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
 812         int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
 813         int (*get_one_reg)(struct kvm_vcpu *vcpu,
 814                            const struct kvm_one_reg *reg, s64 *v);
 815         int (*set_one_reg)(struct kvm_vcpu *vcpu,
 816                            const struct kvm_one_reg *reg, s64 v);
 817         int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
 818         int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu);
 819         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 820         void (*vcpu_reenter)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 821 };
 822 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 823 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 824 
 825 /* Debug: dump vcpu state */
 826 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 827 
 828 extern int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu);
 829 
 830 /* Building of entry/exception code */
 831 int kvm_mips_entry_setup(void);
 832 void *kvm_mips_build_vcpu_run(void *addr);
 833 void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler);
 834 void *kvm_mips_build_exception(void *addr, void *handler);
 835 void *kvm_mips_build_exit(void *addr);
 836 
 837 /* FPU/MSA context management */
 838 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
 839 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
 840 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
 841 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
 842 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
 843 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
 844 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
 845 void kvm_own_fpu(struct kvm_vcpu *vcpu);
 846 void kvm_own_msa(struct kvm_vcpu *vcpu);
 847 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
 848 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
 849 
 850 /* TLB handling */
 851 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 852 
 853 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
 854 
 855 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 856 
 857 #ifdef CONFIG_KVM_MIPS_VZ
 858 int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
 859                                       struct kvm_vcpu *vcpu, bool write_fault);
 860 #endif
 861 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 862                                            struct kvm_vcpu *vcpu,
 863                                            bool write_fault);
 864 
 865 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 866                                               struct kvm_vcpu *vcpu);
 867 
 868 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 869                                                 struct kvm_mips_tlb *tlb,
 870                                                 unsigned long gva,
 871                                                 bool write_fault);
 872 
 873 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
 874                                                      u32 *opc,
 875                                                      struct kvm_run *run,
 876                                                      struct kvm_vcpu *vcpu,
 877                                                      bool write_fault);
 878 
 879 extern void kvm_mips_dump_host_tlbs(void);
 880 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 881 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi,
 882                                  bool user, bool kernel);
 883 
 884 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 885                                      unsigned long entryhi);
 886 
 887 #ifdef CONFIG_KVM_MIPS_VZ
 888 int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 889 int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
 890                             unsigned long *gpa);
 891 void kvm_vz_local_flush_roottlb_all_guests(void);
 892 void kvm_vz_local_flush_guesttlb_all(void);
 893 void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index,
 894                           unsigned int count);
 895 void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
 896                           unsigned int count);
 897 #endif
 898 
 899 void kvm_mips_suspend_mm(int cpu);
 900 void kvm_mips_resume_mm(int cpu);
 901 
 902 /* MMU handling */
 903 
 904 /**
 905  * enum kvm_mips_flush - Types of MMU flushes.
 906  * @KMF_USER:   Flush guest user virtual memory mappings.
 907  *              Guest USeg only.
 908  * @KMF_KERN:   Flush guest kernel virtual memory mappings.
 909  *              Guest USeg and KSeg2/3.
 910  * @KMF_GPA:    Flush guest physical memory mappings.
 911  *              Also includes KSeg0 if KMF_KERN is set.
 912  */
 913 enum kvm_mips_flush {
 914         KMF_USER        = 0x0,
 915         KMF_KERN        = 0x1,
 916         KMF_GPA         = 0x2,
 917 };
 918 void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags);
 919 bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 920 int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 921 pgd_t *kvm_pgd_alloc(void);
 922 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
 923 void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr,
 924                                   bool user);
 925 void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu);
 926 void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu);
 927 
 928 enum kvm_mips_fault_result {
 929         KVM_MIPS_MAPPED = 0,
 930         KVM_MIPS_GVA,
 931         KVM_MIPS_GPA,
 932         KVM_MIPS_TLB,
 933         KVM_MIPS_TLBINV,
 934         KVM_MIPS_TLBMOD,
 935 };
 936 enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu,
 937                                                    unsigned long gva,
 938                                                    bool write);
 939 
 940 #define KVM_ARCH_WANT_MMU_NOTIFIER
 941 int kvm_unmap_hva_range(struct kvm *kvm,
 942                         unsigned long start, unsigned long end);
 943 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 944 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
 945 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
 946 
 947 /* Emulation */
 948 int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 949 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
 950 int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 951 int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 952 
 953 /**
 954  * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
 955  * @vcpu:       Virtual CPU.
 956  *
 957  * Returns:     Whether the TLBL exception was likely due to an instruction
 958  *              fetch fault rather than a data load fault.
 959  */
 960 static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
 961 {
 962         unsigned long badvaddr = vcpu->host_cp0_badvaddr;
 963         unsigned long epc = msk_isa16_mode(vcpu->pc);
 964         u32 cause = vcpu->host_cp0_cause;
 965 
 966         if (epc == badvaddr)
 967                 return true;
 968 
 969         /*
 970          * Branches may be 32-bit or 16-bit instructions.
 971          * This isn't exact, but we don't really support MIPS16 or microMIPS yet
 972          * in KVM anyway.
 973          */
 974         if ((cause & CAUSEF_BD) && badvaddr - epc <= 4)
 975                 return true;
 976 
 977         return false;
 978 }
 979 
 980 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
 981                                                    u32 *opc,
 982                                                    struct kvm_run *run,
 983                                                    struct kvm_vcpu *vcpu);
 984 
 985 long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu);
 986 
 987 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
 988                                                       u32 *opc,
 989                                                       struct kvm_run *run,
 990                                                       struct kvm_vcpu *vcpu);
 991 
 992 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
 993                                                          u32 *opc,
 994                                                          struct kvm_run *run,
 995                                                          struct kvm_vcpu *vcpu);
 996 
 997 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
 998                                                         u32 *opc,
 999                                                         struct kvm_run *run,
1000                                                         struct kvm_vcpu *vcpu);
1001 
1002 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
1003                                                          u32 *opc,
1004                                                          struct kvm_run *run,
1005                                                          struct kvm_vcpu *vcpu);
1006 
1007 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
1008                                                         u32 *opc,
1009                                                         struct kvm_run *run,
1010                                                         struct kvm_vcpu *vcpu);
1011 
1012 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
1013                                                      u32 *opc,
1014                                                      struct kvm_run *run,
1015                                                      struct kvm_vcpu *vcpu);
1016 
1017 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
1018                                                       u32 *opc,
1019                                                       struct kvm_run *run,
1020                                                       struct kvm_vcpu *vcpu);
1021 
1022 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
1023                                                 u32 *opc,
1024                                                 struct kvm_run *run,
1025                                                 struct kvm_vcpu *vcpu);
1026 
1027 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
1028                                                      u32 *opc,
1029                                                      struct kvm_run *run,
1030                                                      struct kvm_vcpu *vcpu);
1031 
1032 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
1033                                                      u32 *opc,
1034                                                      struct kvm_run *run,
1035                                                      struct kvm_vcpu *vcpu);
1036 
1037 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
1038                                                        u32 *opc,
1039                                                        struct kvm_run *run,
1040                                                        struct kvm_vcpu *vcpu);
1041 
1042 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
1043                                                          u32 *opc,
1044                                                          struct kvm_run *run,
1045                                                          struct kvm_vcpu *vcpu);
1046 
1047 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
1048                                                       u32 *opc,
1049                                                       struct kvm_run *run,
1050                                                       struct kvm_vcpu *vcpu);
1051 
1052 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
1053                                                          u32 *opc,
1054                                                          struct kvm_run *run,
1055                                                          struct kvm_vcpu *vcpu);
1056 
1057 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
1058                                                          struct kvm_run *run);
1059 
1060 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
1061 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
1062 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
1063 void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz);
1064 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
1065 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
1066 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
1067 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
1068 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
1069 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
1070 
1071 /* fairly internal functions requiring some care to use */
1072 int kvm_mips_count_disabled(struct kvm_vcpu *vcpu);
1073 ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count);
1074 int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
1075                              u32 count, int min_drift);
1076 
1077 #ifdef CONFIG_KVM_MIPS_VZ
1078 void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu);
1079 void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu);
1080 #else
1081 static inline void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu) {}
1082 static inline void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu) {}
1083 #endif
1084 
1085 enum emulation_result kvm_mips_check_privilege(u32 cause,
1086                                                u32 *opc,
1087                                                struct kvm_run *run,
1088                                                struct kvm_vcpu *vcpu);
1089 
1090 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
1091                                              u32 *opc,
1092                                              u32 cause,
1093                                              struct kvm_run *run,
1094                                              struct kvm_vcpu *vcpu);
1095 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
1096                                            u32 *opc,
1097                                            u32 cause,
1098                                            struct kvm_run *run,
1099                                            struct kvm_vcpu *vcpu);
1100 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
1101                                              u32 cause,
1102                                              struct kvm_run *run,
1103                                              struct kvm_vcpu *vcpu);
1104 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
1105                                             u32 cause,
1106                                             struct kvm_run *run,
1107                                             struct kvm_vcpu *vcpu);
1108 
1109 /* COP0 */
1110 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu);
1111 
1112 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
1113 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
1114 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
1115 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
1116 
1117 /* Hypercalls (hypcall.c) */
1118 
1119 enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
1120                                             union mips_instruction inst);
1121 int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
1122 
1123 /* Dynamic binary translation */
1124 extern int kvm_mips_trans_cache_index(union mips_instruction inst,
1125                                       u32 *opc, struct kvm_vcpu *vcpu);
1126 extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
1127                                    struct kvm_vcpu *vcpu);
1128 extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
1129                                struct kvm_vcpu *vcpu);
1130 extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
1131                                struct kvm_vcpu *vcpu);
1132 
1133 /* Misc */
1134 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
1135 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
1136 
1137 static inline void kvm_arch_hardware_unsetup(void) {}
1138 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1139 static inline void kvm_arch_free_memslot(struct kvm *kvm,
1140                 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
1141 static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {}
1142 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1143 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
1144 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
1145 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
1146 
1147 #endif /* __MIPS_KVM_HOST_H__ */
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