1
2 #ifndef _FORE200E_H
3 #define _FORE200E_H
4
5 #ifdef __KERNEL__
6
7
8
9 #define SMALL_BUFFER_SIZE 384
10 #define LARGE_BUFFER_SIZE 4032
11
12
13 #define RBD_BLK_SIZE 32
14
15
16 #define MAX_PDU_SIZE 65535
17
18
19 #define BUFFER_S1_SIZE SMALL_BUFFER_SIZE
20 #define BUFFER_L1_SIZE LARGE_BUFFER_SIZE
21
22 #define BUFFER_S2_SIZE SMALL_BUFFER_SIZE
23 #define BUFFER_L2_SIZE LARGE_BUFFER_SIZE
24
25 #define BUFFER_S1_NBR (RBD_BLK_SIZE * 6)
26 #define BUFFER_L1_NBR (RBD_BLK_SIZE * 4)
27
28 #define BUFFER_S2_NBR (RBD_BLK_SIZE * 6)
29 #define BUFFER_L2_NBR (RBD_BLK_SIZE * 4)
30
31
32 #define QUEUE_SIZE_CMD 16
33 #define QUEUE_SIZE_RX 64
34 #define QUEUE_SIZE_TX 256
35 #define QUEUE_SIZE_BS 32
36
37 #define FORE200E_VPI_BITS 0
38 #define FORE200E_VCI_BITS 10
39 #define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS))
40
41
42 #define TSD_FIXED 2
43 #define TSD_EXTENSION 0
44 #define TSD_NBR (TSD_FIXED + TSD_EXTENSION)
45
46
47
48
49
50
51
52 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)
53
54 #define RSD_FIXED 3
55
56
57
58
59
60
61 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
62 #define RSD_NBR (RSD_FIXED + RSD_EXTENSION)
63
64
65 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
66 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
67
68
69
70 #if defined(__LITTLE_ENDIAN_BITFIELD)
71 #define BITFIELD2(b1, b2) b1; b2;
72 #define BITFIELD3(b1, b2, b3) b1; b2; b3;
73 #define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4;
74 #define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5;
75 #define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6;
76 #elif defined(__BIG_ENDIAN_BITFIELD)
77 #define BITFIELD2(b1, b2) b2; b1;
78 #define BITFIELD3(b1, b2, b3) b3; b2; b1;
79 #define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1;
80 #define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1;
81 #define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1;
82 #else
83 #error unknown bitfield endianess
84 #endif
85
86
87
88
89 typedef struct atm_header {
90 BITFIELD5(
91 u32 clp : 1,
92 u32 plt : 3,
93 u32 vci : 16,
94 u32 vpi : 8,
95 u32 gfc : 4
96 )
97 } atm_header_t;
98
99
100
101
102 typedef enum fore200e_aal {
103 FORE200E_AAL0 = 0,
104 FORE200E_AAL34 = 4,
105 FORE200E_AAL5 = 5,
106 } fore200e_aal_t;
107
108
109
110
111 typedef struct tpd_spec {
112 BITFIELD4(
113 u32 length : 16,
114 u32 nseg : 8,
115 enum fore200e_aal aal : 4,
116 u32 intr : 4
117 )
118 } tpd_spec_t;
119
120
121
122
123 typedef struct tpd_rate
124 {
125 BITFIELD2(
126 u32 idle_cells : 16,
127 u32 data_cells : 16
128 )
129 } tpd_rate_t;
130
131
132
133
134 typedef struct tsd {
135 u32 buffer;
136 u32 length;
137 } tsd_t;
138
139
140
141
142 typedef struct tpd {
143 struct atm_header atm_header;
144 struct tpd_spec spec;
145 struct tpd_rate rate;
146 u32 pad;
147 struct tsd tsd[ TSD_NBR ];
148 } tpd_t;
149
150
151
152
153 typedef struct rsd {
154 u32 handle;
155 u32 length;
156 } rsd_t;
157
158
159
160
161 typedef struct rpd {
162 struct atm_header atm_header;
163 u32 nseg;
164 struct rsd rsd[ RSD_NBR ];
165 } rpd_t;
166
167
168
169
170 typedef enum buffer_scheme {
171 BUFFER_SCHEME_ONE,
172 BUFFER_SCHEME_TWO,
173 BUFFER_SCHEME_NBR
174 } buffer_scheme_t;
175
176
177
178
179 typedef enum buffer_magn {
180 BUFFER_MAGN_SMALL,
181 BUFFER_MAGN_LARGE,
182 BUFFER_MAGN_NBR
183 } buffer_magn_t;
184
185
186
187
188 typedef struct rbd {
189 u32 handle;
190 u32 buffer_haddr;
191 } rbd_t;
192
193
194
195
196 typedef struct rbd_block {
197 struct rbd rbd[ RBD_BLK_SIZE ];
198 } rbd_block_t;
199
200
201
202
203 typedef struct tpd_haddr {
204 BITFIELD3(
205 u32 size : 4,
206 u32 pad : 1,
207 u32 haddr : 27
208 )
209 } tpd_haddr_t;
210
211 #define TPD_HADDR_SHIFT 5
212
213
214
215 typedef struct cp_txq_entry {
216 struct tpd_haddr tpd_haddr;
217 u32 status_haddr;
218 } cp_txq_entry_t;
219
220
221
222
223 typedef struct cp_rxq_entry {
224 u32 rpd_haddr;
225 u32 status_haddr;
226 } cp_rxq_entry_t;
227
228
229
230
231 typedef struct cp_bsq_entry {
232 u32 rbd_block_haddr;
233 u32 status_haddr;
234 } cp_bsq_entry_t;
235
236
237
238
239 typedef volatile enum status {
240 STATUS_PENDING = (1<<0),
241 STATUS_COMPLETE = (1<<1),
242 STATUS_FREE = (1<<2),
243 STATUS_ERROR = (1<<3)
244 } status_t;
245
246
247
248
249 typedef enum opcode {
250 OPCODE_INITIALIZE = 1,
251 OPCODE_ACTIVATE_VCIN,
252 OPCODE_ACTIVATE_VCOUT,
253 OPCODE_DEACTIVATE_VCIN,
254 OPCODE_DEACTIVATE_VCOUT,
255 OPCODE_GET_STATS,
256 OPCODE_SET_OC3,
257 OPCODE_GET_OC3,
258 OPCODE_RESET_STATS,
259 OPCODE_GET_PROM,
260 OPCODE_SET_VPI_BITS,
261
262
263 OPCODE_REQUEST_INTR = (1<<7)
264 } opcode_t;
265
266
267
268
269 typedef struct vpvc {
270 BITFIELD3(
271 u32 vci : 16,
272 u32 vpi : 8,
273 u32 pad : 8
274 )
275 } vpvc_t;
276
277
278
279
280 typedef struct activate_opcode {
281 BITFIELD4(
282 enum opcode opcode : 8,
283 enum fore200e_aal aal : 8,
284 enum buffer_scheme scheme : 8,
285 u32 pad : 8
286 )
287 } activate_opcode_t;
288
289
290
291
292 typedef struct activate_block {
293 struct activate_opcode opcode;
294 struct vpvc vpvc;
295 u32 mtu;
296
297 } activate_block_t;
298
299
300
301
302 typedef struct deactivate_opcode {
303 BITFIELD2(
304 enum opcode opcode : 8,
305 u32 pad : 24
306 )
307 } deactivate_opcode_t;
308
309
310
311
312 typedef struct deactivate_block {
313 struct deactivate_opcode opcode;
314 struct vpvc vpvc;
315 } deactivate_block_t;
316
317
318
319
320 typedef struct oc3_regs {
321 u32 reg[ 128 ];
322
323
324 } oc3_regs_t;
325
326
327
328
329 typedef struct oc3_opcode {
330 BITFIELD4(
331 enum opcode opcode : 8,
332 u32 reg : 8,
333 u32 value : 8,
334 u32 mask : 8
335
336
337 )
338 } oc3_opcode_t;
339
340
341
342
343 typedef struct oc3_block {
344 struct oc3_opcode opcode;
345 u32 regs_haddr;
346 } oc3_block_t;
347
348
349
350
351 typedef struct stats_phy {
352 __be32 crc_header_errors;
353 __be32 framing_errors;
354 __be32 pad[ 2 ];
355 } stats_phy_t;
356
357
358
359
360 typedef struct stats_oc3 {
361 __be32 section_bip8_errors;
362 __be32 path_bip8_errors;
363 __be32 line_bip24_errors;
364 __be32 line_febe_errors;
365 __be32 path_febe_errors;
366 __be32 corr_hcs_errors;
367 __be32 ucorr_hcs_errors;
368 __be32 pad[ 1 ];
369 } stats_oc3_t;
370
371
372
373
374 typedef struct stats_atm {
375 __be32 cells_transmitted;
376 __be32 cells_received;
377 __be32 vpi_bad_range;
378 __be32 vpi_no_conn;
379 __be32 vci_bad_range;
380 __be32 vci_no_conn;
381 __be32 pad[ 2 ];
382 } stats_atm_t;
383
384
385
386 typedef struct stats_aal0 {
387 __be32 cells_transmitted;
388 __be32 cells_received;
389 __be32 cells_dropped;
390 __be32 pad[ 1 ];
391 } stats_aal0_t;
392
393
394
395
396 typedef struct stats_aal34 {
397 __be32 cells_transmitted;
398 __be32 cells_received;
399 __be32 cells_crc_errors;
400 __be32 cells_protocol_errors;
401 __be32 cells_dropped;
402 __be32 cspdus_transmitted;
403 __be32 cspdus_received;
404 __be32 cspdus_protocol_errors;
405 __be32 cspdus_dropped;
406 __be32 pad[ 3 ];
407 } stats_aal34_t;
408
409
410
411
412 typedef struct stats_aal5 {
413 __be32 cells_transmitted;
414 __be32 cells_received;
415 __be32 cells_dropped;
416 __be32 congestion_experienced;
417 __be32 cspdus_transmitted;
418 __be32 cspdus_received;
419 __be32 cspdus_crc_errors;
420 __be32 cspdus_protocol_errors;
421 __be32 cspdus_dropped;
422 __be32 pad[ 3 ];
423 } stats_aal5_t;
424
425
426
427
428 typedef struct stats_aux {
429 __be32 small_b1_failed;
430 __be32 large_b1_failed;
431 __be32 small_b2_failed;
432 __be32 large_b2_failed;
433 __be32 rpd_alloc_failed;
434 __be32 receive_carrier;
435 __be32 pad[ 2 ];
436 } stats_aux_t;
437
438
439
440
441 typedef struct stats {
442 struct stats_phy phy;
443 struct stats_oc3 oc3;
444 struct stats_atm atm;
445 struct stats_aal0 aal0;
446 struct stats_aal34 aal34;
447 struct stats_aal5 aal5;
448 struct stats_aux aux;
449 } stats_t;
450
451
452
453
454 typedef struct stats_opcode {
455 BITFIELD2(
456 enum opcode opcode : 8,
457 u32 pad : 24
458 )
459 } stats_opcode_t;
460
461
462
463
464 typedef struct stats_block {
465 struct stats_opcode opcode;
466 u32 stats_haddr;
467 } stats_block_t;
468
469
470
471
472 typedef struct prom_data {
473 u32 hw_revision;
474 u32 serial_number;
475 u8 mac_addr[ 8 ];
476 } prom_data_t;
477
478
479
480
481 typedef struct prom_opcode {
482 BITFIELD2(
483 enum opcode opcode : 8,
484 u32 pad : 24
485 )
486 } prom_opcode_t;
487
488
489
490
491 typedef struct prom_block {
492 struct prom_opcode opcode;
493 u32 prom_haddr;
494 } prom_block_t;
495
496
497
498
499 typedef union cmd {
500 enum opcode opcode;
501 struct activate_block activate_block;
502 struct deactivate_block deactivate_block;
503 struct stats_block stats_block;
504 struct prom_block prom_block;
505 struct oc3_block oc3_block;
506 u32 pad[ 4 ];
507 } cmd_t;
508
509
510
511
512 typedef struct cp_cmdq_entry {
513 union cmd cmd;
514 u32 status_haddr;
515 u32 pad[ 3 ];
516 } cp_cmdq_entry_t;
517
518
519
520
521 typedef struct host_txq_entry {
522 struct cp_txq_entry __iomem *cp_entry;
523 enum status* status;
524 struct tpd* tpd;
525 u32 tpd_dma;
526 struct sk_buff* skb;
527 void* data;
528 unsigned long incarn;
529 struct fore200e_vc_map* vc_map;
530
531 } host_txq_entry_t;
532
533
534
535
536 typedef struct host_rxq_entry {
537 struct cp_rxq_entry __iomem *cp_entry;
538 enum status* status;
539 struct rpd* rpd;
540 u32 rpd_dma;
541 } host_rxq_entry_t;
542
543
544
545
546 typedef struct host_bsq_entry {
547 struct cp_bsq_entry __iomem *cp_entry;
548 enum status* status;
549 struct rbd_block* rbd_block;
550 u32 rbd_block_dma;
551 } host_bsq_entry_t;
552
553
554
555
556 typedef struct host_cmdq_entry {
557 struct cp_cmdq_entry __iomem *cp_entry;
558 enum status *status;
559 } host_cmdq_entry_t;
560
561
562
563
564 typedef struct chunk {
565 void* alloc_addr;
566 void* align_addr;
567 dma_addr_t dma_addr;
568 int direction;
569 u32 alloc_size;
570 u32 align_size;
571 } chunk_t;
572
573 #define dma_size align_size
574
575
576
577
578 typedef struct buffer {
579 struct buffer* next;
580 enum buffer_scheme scheme;
581 enum buffer_magn magn;
582 struct chunk data;
583 #ifdef FORE200E_BSQ_DEBUG
584 unsigned long index;
585 int supplied;
586 #endif
587 } buffer_t;
588
589
590 #if (BITS_PER_LONG == 32)
591 #define FORE200E_BUF2HDL(buffer) ((u32)(buffer))
592 #define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle))
593 #else
594 #define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))
595 #define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
596 #endif
597
598
599
600
601 typedef struct host_cmdq {
602 struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ];
603 int head;
604 struct chunk status;
605 } host_cmdq_t;
606
607
608
609
610 typedef struct host_txq {
611 struct host_txq_entry host_entry[ QUEUE_SIZE_TX ];
612 int head;
613 int tail;
614 struct chunk tpd;
615 struct chunk status;
616 int txing;
617 } host_txq_t;
618
619
620
621
622 typedef struct host_rxq {
623 struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ];
624 int head;
625 struct chunk rpd;
626 struct chunk status;
627 } host_rxq_t;
628
629
630
631
632 typedef struct host_bsq {
633 struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ];
634 int head;
635 struct chunk rbd_block;
636 struct chunk status;
637 struct buffer* buffer;
638 struct buffer* freebuf;
639 volatile int freebuf_count;
640 } host_bsq_t;
641
642
643
644
645 typedef struct fw_header {
646 __le32 magic;
647 __le32 version;
648 __le32 load_offset;
649 __le32 start_offset;
650 } fw_header_t;
651
652 #define FW_HEADER_MAGIC 0x65726f66
653
654
655
656
657 typedef struct bs_spec {
658 u32 queue_length;
659 u32 buffer_size;
660 u32 pool_size;
661 u32 supply_blksize;
662
663 } bs_spec_t;
664
665
666
667
668 typedef struct init_block {
669 enum opcode opcode;
670 enum status status;
671 u32 receive_threshold;
672 u32 num_connect;
673 u32 cmd_queue_len;
674 u32 tx_queue_len;
675 u32 rx_queue_len;
676 u32 rsd_extension;
677 u32 tsd_extension;
678 u32 conless_vpvc;
679 u32 pad[ 2 ];
680 struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
681 } init_block_t;
682
683
684 typedef enum media_type {
685 MEDIA_TYPE_CAT5_UTP = 0x06,
686 MEDIA_TYPE_MM_OC3_ST = 0x16,
687 MEDIA_TYPE_MM_OC3_SC = 0x26,
688 MEDIA_TYPE_SM_OC3_ST = 0x36,
689 MEDIA_TYPE_SM_OC3_SC = 0x46
690 } media_type_t;
691
692 #define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4)
693
694
695
696
697 typedef struct cp_queues {
698 u32 cp_cmdq;
699 u32 cp_txq;
700 u32 cp_rxq;
701 u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
702 u32 imask;
703 u32 istat;
704 u32 heap_base;
705 u32 heap_size;
706 u32 hlogger;
707 u32 heartbeat;
708 u32 fw_release;
709 u32 mon960_release;
710 u32 tq_plen;
711
712 struct init_block init;
713 enum media_type media_type;
714 u32 oc3_revision;
715 } cp_queues_t;
716
717
718
719
720 typedef enum boot_status {
721 BSTAT_COLD_START = (u32) 0xc01dc01d,
722 BSTAT_SELFTEST_OK = (u32) 0x02201958,
723 BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad,
724 BSTAT_CP_RUNNING = (u32) 0xce11feed,
725 BSTAT_MON_TOO_BIG = (u32) 0x10aded00
726 } boot_status_t;
727
728
729
730
731 typedef struct soft_uart {
732 u32 send;
733 u32 recv;
734 } soft_uart_t;
735
736 #define FORE200E_CP_MONITOR_UART_FREE 0x00000000
737 #define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000
738
739
740
741
742 typedef struct cp_monitor {
743 struct soft_uart soft_uart;
744 enum boot_status bstat;
745 u32 app_base;
746 u32 mon_version;
747 } cp_monitor_t;
748
749
750
751
752 typedef enum fore200e_state {
753 FORE200E_STATE_BLANK,
754 FORE200E_STATE_REGISTER,
755 FORE200E_STATE_CONFIGURE,
756 FORE200E_STATE_MAP,
757 FORE200E_STATE_RESET,
758 FORE200E_STATE_START_FW,
759 FORE200E_STATE_INITIALIZE,
760 FORE200E_STATE_INIT_CMDQ,
761 FORE200E_STATE_INIT_TXQ,
762 FORE200E_STATE_INIT_RXQ,
763 FORE200E_STATE_INIT_BSQ,
764 FORE200E_STATE_ALLOC_BUF,
765 FORE200E_STATE_IRQ,
766 FORE200E_STATE_COMPLETE
767 } fore200e_state;
768
769
770
771
772 typedef struct fore200e_pca_regs {
773 volatile u32 __iomem * hcr;
774 volatile u32 __iomem * imr;
775 volatile u32 __iomem * psr;
776 } fore200e_pca_regs_t;
777
778
779
780
781 typedef struct fore200e_sba_regs {
782 u32 __iomem *hcr;
783 u32 __iomem *bsr;
784 u32 __iomem *isr;
785 } fore200e_sba_regs_t;
786
787
788
789
790 typedef union fore200e_regs {
791 struct fore200e_pca_regs pca;
792 struct fore200e_sba_regs sba;
793 } fore200e_regs;
794
795
796 struct fore200e;
797
798
799
800 typedef struct fore200e_bus {
801 char* model_name;
802 char* proc_name;
803 int descr_alignment;
804 int buffer_alignment;
805 int status_alignment;
806 u32 (*read)(volatile u32 __iomem *);
807 void (*write)(u32, volatile u32 __iomem *);
808 int (*configure)(struct fore200e*);
809 int (*map)(struct fore200e*);
810 void (*reset)(struct fore200e*);
811 int (*prom_read)(struct fore200e*, struct prom_data*);
812 void (*unmap)(struct fore200e*);
813 void (*irq_enable)(struct fore200e*);
814 int (*irq_check)(struct fore200e*);
815 void (*irq_ack)(struct fore200e*);
816 int (*proc_read)(struct fore200e*, char*);
817 } fore200e_bus_t;
818
819
820
821 typedef struct fore200e_vc_map {
822 struct atm_vcc* vcc;
823 unsigned long incarn;
824 } fore200e_vc_map_t;
825
826 #define FORE200E_VC_MAP(fore200e, vpi, vci) \
827 (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ])
828
829
830
831
832 typedef struct fore200e {
833 struct list_head entry;
834 const struct fore200e_bus* bus;
835 union fore200e_regs regs;
836 struct atm_dev* atm_dev;
837
838 enum fore200e_state state;
839
840 char name[16];
841 struct device *dev;
842 int irq;
843 unsigned long phys_base;
844 void __iomem * virt_base;
845
846 unsigned char esi[ ESI_LEN ];
847
848 struct cp_monitor __iomem * cp_monitor;
849 struct cp_queues __iomem * cp_queues;
850 struct host_cmdq host_cmdq;
851 struct host_txq host_txq;
852 struct host_rxq host_rxq;
853
854 struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
855
856 u32 available_cell_rate;
857
858 int loop_mode;
859
860 struct stats* stats;
861
862 struct mutex rate_mtx;
863 spinlock_t q_lock;
864 #ifdef FORE200E_USE_TASKLET
865 struct tasklet_struct tx_tasklet;
866 struct tasklet_struct rx_tasklet;
867 #endif
868 unsigned long tx_sat;
869
870 unsigned long incarn_count;
871 struct fore200e_vc_map vc_map[ NBR_CONNECT ];
872 } fore200e_t;
873
874
875
876
877 typedef struct fore200e_vcc {
878 enum buffer_scheme scheme;
879 struct tpd_rate rate;
880 int rx_min_pdu;
881 int rx_max_pdu;
882 int tx_min_pdu;
883 int tx_max_pdu;
884 unsigned long tx_pdu;
885 unsigned long rx_pdu;
886 } fore200e_vcc_t;
887
888
889
890
891
892 #define FORE200E_CP_MONITOR_OFFSET 0x00000400
893 #define FORE200E_CP_QUEUES_OFFSET 0x00004d40
894
895
896
897
898 #define PCA200E_IOSPACE_LENGTH 0x00200000
899
900 #define PCA200E_HCR_OFFSET 0x00100000
901 #define PCA200E_IMR_OFFSET 0x00100004
902 #define PCA200E_PSR_OFFSET 0x00100008
903
904
905
906
907 #define PCA200E_HCR_RESET (1<<0)
908 #define PCA200E_HCR_HOLD_LOCK (1<<1)
909 #define PCA200E_HCR_I960FAIL (1<<2)
910 #define PCA200E_HCR_INTRB (1<<2)
911 #define PCA200E_HCR_HOLD_ACK (1<<3)
912 #define PCA200E_HCR_INTRA (1<<3)
913 #define PCA200E_HCR_OUTFULL (1<<4)
914 #define PCA200E_HCR_CLRINTR (1<<4)
915 #define PCA200E_HCR_ESPHOLD (1<<5)
916 #define PCA200E_HCR_INFULL (1<<6)
917 #define PCA200E_HCR_TESTMODE (1<<7)
918
919
920
921
922 #define PCA200E_PCI_LATENCY 0x40
923 #define PCA200E_PCI_MASTER_CTRL 0x41
924 #define PCA200E_PCI_THRESHOLD 0x42
925
926
927
928 #define PCA200E_CTRL_DIS_CACHE_RD (1<<0)
929 #define PCA200E_CTRL_DIS_WRT_INVAL (1<<1)
930 #define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2)
931 #define PCA200E_CTRL_IGN_LAT_TIMER (1<<3)
932 #define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4)
933 #define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5)
934 #define PCA200E_CTRL_CONVERT_ENDIAN (1<<6)
935
936
937
938 #define SBA200E_PROM_NAME "FORE,sba-200e"
939
940
941
942
943 #define SBA200E_HCR_LENGTH 4
944 #define SBA200E_BSR_LENGTH 4
945 #define SBA200E_ISR_LENGTH 4
946 #define SBA200E_RAM_LENGTH 0x40000
947
948
949
950
951 #define SBA200E_BSR_BURST4 0x04
952 #define SBA200E_BSR_BURST8 0x08
953 #define SBA200E_BSR_BURST16 0x10
954
955
956
957
958 #define SBA200E_HCR_RESET (1<<0)
959 #define SBA200E_HCR_HOLD_LOCK (1<<1)
960 #define SBA200E_HCR_I960FAIL (1<<2)
961 #define SBA200E_HCR_I960SETINTR (1<<2)
962 #define SBA200E_HCR_OUTFULL (1<<3)
963 #define SBA200E_HCR_INTR_CLR (1<<3)
964 #define SBA200E_HCR_INTR_ENA (1<<4)
965 #define SBA200E_HCR_ESPHOLD (1<<5)
966 #define SBA200E_HCR_INFULL (1<<6)
967 #define SBA200E_HCR_TESTMODE (1<<7)
968 #define SBA200E_HCR_INTR_REQ (1<<8)
969
970 #define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)
971
972
973 #endif
974 #endif